i965/vs: Combine code generation's inst->opcode switch statements.
vec4_visitor::generate_code() switches on vec4_instruction::opcode and calls into the brw_eu_emit.c layer to generate code for some of them. It then has a default case which calls generate_vec4_instruction() to handle the rest...which switches on opcode and handles the rest of the cases. The split apparently is that generate_code() handles the actual hardware opcodes (BRW_OPCODE_*) while generate_vec4_instruction() handles the virtual opcodes (SHADER_OPCODE_* and VS_OPCODE_*). But this looks fairly arbitrary, and it makes more sense to combine the two switches. This patch moves the cases from generate_code() into the helper function so that generate_code() isn't as large. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Eric Anholt <eric@anholt.net>
This commit is contained in:
Kenneth Graunke
parent
55272883ac
commit
dd0b99b0be
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@ -621,14 +621,178 @@ vec4_generator::generate_pull_constant_load_gen7(vec4_instruction *inst,
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0);
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}
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/**
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* Generate assembly for a Vec4 IR instruction.
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*
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* \param instruction The Vec4 IR instruction to generate code for.
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* \param dst The destination register.
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* \param src An array of up to three source registers.
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*/
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void
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vec4_generator::generate_vec4_instruction(vec4_instruction *instruction,
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struct brw_reg dst,
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struct brw_reg *src)
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{
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vec4_instruction *inst = (vec4_instruction *)instruction;
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vec4_instruction *inst = (vec4_instruction *) instruction;
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switch (inst->opcode) {
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case BRW_OPCODE_MOV:
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brw_MOV(p, dst, src[0]);
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break;
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case BRW_OPCODE_ADD:
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brw_ADD(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_MUL:
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brw_MUL(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_MACH:
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brw_set_acc_write_control(p, 1);
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brw_MACH(p, dst, src[0], src[1]);
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brw_set_acc_write_control(p, 0);
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break;
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case BRW_OPCODE_MAD:
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brw_MAD(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_FRC:
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brw_FRC(p, dst, src[0]);
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break;
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case BRW_OPCODE_RNDD:
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brw_RNDD(p, dst, src[0]);
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break;
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case BRW_OPCODE_RNDE:
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brw_RNDE(p, dst, src[0]);
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break;
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case BRW_OPCODE_RNDZ:
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brw_RNDZ(p, dst, src[0]);
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break;
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case BRW_OPCODE_AND:
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brw_AND(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_OR:
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brw_OR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_XOR:
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brw_XOR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_NOT:
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brw_NOT(p, dst, src[0]);
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break;
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case BRW_OPCODE_ASR:
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brw_ASR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_SHR:
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brw_SHR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_SHL:
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brw_SHL(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_CMP:
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brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
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break;
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case BRW_OPCODE_SEL:
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brw_SEL(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_DPH:
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brw_DPH(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_DP4:
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brw_DP4(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_DP3:
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brw_DP3(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_DP2:
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brw_DP2(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_F32TO16:
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brw_F32TO16(p, dst, src[0]);
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break;
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case BRW_OPCODE_F16TO32:
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brw_F16TO32(p, dst, src[0]);
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break;
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case BRW_OPCODE_LRP:
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brw_LRP(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_BFREV:
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/* BFREV only supports UD type for src and dst. */
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brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
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retype(src[0], BRW_REGISTER_TYPE_UD));
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break;
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case BRW_OPCODE_FBH:
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/* FBH only supports UD type for dst. */
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brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
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break;
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case BRW_OPCODE_FBL:
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/* FBL only supports UD type for dst. */
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brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
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break;
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case BRW_OPCODE_CBIT:
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/* CBIT only supports UD type for dst. */
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brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
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break;
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case BRW_OPCODE_BFE:
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brw_BFE(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_BFI1:
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brw_BFI1(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_BFI2:
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brw_BFI2(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_IF:
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if (inst->src[0].file != BAD_FILE) {
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/* The instruction has an embedded compare (only allowed on gen6) */
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assert(intel->gen == 6);
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gen6_IF(p, inst->conditional_mod, src[0], src[1]);
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} else {
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struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
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brw_inst->header.predicate_control = inst->predicate;
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}
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break;
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case BRW_OPCODE_ELSE:
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brw_ELSE(p);
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break;
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case BRW_OPCODE_ENDIF:
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brw_ENDIF(p);
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break;
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case BRW_OPCODE_DO:
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brw_DO(p, BRW_EXECUTE_8);
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break;
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case BRW_OPCODE_BREAK:
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brw_BREAK(p);
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brw_set_predicate_control(p, BRW_PREDICATE_NONE);
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break;
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case BRW_OPCODE_CONTINUE:
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/* FINISHME: We need to write the loop instruction support still. */
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if (intel->gen >= 6)
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gen6_CONT(p);
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else
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brw_CONT(p);
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brw_set_predicate_control(p, BRW_PREDICATE_NONE);
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break;
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case BRW_OPCODE_WHILE:
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brw_WHILE(p);
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break;
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case SHADER_OPCODE_RCP:
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case SHADER_OPCODE_RSQ:
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case SHADER_OPCODE_SQRT:
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@ -756,168 +920,7 @@ vec4_generator::generate_code(exec_list *instructions)
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unsigned pre_emit_nr_insn = p->nr_insn;
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switch (inst->opcode) {
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case BRW_OPCODE_MOV:
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brw_MOV(p, dst, src[0]);
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break;
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case BRW_OPCODE_ADD:
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brw_ADD(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_MUL:
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brw_MUL(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_MACH:
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brw_set_acc_write_control(p, 1);
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brw_MACH(p, dst, src[0], src[1]);
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brw_set_acc_write_control(p, 0);
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break;
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case BRW_OPCODE_MAD:
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brw_MAD(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_FRC:
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brw_FRC(p, dst, src[0]);
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break;
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case BRW_OPCODE_RNDD:
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brw_RNDD(p, dst, src[0]);
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break;
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case BRW_OPCODE_RNDE:
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brw_RNDE(p, dst, src[0]);
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break;
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case BRW_OPCODE_RNDZ:
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brw_RNDZ(p, dst, src[0]);
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break;
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case BRW_OPCODE_AND:
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brw_AND(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_OR:
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brw_OR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_XOR:
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brw_XOR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_NOT:
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brw_NOT(p, dst, src[0]);
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break;
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case BRW_OPCODE_ASR:
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brw_ASR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_SHR:
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brw_SHR(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_SHL:
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brw_SHL(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_CMP:
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brw_CMP(p, dst, inst->conditional_mod, src[0], src[1]);
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break;
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case BRW_OPCODE_SEL:
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brw_SEL(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_DPH:
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brw_DPH(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_DP4:
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brw_DP4(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_DP3:
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brw_DP3(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_DP2:
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brw_DP2(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_F32TO16:
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brw_F32TO16(p, dst, src[0]);
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break;
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case BRW_OPCODE_F16TO32:
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brw_F16TO32(p, dst, src[0]);
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break;
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case BRW_OPCODE_LRP:
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brw_LRP(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_BFREV:
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/* BFREV only supports UD type for src and dst. */
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brw_BFREV(p, retype(dst, BRW_REGISTER_TYPE_UD),
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retype(src[0], BRW_REGISTER_TYPE_UD));
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break;
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case BRW_OPCODE_FBH:
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/* FBH only supports UD type for dst. */
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brw_FBH(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
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break;
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case BRW_OPCODE_FBL:
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/* FBL only supports UD type for dst. */
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brw_FBL(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
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break;
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case BRW_OPCODE_CBIT:
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/* CBIT only supports UD type for dst. */
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brw_CBIT(p, retype(dst, BRW_REGISTER_TYPE_UD), src[0]);
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break;
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case BRW_OPCODE_BFE:
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brw_BFE(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_BFI1:
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brw_BFI1(p, dst, src[0], src[1]);
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break;
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case BRW_OPCODE_BFI2:
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brw_BFI2(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_IF:
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if (inst->src[0].file != BAD_FILE) {
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/* The instruction has an embedded compare (only allowed on gen6) */
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assert(intel->gen == 6);
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gen6_IF(p, inst->conditional_mod, src[0], src[1]);
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} else {
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struct brw_instruction *brw_inst = brw_IF(p, BRW_EXECUTE_8);
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brw_inst->header.predicate_control = inst->predicate;
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}
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break;
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case BRW_OPCODE_ELSE:
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brw_ELSE(p);
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break;
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case BRW_OPCODE_ENDIF:
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brw_ENDIF(p);
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break;
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case BRW_OPCODE_DO:
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brw_DO(p, BRW_EXECUTE_8);
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break;
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case BRW_OPCODE_BREAK:
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brw_BREAK(p);
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brw_set_predicate_control(p, BRW_PREDICATE_NONE);
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break;
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case BRW_OPCODE_CONTINUE:
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/* FINISHME: We need to write the loop instruction support still. */
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if (intel->gen >= 6)
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gen6_CONT(p);
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else
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brw_CONT(p);
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brw_set_predicate_control(p, BRW_PREDICATE_NONE);
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break;
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case BRW_OPCODE_WHILE:
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brw_WHILE(p);
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break;
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default:
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generate_vec4_instruction(inst, dst, src);
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break;
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}
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generate_vec4_instruction(inst, dst, src);
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if (inst->no_dd_clear || inst->no_dd_check) {
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assert(p->nr_insn == pre_emit_nr_insn + 1 ||
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