7ba5e94c50
ac: add radeon_info::use_late_alloc to control LATE_ALLOC globally
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4143 >
2020-03-12 17:27:23 +00:00
7481c4be58
radeonsi: add a bug workaround for NGG - LATE_ALLOC_GS
...
Cc: 19.3 20.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4079 >
2020-03-09 16:08:10 -04:00
9d64ad2fe7
radeonsi: lower discard to demote when FS_CORRECT_DERIVS_AFTER_KILL is enabled
...
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4047 >
2020-03-09 12:29:32 +00:00
c046551e60
radeonsi: print shader cache stats with AMD_DEBUG=cache_stats
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929 >
2020-01-24 20:29:29 -05:00
2fd3bb23ab
radeonsi: restructure si_shader_cache_load_shader
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929 >
2020-01-24 20:29:29 -05:00
0db74f479b
radeonsi: use the live shader cache
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929 >
2020-01-24 20:29:29 -05:00
7ce84b256e
radeonsi: make si_compile_shader return bool
...
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3421 >
2020-01-23 19:10:21 +00:00
735a3ba007
radeonsi/gfx10: enable GS fast launch for triangles and strips with NGG culling
...
Only non-indexed triangle lists and strips are supported. This increases
performance if there is something to cull.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
c377f45c18
radeonsi/gfx10: rewrite late alloc computation
...
- Use conservative late alloc when the number of CUs <= 6.
- Move the late alloc GS register to the GS shader state, so that it can be
tuned for NGG culling.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
8db00a51f8
radeonsi/gfx10: implement NGG culling for 4x wave32 subgroups
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
aa2d846604
radeonsi/gfx10: move GE_PC_ALLOC setting to shader states
...
The value is not changed. I just use a different way to compute it.
The value will vary with NGG culling.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
41fef6fc09
radeonsi/gfx10: don't initialize VGPRs not used by NGG passthrough
...
v2: TES doesn't use the GS PrimitiveID
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
42112010a3
radeonsi: rename si_shader_create -> si_create_shader_variant for clarity
...
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
03950473df
radeonsi: merge si_tessctrl_info into si_shader_info
...
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
5fa2ab831e
radeonsi: fork tgsi_shader_info and tgsi_tessctrl_info
...
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
363b4027fc
radeonsi: put up to 5 VBO descriptors into user SGPRs
...
gfx6-8: 1 VBO descriptor in user SGPRs
gfx9-10: 5 VBO descriptors in user SGPRs
We no longer pull up to 5 VBO descriptors from GTT when SDMA is disabled.
Totals from affected shaders:
SGPRS: 1110528 -> 1170528 (5.40 %)
VGPRS: 952896 -> 951936 (-0.10 %)
Spilled SGPRs: 83 -> 61 (-26.51 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 23766296 -> 22843920 (-3.88 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 179344 -> 179344 (0.00 %)
Wait states: 0 -> 0 (0.00 %)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-13 15:57:07 -05:00
312e04689a
radeonsi: don't allow draw calls with uninitialized VS inputs
...
These always hang, because vertex buffer descriptors are not set up.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-13 15:57:07 -05:00
fd84e422b6
radeonsi: clean up messy si_emit_rasterizer_prim_state
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 15:48:49 -05:00
898c9cb797
radeonsi: fix context roll tracking in si_emit_shader_vs
...
probably harmless, because we don't need to track context rolls on gfx10
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 15:48:39 -05:00
420fe1e7f9
radeonsi: remove TGSI
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-06 15:57:20 -05:00
e79f55ff86
radeonsi/gfx10: improve performance for TES using PrimID but not exporting it
...
This field is really for the primitive export to the pixel shader.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-27 13:50:57 -05:00
aa3df12fc2
radeonsi/gfx10: enable NGG passthrough for eligible shaders
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-27 13:50:57 -05:00
aced18aa61
radeonsi/gfx10: simplify the tess_turns_off_ngg condition
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-10 16:32:36 -05:00
42f921387b
radeonsi/gfx10: disable vertex grouping
...
based on PAL.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-10 16:32:34 -05:00
4675cb2019
radeonsi: initialize the per-context compiler on demand
...
This takes a noticable amount of time in piglit and some tests don't
need it.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-11-25 16:48:27 -05:00
3ef50b023e
radeonsi/nir: fix compute shader crash due to nir_binary == NULL
...
This partially reverts 8b30114dda8b30114dda
2019-11-08 16:47:59 -05:00
8b30114dda
radeonsi/nir: call nir_serialize only once per shader
...
We were calling it twice.
First serialize it, then use it to compute the cache key.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-08 15:30:28 -05:00
442ef8c3e3
radeonsi: keep serialized NIR instead of nir_shader in si_shader_selector
...
This decreases memory usage, because serialized NIR is more compact.
The main shader part is compiled from nir_shader.
Monolithic shader variants are compiled from nir_binary.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-05 23:28:45 -05:00
62229e8949
radeonsi: use IR SHA1 as the cache key for the in-memory shader cache
...
instead of using whole IR binaries. This saves some memory.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-11-05 23:28:42 -05:00
4d1e43badb
radeonsi: initialize shader compilers in threads on demand
...
It takes a noticable amount of time with piglit.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-10-28 21:36:18 -04:00
fff884e09d
radeonsi/nir: implement pipe_screen::finalize_nir
...
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-23 21:12:52 -04:00
268e0e01f3
radeonsi/nir: simplify si_lower_nir signature
...
just a cleanup
2019-10-15 21:52:09 -04:00
dd4cc56ebd
nir: add a strip parameter to nir_serialize
...
so that drivers don't have to call nir_strip manually.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Rob Clark <robdclark@gmail.com>
2019-10-10 15:47:07 -04:00
743a9d85e2
radeonsi: add FMASK slots for shader images (for MSAA images)
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-10-09 17:12:31 -04:00
eec7b0a865
radeonsi: use simple_mtx_t instead of mtx_t
...
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-07 20:05:07 -04:00
896885025f
util/u_queue: track job size and limit the size of queue growth
...
When both UTIL_QUEUE_INIT_RESIZE_IF_FULL and
UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY are set, we can get into a
situation where the queue never executes and grows to a huge size
due to all other threads being busy.
This is the case with the shader cache when attempting to compile a
huge number of shaders up front. If all threads are busy compiling
shaders the cache queues memory use can climb into the many GBs
very fast.
The use of these two flags with the shader cache is intended to
allow shaders compiled at runtime to be compiled as fast as possible.
To avoid huge memory use but still allow the queue to perform
optimally in the run time compilation case, we now add the ability
to track memory consumed by the jobs in the queue and limit it to
a hardcoded 256MB which should be more than enough.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-09-19 15:03:27 +10:00
360cf3c4b0
radeonsi: fix scratch buffer WAVESIZE setting leading to corruption
...
Cc: 19.2 19.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:52:32 -04:00
40e5ac45ae
radeonsi: align scratch and ring buffer allocations for faster memory access
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:52:28 -04:00
d8f27552f4
radeonsi: consolidate determining VGPR_COMP_CNT for API VS
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:16:08 -04:00
4dde40908f
radeonsi/gfx10: set PA_CL_VS_OUT_CNTL with CONTEXT_REG_RMW to fix edge flags
...
We need two different values of the register, one for NGG and one for
legacy, in order to fix edge flags for the legacy pipeline.
Passing the ngg flag to emit_clip_regs would be too complicated,
so CONTEXT_REG_RMW is used for partial register updates.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:16:08 -04:00
1426acf9e7
radeonsi/gfx10: remove incorrect ngg/pos_writes_edgeflag variables
...
It varies depending on si_shader_key::as_ngg.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:16:08 -04:00
28f44ee533
radeonsi/gfx10: fix InstanceID for legacy VS+GS
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:16:08 -04:00
e121d75de9
radeonsi/gfx10: add as_ngg variant for VS as ES to select Wave32/64
...
Legacy GS only works with Wave64.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:16:08 -04:00
f34d023f1a
radeonsi/gfx10: create the GS copy shader if using legacy streamout
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:16:08 -04:00
776f05a307
radeonsi/gfx10: fix the PRIMITIVES_GENERATED query if using legacy streamout
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:16:08 -04:00
cab5b3861d
radeonsi/gfx10: fix tessellation for the legacy pipeline
...
ported from PAL
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:16:08 -04:00
a9bb566955
radeonsi: move some global shader cache flags to per-binary flags
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:16:08 -04:00
810846e157
radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the shader cache
...
It could load an NGG shader when we want a legacy shader and vice versa.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:16:08 -04:00
021feb1bf6
ac: add rbplus_allowed to ac_gpu_info
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-27 08:04:41 +02:00
c08401f035
ac: add has_distributed_tess to ac_gpu_info
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-27 08:04:11 +02:00
223b3174bd
radeonsi/nir: always lower ballot masks as 64-bit, codegen handles it
...
This fixes KHR-GL45.shader_ballot_tests.ShaderBallotBitmasks.
This solution is better, because the IR isn't dependent on wave32.
2019-08-19 17:23:38 -04:00
bdcbac9459
radeonsi: handle the use_ngg_streamout flag in si_update_ngg
2019-08-19 17:23:38 -04:00
a6b3ca1c70
radeonsi: move the tess factor ring size assertion to a place where it matters
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-19 17:23:38 -04:00
8ce4f9bbc3
radeonsi: remove the always_nir option
...
tgsi_to_nir is no longer optional if NIR is enabled.
2019-08-12 14:52:17 -04:00
6a2bdb8d01
gallium: add TGSI_PROPERTY_VS_BLIT_SGPRS_AMD for tgsi_to_nir
...
needed by radeonsi NIR support
2019-08-12 14:52:17 -04:00
91227a1e17
radeonsi/gfx10: add global use_ngg and use_ngg_streamout flags
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:09:02 -04:00
f064b530f6
radeonsi/gfx10: remove an obsolete VGT_REUSE_OFF workaround
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:09:01 -04:00
c5a6ecf61a
radeonsi/gfx10: implement a bug workaround for GE_PC_ALLOC
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:08:58 -04:00
8f8c28767e
radeonsi/gfx10: implement a bug workaround for NGG -> legacy transitions
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:08:57 -04:00
cb9d95623b
radeonsi/gfx10: implement a GE bug workaround
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:08:56 -04:00
71b53020b7
radeonsi/gfx10: simplify NGG code in si_update_shaders
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:08:53 -04:00
a232f5e07c
radeonsi/gfx10: fix input VGPRs for legacy VS
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:08:51 -04:00
8b8819e88a
radeonsi: make sure that DSA state != NULL and remove all NULL checking
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:08:39 -04:00
b758eed9c3
radeonsi: make sure that blend state != NULL and remove all NULL checking
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:08:39 -04:00
e777720173
radeonsi/nir: lower PS inputs before scanning the shader
...
Lowering PS inputs can eliminate some of them, which messes up
persp/linear barycentric coord usage info.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:08:46 -04:00
5f16fdefdf
radeonsi/nir: add an option to convert TGSI to NIR
...
Use at your own risk.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-07-30 22:06:23 -04:00
e718f8e713
radeonsi: simplify si_get_input_prim and remove incorrect TODO comment
...
u_vertices_per_prim(QUADS) is the same as TRIANGLES.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-23 15:03:49 -04:00
ad642d5b3a
radeonsi: stop using info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE]
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-23 15:03:46 -04:00
8f72f137ad
radeonsi/gfx10: add as_ngg variant for TES as ES to select Wave32/64
...
Legacy GS has to use Wave64, so TES before GS has to use Wave64 too.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-19 20:16:19 -04:00
88efb63caf
radeonsi/gfx10: implement Wave32
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-19 20:16:19 -04:00
d3a80f2dda
radeonsi/gfx10: remove the disable_ngg option
...
because legacy VS hangs.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-19 20:16:19 -04:00
0f30223cf4
radeonsi/gfx10: combine hw edgeflags with user edgeflags for correct behavior
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-19 20:16:19 -04:00
985a59e0d1
radeonsi/gfx10: don't compile the GS copy shader if it's 100% not needed
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-19 20:16:19 -04:00
7f0ada3f3e
radeonsi/gfx10: set GE_CTNL.PACKET_TO_ONE_PA for NGG
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-19 20:16:19 -04:00
e08463ac22
radeonsi/gfx10: update a tunable max_es_verts_base for NGG
...
We have to fix the computation so as not to break quads.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-19 20:16:19 -04:00
79d56e6a4a
radeonsi/gfx10: implement ARB_post_depth_coverage
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-19 20:16:19 -04:00
4985c3ee22
radeonsi/gfx10: set HS/GS/CS.WGP_MODE
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2019-07-09 17:24:16 -04:00
329406ec9c
radeonsi/gfx10: set GE_PC_ALLOC
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2019-07-09 17:24:16 -04:00
fbf781e401
radeonsi/gfx10: support pixel shaders without exports
...
It only works if there are not color and no Z exports.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2019-07-09 17:24:16 -04:00
2adc8e2736
radeonsi/gfx10: enable vertex shaders without param space allocation
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2019-07-09 17:24:16 -04:00
3be4ed2fe1
radeonsi: fix and clean up shader_type passing
...
- don't pass it via a parameter if it can be derived from other parameters
- set shader_type for ac_rtld_open
- use enum pipe_shader_type instead of unsigned
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2019-07-09 17:24:16 -04:00
f66ee5af2f
radeonsi: determine the rasterization primitive type accurately (v2)
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v2: reworked version to fix bugs and make it more efficient
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
a4b3eea325
radeonsi/gfx10: consolidate & improve input_prim determination for NGG
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
214ddfb688
radeonsi/gfx10: implement si_shader_vs
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Only used with tessellation + GS instancing.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
6920f09f4b
radeonsi/gfx10: fix GL_LINE polygon mode for decomposed primitives
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We need to tell PA to accept edge flags generated by the input assembler,
because decomposed primitives shouldn't draw inner edges.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
cc7875150a
radeonsi/gfx10: unbind NGG shaders when destroyed
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This fixes glsl-max-varyings, which creates shaders, draws, and then
destroys them.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
adbec817d3
radeonsi/gfx10: update spi_map if API VS (as NGG) changes and PS doesn't
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
6bcc273de8
radeonsi/gfx10: implement si_init_tess_factor_ring
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
f3b9a37278
radeonsi/gfx10: implement si_shader_hs
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
69c41fb8ff
radeonsi/gfx10: fix binding on si_update_scratch_relocs
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
1b11fb148c
radeonsi/gfx10: take PRIMID from the correct output when exported by GS
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
e0c2a4d58c
radeonsi/gfx10: implement si_shader_gs
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This is only used in the legacy, non-NGG path.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
77e715541c
radeonsi/gfx10: emit VGT_GS_OUT_PRIM_TYPE from draw and add it to VS_STATE
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With NGG, the VGT_GS_OUT_PRIM_TYPE can change without a shader change.
The VS_STATE is required for both streamout and culling from a vertex
shader without pre-compiling outprim-specific variants.
We could consider compiling specialized variants in the future. We
could also consider compiling the NGG logic as an epilog.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
4ecc39e1aa
radeonsi/gfx10: NGG geometry shader PM4 and upload
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
a04aa4be2b
radeonsi/gfx10: generate geometry shaders for NGG
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
016a465d7d
radeonsi/gfx10: implement gfx10_shader_ngg
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For pipelines without API GS. We will later expand this to cover NGG
geometry shaders as well.
Note that the vtx offset passed into the GS part is just the
vertex index multiplied by VGT_ESGS_RING_ITEMSIZE.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
1dee01ee13
radeonsi/gfx10: implement si_shader_ps
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
8ec60d3031
radeonsi/gfx10: add as_ngg shader key bit
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Also add the shader main part NGG variant, so that in principle
we can switch between legacy in NGG modes.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
40b12c0f5a
radeonsi/gfx10: implement si_update_shaders
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
5726ec0d24
radeonsi/gfx10: implement si_build_vgt_shader_config
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Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
Marek Olšák
Daniel Schürmann
Timothy Arceri
Samuel Pitoiset
Nicolai Hähnle