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radeonsi: fork tgsi_shader_info and tgsi_tessctrl_info 

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
This commit is contained in:
Marek Olšák 2020-01-10 18:06:56 -05:00
parent 18aaceae8d
commit 5fa2ab831e
12 changed files with 205 additions and 56 deletions
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12
src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
View File

@ -76,7 +76,7 @@ static void build_streamout_vertex(struct si_shader_context *ctx,
unsigned stream, LLVMValueRef offset_vtx,
LLVMValueRef vertexptr)
{
struct tgsi_shader_info *info = &ctx->shader->selector->info;
struct si_shader_info *info = &ctx->shader->selector->info;
struct pipe_stream_output_info *so = &ctx->shader->selector->so;
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef offset[4] = {};
@ -136,7 +136,7 @@ struct ngg_streamout {
static void build_streamout(struct si_shader_context *ctx,
struct ngg_streamout *nggso)
{
struct tgsi_shader_info *info = &ctx->shader->selector->info;
struct si_shader_info *info = &ctx->shader->selector->info;
struct pipe_stream_output_info *so = &ctx->shader->selector->so;
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->rw_buffers);
@ -461,7 +461,7 @@ void gfx10_emit_ngg_epilogue(struct ac_shader_abi *abi,
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct si_shader_selector *sel = ctx->shader->selector;
struct tgsi_shader_info *info = &sel->info;
struct si_shader_info *info = &sel->info;
struct si_shader_output_values outputs[PIPE_MAX_SHADER_OUTPUTS];
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef tmp, tmp2;
@ -739,7 +739,7 @@ static LLVMValueRef
ngg_gs_get_vertex_storage(struct si_shader_context *ctx)
{
const struct si_shader_selector *sel = ctx->shader->selector;
const struct tgsi_shader_info *info = &sel->info;
const struct si_shader_info *info = &sel->info;
LLVMTypeRef elements[2] = {
LLVMArrayType(ctx->ac.i32, 4 * info->num_outputs),
@ -846,7 +846,7 @@ void gfx10_ngg_gs_emit_vertex(struct si_shader_context *ctx,
LLVMValueRef *addrs)
{
const struct si_shader_selector *sel = ctx->shader->selector;
const struct tgsi_shader_info *info = &sel->info;
const struct si_shader_info *info = &sel->info;
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef tmp;
const LLVMValueRef vertexidx =
@ -945,7 +945,7 @@ void gfx10_ngg_gs_emit_prologue(struct si_shader_context *ctx)
void gfx10_ngg_gs_emit_epilogue(struct si_shader_context *ctx)
{
const struct si_shader_selector *sel = ctx->shader->selector;
const struct tgsi_shader_info *info = &sel->info;
const struct si_shader_info *info = &sel->info;
const unsigned verts_per_prim = u_vertices_per_prim(sel->gs_output_prim);
LLVMBuilderRef builder = ctx->ac.builder;
LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);

2
src/gallium/drivers/radeonsi/si_compute.c
View File

@ -126,7 +126,7 @@ static void si_create_compute_state_async(void *job, int thread_index)
assert(program->ir_type == PIPE_SHADER_IR_NIR);
si_nir_scan_shader(sel->nir, &sel->info);
/* Store the declared LDS size into tgsi_shader_info for the shader
/* Store the declared LDS size into si_shader_info for the shader
* cache to include it.
*/
sel->info.properties[TGSI_PROPERTY_CS_LOCAL_SIZE] = program->local_size;

2
src/gallium/drivers/radeonsi/si_debug.c
View File

@ -830,7 +830,7 @@ static unsigned si_identity(unsigned slot)
static void si_dump_descriptors(struct si_context *sctx,
enum pipe_shader_type processor,
const struct tgsi_shader_info *info,
const struct si_shader_info *info,
struct u_log_context *log)
{
struct si_descriptors *descs =

2
src/gallium/drivers/radeonsi/si_pipe.h
View File

@ -1646,7 +1646,7 @@ static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
return &sctx->vs_shader;
}
static inline struct tgsi_shader_info *si_get_vs_info(struct si_context *sctx)
static inline struct si_shader_info *si_get_vs_info(struct si_context *sctx)
{
struct si_shader_ctx_state *vs = si_get_vs(sctx);

36
src/gallium/drivers/radeonsi/si_shader.c
View File

@ -272,7 +272,7 @@ static LLVMValueRef get_tcs_out_patch_stride(struct si_shader_context *ctx)
if (ctx->shader->key.mono.u.ff_tcs_inputs_to_copy)
return si_unpack_param(ctx, ctx->tcs_out_lds_layout, 0, 13);
const struct tgsi_shader_info *info = &ctx->shader->selector->info;
const struct si_shader_info *info = &ctx->shader->selector->info;
unsigned tcs_out_vertices = info->properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
unsigned vertex_dw_stride = get_tcs_out_vertex_dw_stride_constant(ctx);
unsigned num_patch_outputs = util_last_bit64(ctx->shader->selector->patch_outputs_written);
@ -383,7 +383,7 @@ void si_llvm_load_input_vs(
unsigned input_index,
LLVMValueRef out[4])
{
const struct tgsi_shader_info *info = &ctx->shader->selector->info;
const struct si_shader_info *info = &ctx->shader->selector->info;
unsigned vs_blit_property = info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
if (vs_blit_property) {
@ -879,7 +879,7 @@ static LLVMValueRef si_nir_load_tcs_varyings(struct ac_shader_abi *abi,
bool load_input)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct tgsi_shader_info *info = &ctx->shader->selector->info;
struct si_shader_info *info = &ctx->shader->selector->info;
LLVMValueRef dw_addr, stride;
ubyte name, index;
@ -945,7 +945,7 @@ LLVMValueRef si_nir_load_input_tes(struct ac_shader_abi *abi,
bool load_input)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct tgsi_shader_info *info = &ctx->shader->selector->info;
struct si_shader_info *info = &ctx->shader->selector->info;
LLVMValueRef base, addr;
driver_location = driver_location / 4;
@ -1004,7 +1004,7 @@ static void si_nir_store_output_tcs(struct ac_shader_abi *abi,
unsigned writemask)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct tgsi_shader_info *info = &ctx->shader->selector->info;
struct si_shader_info *info = &ctx->shader->selector->info;
const unsigned component = var->data.location_frac;
unsigned driver_location = var->data.driver_location;
LLVMValueRef dw_addr, stride;
@ -1126,7 +1126,7 @@ static LLVMValueRef si_llvm_load_input_gs(struct ac_shader_abi *abi,
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct si_shader *shader = ctx->shader;
LLVMValueRef vtx_offset, soffset;
struct tgsi_shader_info *info = &shader->selector->info;
struct si_shader_info *info = &shader->selector->info;
unsigned semantic_name = info->input_semantic_name[input_index];
unsigned semantic_index = info->input_semantic_index[input_index];
unsigned param;
@ -2702,7 +2702,7 @@ static void si_llvm_emit_ls_epilogue(struct ac_shader_abi *abi,
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct si_shader *shader = ctx->shader;
struct tgsi_shader_info *info = &shader->selector->info;
struct si_shader_info *info = &shader->selector->info;
unsigned i, chan;
LLVMValueRef vertex_id = ac_get_arg(&ctx->ac, ctx->rel_auto_id);
LLVMValueRef vertex_dw_stride = get_tcs_in_vertex_dw_stride(ctx);
@ -2757,7 +2757,7 @@ static void si_llvm_emit_es_epilogue(struct ac_shader_abi *abi,
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct si_shader *es = ctx->shader;
struct tgsi_shader_info *info = &es->selector->info;
struct si_shader_info *info = &es->selector->info;
LLVMValueRef lds_base = NULL;
unsigned chan;
int i;
@ -2841,7 +2841,7 @@ static void si_llvm_emit_gs_epilogue(struct ac_shader_abi *abi,
LLVMValueRef *addrs)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct tgsi_shader_info UNUSED *info = &ctx->shader->selector->info;
struct si_shader_info UNUSED *info = &ctx->shader->selector->info;
assert(info->num_outputs <= max_outputs);
@ -2853,7 +2853,7 @@ static void si_llvm_emit_vs_epilogue(struct ac_shader_abi *abi,
LLVMValueRef *addrs)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct tgsi_shader_info *info = &ctx->shader->selector->info;
struct si_shader_info *info = &ctx->shader->selector->info;
struct si_shader_output_values *outputs = NULL;
int i,j;
@ -2902,7 +2902,7 @@ static void si_llvm_emit_prim_discard_cs_epilogue(struct ac_shader_abi *abi,
LLVMValueRef *addrs)
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct tgsi_shader_info *info = &ctx->shader->selector->info;
struct si_shader_info *info = &ctx->shader->selector->info;
LLVMValueRef pos[4] = {};
assert(info->num_outputs <= max_outputs);
@ -3031,7 +3031,7 @@ static void si_llvm_return_fs_outputs(struct ac_shader_abi *abi,
{
struct si_shader_context *ctx = si_shader_context_from_abi(abi);
struct si_shader *shader = ctx->shader;
struct tgsi_shader_info *info = &shader->selector->info;
struct si_shader_info *info = &shader->selector->info;
LLVMBuilderRef builder = ctx->ac.builder;
unsigned i, j, first_vgpr, vgpr;
@ -3122,7 +3122,7 @@ static void si_llvm_emit_vertex(struct ac_shader_abi *abi,
return;
}
struct tgsi_shader_info *info = &ctx->shader->selector->info;
struct si_shader_info *info = &ctx->shader->selector->info;
struct si_shader *shader = ctx->shader;
LLVMValueRef soffset = ac_get_arg(&ctx->ac, ctx->gs2vs_offset);
LLVMValueRef gs_next_vertex;
@ -4528,7 +4528,7 @@ si_generate_gs_copy_shader(struct si_screen *sscreen,
struct si_shader *shader;
LLVMBuilderRef builder;
struct si_shader_output_values outputs[SI_MAX_VS_OUTPUTS];
struct tgsi_shader_info *gsinfo = &gs_selector->info;
struct si_shader_info *gsinfo = &gs_selector->info;
int i;
@ -4809,7 +4809,7 @@ static void si_dump_shader_key(const struct si_shader *shader, FILE *f)
static void si_optimize_vs_outputs(struct si_shader_context *ctx)
{
struct si_shader *shader = ctx->shader;
struct tgsi_shader_info *info = &shader->selector->info;
struct si_shader_info *info = &shader->selector->info;
if ((ctx->type != PIPE_SHADER_VERTEX &&
ctx->type != PIPE_SHADER_TESS_EVAL) ||
@ -5117,7 +5117,7 @@ static bool si_compile_tgsi_main(struct si_shader_context *ctx,
* \param shader_out The vertex shader, or the next shader if merging LS+HS or ES+GS.
* \param key Output shader part key.
*/
static void si_get_vs_prolog_key(const struct tgsi_shader_info *info,
static void si_get_vs_prolog_key(const struct si_shader_info *info,
unsigned num_input_sgprs,
const struct si_vs_prolog_bits *prolog_key,
struct si_shader *shader_out,
@ -5157,7 +5157,7 @@ static void si_get_ps_prolog_key(struct si_shader *shader,
union si_shader_part_key *key,
bool separate_prolog)
{
struct tgsi_shader_info *info = &shader->selector->info;
struct si_shader_info *info = &shader->selector->info;
memset(key, 0, sizeof(*key));
key->ps_prolog.states = shader->key.part.ps.prolog;
@ -5306,7 +5306,7 @@ static bool si_need_ps_prolog(const union si_shader_part_key *key)
static void si_get_ps_epilog_key(struct si_shader *shader,
union si_shader_part_key *key)
{
struct tgsi_shader_info *info = &shader->selector->info;
struct si_shader_info *info = &shader->selector->info;
memset(key, 0, sizeof(*key));
key->ps_epilog.colors_written = info->colors_written;
key->ps_epilog.writes_z = info->writes_z;

160
src/gallium/drivers/radeonsi/si_shader.h
View File

@ -133,7 +133,6 @@
#include <llvm-c/Core.h> /* LLVMModuleRef */
#include <llvm-c/TargetMachine.h>
#include "tgsi/tgsi_scan.h"
#include "util/u_inlines.h"
#include "util/u_queue.h"
#include "util/simple_mtx.h"
@ -307,6 +306,157 @@ struct si_compiler_ctx_state {
bool is_debug_context;
};
struct si_shader_info {
uint num_tokens;
ubyte num_inputs;
ubyte num_outputs;
ubyte input_semantic_name[PIPE_MAX_SHADER_INPUTS]; /**< TGSI_SEMANTIC_x */
ubyte input_semantic_index[PIPE_MAX_SHADER_INPUTS];
ubyte input_interpolate[PIPE_MAX_SHADER_INPUTS];
ubyte input_interpolate_loc[PIPE_MAX_SHADER_INPUTS];
ubyte input_usage_mask[PIPE_MAX_SHADER_INPUTS];
ubyte input_cylindrical_wrap[PIPE_MAX_SHADER_INPUTS];
ubyte output_semantic_name[PIPE_MAX_SHADER_OUTPUTS]; /**< TGSI_SEMANTIC_x */
ubyte output_semantic_index[PIPE_MAX_SHADER_OUTPUTS];
ubyte output_usagemask[PIPE_MAX_SHADER_OUTPUTS];
ubyte output_streams[PIPE_MAX_SHADER_OUTPUTS];
ubyte num_system_values;
ubyte system_value_semantic_name[PIPE_MAX_SHADER_INPUTS];
ubyte processor;
uint file_mask[TGSI_FILE_COUNT]; /**< bitmask of declared registers */
uint file_count[TGSI_FILE_COUNT]; /**< number of declared registers */
int file_max[TGSI_FILE_COUNT]; /**< highest index of declared registers */
int const_file_max[PIPE_MAX_CONSTANT_BUFFERS];
unsigned const_buffers_declared; /**< bitmask of declared const buffers */
unsigned samplers_declared; /**< bitmask of declared samplers */
ubyte sampler_targets[PIPE_MAX_SHADER_SAMPLER_VIEWS]; /**< TGSI_TEXTURE_x values */
ubyte sampler_type[PIPE_MAX_SHADER_SAMPLER_VIEWS]; /**< TGSI_RETURN_TYPE_x */
ubyte num_stream_output_components[4];
ubyte input_array_first[PIPE_MAX_SHADER_INPUTS];
ubyte input_array_last[PIPE_MAX_SHADER_INPUTS];
ubyte output_array_first[PIPE_MAX_SHADER_OUTPUTS];
ubyte output_array_last[PIPE_MAX_SHADER_OUTPUTS];
unsigned array_max[TGSI_FILE_COUNT]; /**< highest index array per register file */
uint immediate_count; /**< number of immediates declared */
uint num_instructions;
uint num_memory_instructions; /**< sampler, buffer, and image instructions */
uint opcode_count[TGSI_OPCODE_LAST]; /**< opcode histogram */
/**
* If a tessellation control shader reads outputs, this describes which ones.
*/
boolean reads_pervertex_outputs;
boolean reads_perpatch_outputs;
boolean reads_tessfactor_outputs;
ubyte colors_read; /**< which color components are read by the FS */
ubyte colors_written;
boolean reads_position; /**< does fragment shader read position? */
boolean reads_z; /**< does fragment shader read depth? */
boolean reads_samplemask; /**< does fragment shader read sample mask? */
boolean reads_tess_factors; /**< If TES reads TESSINNER or TESSOUTER */
boolean writes_z; /**< does fragment shader write Z value? */
boolean writes_stencil; /**< does fragment shader write stencil value? */
boolean writes_samplemask; /**< does fragment shader write sample mask? */
boolean writes_edgeflag; /**< vertex shader outputs edgeflag */
boolean uses_kill; /**< KILL or KILL_IF instruction used? */
boolean uses_persp_center;
boolean uses_persp_centroid;
boolean uses_persp_sample;
boolean uses_linear_center;
boolean uses_linear_centroid;
boolean uses_linear_sample;
boolean uses_persp_opcode_interp_centroid;
boolean uses_persp_opcode_interp_offset;
boolean uses_persp_opcode_interp_sample;
boolean uses_linear_opcode_interp_centroid;
boolean uses_linear_opcode_interp_offset;
boolean uses_linear_opcode_interp_sample;
boolean uses_instanceid;
boolean uses_vertexid;
boolean uses_vertexid_nobase;
boolean uses_basevertex;
boolean uses_drawid;
boolean uses_primid;
boolean uses_frontface;
boolean uses_invocationid;
boolean uses_thread_id[3];
boolean uses_block_id[3];
boolean uses_block_size;
boolean uses_grid_size;
boolean uses_subgroup_info;
boolean writes_position;
boolean writes_psize;
boolean writes_clipvertex;
boolean writes_primid;
boolean writes_viewport_index;
boolean writes_layer;
boolean writes_memory; /**< contains stores or atomics to buffers or images */
boolean uses_doubles; /**< uses any of the double instructions */
boolean uses_derivatives;
boolean uses_bindless_samplers;
boolean uses_bindless_images;
boolean uses_fbfetch;
unsigned clipdist_writemask;
unsigned culldist_writemask;
unsigned num_written_culldistance;
unsigned num_written_clipdistance;
unsigned images_declared; /**< bitmask of declared images */
unsigned msaa_images_declared; /**< bitmask of declared MSAA images */
/**
* Bitmask indicating which declared image is a buffer.
*/
unsigned images_buffers;
unsigned images_load; /**< bitmask of images using loads */
unsigned images_store; /**< bitmask of images using stores */
unsigned images_atomic; /**< bitmask of images using atomics */
unsigned shader_buffers_declared; /**< bitmask of declared shader buffers */
unsigned shader_buffers_load; /**< bitmask of shader buffers using loads */
unsigned shader_buffers_store; /**< bitmask of shader buffers using stores */
unsigned shader_buffers_atomic; /**< bitmask of shader buffers using atomics */
bool uses_bindless_buffer_load;
bool uses_bindless_buffer_store;
bool uses_bindless_buffer_atomic;
bool uses_bindless_image_load;
bool uses_bindless_image_store;
bool uses_bindless_image_atomic;
/**
* Bitmask indicating which register files are accessed with
* indirect addressing. The bits are (1 << TGSI_FILE_x), etc.
*/
unsigned indirect_files;
/**
* Bitmask indicating which register files are read / written with
* indirect addressing. The bits are (1 << TGSI_FILE_x).
*/
unsigned indirect_files_read;
unsigned indirect_files_written;
unsigned dim_indirect_files; /**< shader resource indexing */
unsigned const_buffers_indirect; /**< const buffers using indirect addressing */
unsigned properties[TGSI_PROPERTY_COUNT]; /* index with TGSI_PROPERTY_ */
/**
* Max nesting limit of loops/if's
*/
unsigned max_depth;
};
struct si_tessctrl_info {
/** Whether all codepaths write tess factors in all invocations. */
bool tessfactors_are_def_in_all_invocs;
};
/* A shader selector is a gallium CSO and contains shader variants and
* binaries for one NIR program. This can be shared by multiple contexts.
*/
@ -336,8 +486,8 @@ struct si_shader_selector {
unsigned nir_size;
struct pipe_stream_output_info so;
struct tgsi_shader_info info;
struct tgsi_tessctrl_info tcs_info;
struct si_shader_info info;
struct si_tessctrl_info tcs_info;
/* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
enum pipe_shader_type type;
@ -762,9 +912,9 @@ void si_shader_binary_clean(struct si_shader_binary *binary);
/* si_shader_nir.c */
void si_nir_scan_shader(const struct nir_shader *nir,
struct tgsi_shader_info *info);
struct si_shader_info *info);
void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
struct tgsi_tessctrl_info *out);
struct si_tessctrl_info *out);
void si_nir_adjust_driver_locations(struct nir_shader *nir);
void si_finalize_nir(struct pipe_screen *screen, void *nirptr, bool optimize);

2
src/gallium/drivers/radeonsi/si_shader_llvm.c
View File

@ -155,7 +155,7 @@ void si_llvm_context_set_ir(struct si_shader_context *ctx,
struct si_shader *shader)
{
struct si_shader_selector *sel = shader->selector;
const struct tgsi_shader_info *info = &sel->info;
const struct si_shader_info *info = &sel->info;
ctx->shader = shader;
ctx->type = sel->type;

18
src/gallium/drivers/radeonsi/si_shader_nir.c
View File

@ -128,7 +128,7 @@ static void gather_usage(const nir_deref_instr *deref,
static void gather_intrinsic_load_deref_input_info(const nir_shader *nir,
const nir_intrinsic_instr *instr,
const nir_deref_instr *deref,
struct tgsi_shader_info *info)
struct si_shader_info *info)
{
switch (nir->info.stage) {
case MESA_SHADER_VERTEX:
@ -141,7 +141,7 @@ static void gather_intrinsic_load_deref_input_info(const nir_shader *nir,
static void gather_intrinsic_load_deref_output_info(const nir_shader *nir,
const nir_intrinsic_instr *instr,
nir_variable *var,
struct tgsi_shader_info *info)
struct si_shader_info *info)
{
assert(var && var->data.mode == nir_var_shader_out);
@ -167,7 +167,7 @@ static void gather_intrinsic_load_deref_output_info(const nir_shader *nir,
static void gather_intrinsic_store_deref_output_info(const nir_shader *nir,
const nir_intrinsic_instr *instr,
const nir_deref_instr *deref,
struct tgsi_shader_info *info)
struct si_shader_info *info)
{
switch (nir->info.stage) {
case MESA_SHADER_VERTEX: /* needed by LS, ES */
@ -181,7 +181,7 @@ static void gather_intrinsic_store_deref_output_info(const nir_shader *nir,
}
static void scan_instruction(const struct nir_shader *nir,
struct tgsi_shader_info *info,
struct si_shader_info *info,
nir_instr *instr)
{
if (instr->type == nir_instr_type_alu) {
@ -431,7 +431,7 @@ static void scan_instruction(const struct nir_shader *nir,
}
void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
struct tgsi_tessctrl_info *out)
struct si_tessctrl_info *out)
{
memset(out, 0, sizeof(*out));
@ -445,7 +445,7 @@ void si_nir_scan_tess_ctrl(const struct nir_shader *nir,
static void scan_output_slot(const nir_variable *var,
unsigned var_idx,
unsigned component, unsigned num_components,
struct tgsi_shader_info *info)
struct si_shader_info *info)
{
assert(component + num_components <= 4);
assert(component < 4);
@ -545,7 +545,7 @@ static void scan_output_slot(const nir_variable *var,
static void scan_output_helper(const nir_variable *var,
unsigned location,
const struct glsl_type *type,
struct tgsi_shader_info *info)
struct si_shader_info *info)
{
if (glsl_type_is_struct(type) || glsl_type_is_interface(type)) {
for (unsigned i = 0; i < glsl_get_length(type); i++) {
@ -591,7 +591,7 @@ static void scan_output_helper(const nir_variable *var,
}
void si_nir_scan_shader(const struct nir_shader *nir,
struct tgsi_shader_info *info)
struct si_shader_info *info)
{
nir_function *func;
unsigned i;
@ -1158,7 +1158,7 @@ static void bitcast_inputs(struct si_shader_context *ctx,
bool si_nir_build_llvm(struct si_shader_context *ctx, struct nir_shader *nir)
{
struct tgsi_shader_info *info = &ctx->shader->selector->info;
struct si_shader_info *info = &ctx->shader->selector->info;
if (nir->info.stage == MESA_SHADER_VERTEX) {
uint64_t processed_inputs = 0;

2
src/gallium/drivers/radeonsi/si_state.c
View File

@ -779,7 +779,7 @@ static void si_emit_clip_regs(struct si_context *sctx)
{
struct si_shader *vs = si_get_vs_state(sctx);
struct si_shader_selector *vs_sel = vs->selector;
struct tgsi_shader_info *info = &vs_sel->info;
struct si_shader_info *info = &vs_sel->info;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
unsigned window_space =
info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];

2
src/gallium/drivers/radeonsi/si_state.h
View File

@ -604,7 +604,7 @@ void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
struct util_queue_fence *ready_fence,
struct si_compiler_ctx_state *compiler_ctx_state,
void *job, util_queue_execute_func execute);
void si_get_active_slot_masks(const struct tgsi_shader_info *info,
void si_get_active_slot_masks(const struct si_shader_info *info,
uint32_t *const_and_shader_buffers,
uint64_t *samplers_and_images);
int si_shader_select_with_key(struct si_screen *sscreen,

20
src/gallium/drivers/radeonsi/si_state_shaders.c
View File

@ -335,7 +335,7 @@ static void si_set_tesseval_regs(struct si_screen *sscreen,
const struct si_shader_selector *tes,
struct si_pm4_state *pm4)
{
const struct tgsi_shader_info *info = &tes->info;
const struct si_shader_info *info = &tes->info;
unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
@ -1105,11 +1105,11 @@ static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ng
static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
{
const struct si_shader_selector *gs_sel = shader->selector;
const struct tgsi_shader_info *gs_info = &gs_sel->info;
const struct si_shader_info *gs_info = &gs_sel->info;
enum pipe_shader_type gs_type = shader->selector->type;
const struct si_shader_selector *es_sel =
shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
const struct tgsi_shader_info *es_info = &es_sel->info;
const struct si_shader_info *es_info = &es_sel->info;
enum pipe_shader_type es_type = es_sel->type;
unsigned num_user_sgprs;
unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
@ -1354,7 +1354,7 @@ static void si_emit_shader_vs(struct si_context *sctx)
static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
struct si_shader_selector *gs)
{
const struct tgsi_shader_info *info = &shader->selector->info;
const struct si_shader_info *info = &shader->selector->info;
struct si_pm4_state *pm4;
unsigned num_user_sgprs, vgpr_comp_cnt;
uint64_t va;
@ -1492,7 +1492,7 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
static unsigned si_get_ps_num_interp(struct si_shader *ps)
{
struct tgsi_shader_info *info = &ps->selector->info;
struct si_shader_info *info = &ps->selector->info;
unsigned num_colors = !!(info->colors_read & 0x0f) +
!!(info->colors_read & 0xf0);
unsigned num_interp = ps->selector->info.num_inputs +
@ -1554,7 +1554,7 @@ static void si_emit_shader_ps(struct si_context *sctx)
static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
{
struct tgsi_shader_info *info = &shader->selector->info;
struct si_shader_info *info = &shader->selector->info;
struct si_pm4_state *pm4;
unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
@ -2425,7 +2425,7 @@ static int si_shader_select(struct pipe_context *ctx,
&key, -1, false);
}
static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
static void si_parse_next_shader_property(const struct si_shader_info *info,
bool streamout,
struct si_shader_key *key)
{
@ -2653,7 +2653,7 @@ void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
}
/* Return descriptor slot usage masks from the given shader info. */
void si_get_active_slot_masks(const struct tgsi_shader_info *info,
void si_get_active_slot_masks(const struct si_shader_info *info,
uint32_t *const_and_shader_buffers,
uint64_t *samplers_and_images)
{
@ -3311,7 +3311,7 @@ static unsigned si_get_ps_input_cntl(struct si_context *sctx,
struct si_shader *vs, unsigned name,
unsigned index, unsigned interpolate)
{
struct tgsi_shader_info *vsinfo = &vs->selector->info;
struct si_shader_info *vsinfo = &vs->selector->info;
unsigned j, offset, ps_input_cntl = 0;
if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
@ -3370,7 +3370,7 @@ static void si_emit_spi_map(struct si_context *sctx)
{
struct si_shader *ps = sctx->ps_shader.current;
struct si_shader *vs = si_get_vs_state(sctx);
struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
struct si_shader_info *psinfo = ps ? &ps->selector->info : NULL;
unsigned i, num_interp, num_written = 0, bcol_interp[2];
unsigned spi_ps_input_cntl[32];

3
src/gallium/drivers/radeonsi/si_state_viewport.c
View File

@ -24,7 +24,6 @@
#include "si_build_pm4.h"
#include "util/u_viewport.h"
#include "tgsi/tgsi_scan.h"
#define SI_MAX_SCISSOR 16384
@ -487,7 +486,7 @@ static void si_emit_viewport_states(struct si_context *ctx)
*/
void si_update_vs_viewport_state(struct si_context *ctx)
{
struct tgsi_shader_info *info = si_get_vs_info(ctx);
struct si_shader_info *info = si_get_vs_info(ctx);
bool vs_window_space;
if (!info)