radeonsi: move some global shader cache flags to per-binary flags
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
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810846e157
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a9bb566955
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@ -147,7 +147,7 @@ static void si_create_compute_state_async(void *job, int thread_index)
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program->num_cs_user_data_dwords =
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sel->info.properties[TGSI_PROPERTY_CS_USER_DATA_COMPONENTS_AMD];
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void *ir_binary = si_get_ir_binary(sel, false);
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void *ir_binary = si_get_ir_binary(sel, false, false);
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/* Try to load the shader from the shader cache. */
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mtx_lock(&sscreen->shader_cache_mutex);
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@ -871,22 +871,9 @@ static void si_disk_cache_create(struct si_screen *sscreen)
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disk_cache_format_hex_id(cache_id, sha1, 20 * 2);
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/* These flags affect shader compilation. */
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#define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
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DBG(SI_SCHED) | \
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DBG(GISEL) | \
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DBG(W32_GE) | \
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DBG(W32_PS) | \
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DBG(W32_CS) | \
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DBG(W64_GE) | \
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DBG(W64_PS) | \
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DBG(W64_CS))
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#define ALL_FLAGS (DBG(SI_SCHED) | DBG(GISEL))
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uint64_t shader_debug_flags = sscreen->debug_flags & ALL_FLAGS;
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if (sscreen->options.enable_nir) {
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STATIC_ASSERT((ALL_FLAGS & (1u << 31)) == 0);
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shader_debug_flags |= 1u << 31;
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}
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/* Add the high bits of 32-bit addresses, which affects
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* how 32-bit addresses are expanded to 64 bits.
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*/
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@ -573,7 +573,7 @@ si_compute_fast_udiv_info32(uint32_t D, unsigned num_bits);
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void si_emit_dpbb_state(struct si_context *sctx);
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/* si_state_shaders.c */
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void *si_get_ir_binary(struct si_shader_selector *sel, bool as_ngg);
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void *si_get_ir_binary(struct si_shader_selector *sel, bool ngg, bool es);
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bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
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struct si_shader *shader);
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bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
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@ -45,7 +45,7 @@
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* Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
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* size as integer.
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*/
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void *si_get_ir_binary(struct si_shader_selector *sel, bool as_ngg)
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void *si_get_ir_binary(struct si_shader_selector *sel, bool ngg, bool es)
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{
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struct blob blob;
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unsigned ir_size;
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@ -64,13 +64,27 @@ void *si_get_ir_binary(struct si_shader_selector *sel, bool as_ngg)
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ir_size = blob.size;
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}
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/* These settings affect the compilation, but they are not derived
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* from the input shader IR.
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*/
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unsigned shader_variant_flags = 0;
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if (ngg)
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shader_variant_flags |= 1 << 0;
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if (sel->nir)
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shader_variant_flags |= 1 << 1;
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if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
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shader_variant_flags |= 1 << 2;
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if (sel->force_correct_derivs_after_kill)
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shader_variant_flags |= 1 << 3;
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unsigned size = 4 + 4 + ir_size + sizeof(sel->so);
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char *result = (char*)MALLOC(size);
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if (!result)
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return NULL;
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((uint32_t*)result)[0] = size;
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((uint32_t*)result)[1] = as_ngg;
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((uint32_t*)result)[1] = shader_variant_flags;
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memcpy(result + 8, ir_binary, ir_size);
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memcpy(result + 8 + ir_size, &sel->so, sizeof(sel->so));
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@ -2462,8 +2476,10 @@ static void si_init_shader_selector_async(void *job, int thread_index)
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sel->type == PIPE_SHADER_GEOMETRY))
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shader->key.as_ngg = 1;
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if (sel->tokens || sel->nir)
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ir_binary = si_get_ir_binary(sel, shader->key.as_ngg);
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if (sel->tokens || sel->nir) {
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ir_binary = si_get_ir_binary(sel, shader->key.as_ngg,
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shader->key.as_es);
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}
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/* Try to load the shader from the shader cache. */
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mtx_lock(&sscreen->shader_cache_mutex);
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