radeonsi/gfx10: implement si_shader_gs
This is only used in the legacy, non-NGG path. Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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@ -866,22 +866,36 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
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else
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num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
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si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
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si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
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if (sscreen->info.chip_class >= GFX10) {
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si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
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si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
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} else {
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si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
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si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
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}
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si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
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S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
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S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
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S_00B228_DX10_CLAMP(1) |
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S_00B228_FLOAT_MODE(shader->config.float_mode) |
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S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
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si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
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S_00B22C_USER_SGPR(num_user_sgprs) |
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S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5) |
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S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
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S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
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S_00B22C_LDS_SIZE(shader->config.lds_size) |
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S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
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uint32_t rsrc1 =
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S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
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S_00B228_DX10_CLAMP(1) |
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S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
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S_00B228_FLOAT_MODE(shader->config.float_mode) |
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S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
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uint32_t rsrc2 =
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S_00B22C_USER_SGPR(num_user_sgprs) |
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S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
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S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
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S_00B22C_LDS_SIZE(shader->config.lds_size) |
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S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
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if (sscreen->info.chip_class >= GFX10) {
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rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
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} else {
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rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
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rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
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}
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si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
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si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
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shader->ctx_reg.gs.vgt_gs_onchip_cntl =
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S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
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