Commit Graph

87651 Commits

Author SHA1 Message Date
Marek Olšák cdaaf66566 gallium: remove TGSI opcode BREAKC
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:33:48 +02:00
Marek Olšák 985e6b5ef9 gallium: remove TGSI opcode XPD
use MUL+MAD+MOV instead.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 3e2ff8fade gallium: remove TGSI opcode DPH
use DP4 or DP3 + ADD.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 86e6f7a73b gallium: remove TGSI opcode DP2A
use DP3 instead.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 0bb367830a gallium: remove TGSI_OPCODE_CALLNZ
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 068c3ad2cb gallium: remove TGSI FENCE opcodes
use MEMBAR instead

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 44716655e6 gallium: remove TGSI opcodes PUSHA, POPA, SAD, TXQ_LZ
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 8dadb07790 radeonsi: emit VGT_REUSE_OFF in the right place
clip_regs aren't marked dirty when writes_viewport_index is changed.

Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák a6fed63f27 radeonsi: add support for TGSI opcodes DCEIL, DFLR, DROUND, DSSG, DTRUNC
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák addd48194a radeonsi: use a faster version of PK2H
+ 4 piglit regressions, but it's correct accorcing to the GL spec and
performance is more important than piglit.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák dc2ac03669 radeonsi: don't decompress Z/S if there is no HTILE
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák e96259fabe gallium/radeon: add helpers for whether HTILE is enabled
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 7dec48b81e radeonsi/gfx9: don't flush L2 metadata for DB if not needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák aa64e24cb1 radeonsi/gfx9: don't flush L2 metadata for CB if not needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 5b62eb237c radeonsi/gfx9: don't flush TC L2 between rendering and texturing if not needed
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 287b0a28f4 radeonsi/gfx9: use correct TC flush flags when invalidating CB & DB
Now we can finally stop flushing L2 data.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 759526813b ac/surface/gfx9: don't allow DCC for the smallest mipmap levels
This fixes garbage there if we don't flush TC L2 after rendering.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 54c2c771bd radeonsi/gfx9: don't use GS scenario A for VS writing ViewportIndex
Vulkan doesn't do it anymore.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 776fcccabf gallium/radeon: clean up EOP_DATA_SEL magic numbers
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák a57f588fa9 radeonsi/gfx9: set 'not a query' for r600_gfx_write_event_eop correctly
0 is PIPE_QUERY_OCCLUSION_COUNTER, which is not what we want.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák a65afda768 radeonsi/gfx9: prevent shader-db crashes
- don't precompile LS and ES (they don't exist on GFX9), compile as VS instead
- don't precompile HS and GS (we don't have LS and ES parts)

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák fdef2f0fd1 radeonsi/gfx9: properly handle imported textures with unexpected swizzle mode
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 113278ee79 radeonsi: remove Constant Engine support
We have come to the conclusion that it doesn't improve performance.

Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 166823bfd2 radeonsi/gfx9: add a temporary workaround for a tessellation driver bug
The workaround will do for now. The root cause is still unknown.

This fixes new piglit: 16in-1out

Cc: 17.1 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Marek Olšák 248555ed2f glsl_to_tgsi: clean up opcode translation
An island of beauty in the middle of chaos.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-22 13:29:47 +02:00
Timothy Arceri da28280544 mesa: pass ctx to add_uniform_to_shader constructor
Fixes: 4c2422067b ("glsl: pass UseSTD430AsDefaultPacking to where it will be used")

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-08-22 21:25:55 +10:00
Gwan-gyeong Mun 640b6e607c egl: deduplicate allocations of local buffer over each platform backend (v2)
platform_drm, platform_wayland and platform_android have similiar local buffer
allocation routines. For deduplicating, it unifies dri2_egl_surface's
local buffer allocation routines. And it polishes inconsistent indentations.

Note that as dri2_wl_get_buffers_with_format() have not make a __DRI_BUFFER_BACK_LEFT
attachment buffer for local_buffers, new helper function, dri2_egl_surface_free_local_buffers(),
will drop the __DRI_BUFFER_BACK_LEFT check.
So if other platforms use new helper functions, we have to ensure not to make
__DRI_BUFFER_BACK_LEFT attachment buffer for local_buffers.

v2: Fixes from Emil's review:
   a) Make local_buffers variable, dri2_egl_surface_alloc_local_buffer() and
      dri2_egl_surface_free_local_buffers() unconditionally.
   b) Preserve the original codeflow for error_path and normal_path.
   c) Add note on commit messages for dropping of __DRI_BUFFER_BACK_LEFT check.
   c) Rollback the unrelated whitespace changes.
   d) Add a missing blank line.

Signed-off-by: Mun Gwan-gyeong <elongbug@gmail.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
2017-08-22 12:10:15 +01:00
Samuel Pitoiset 46a8c4ef81 mesa: only expose EXT_memory_object functions if the ext is supported
They should not be exposed when the extension is unsupported.
Note that ARB_direct_state_access is always exposed and
EXT_semaphore is not supported at all.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:54:32 +02:00
Samuel Pitoiset 44cd9aeeec mesa: only expose glImportMemoryFdEXT if the ext is supported
From the EXT_external_objects_fd spec:

   "If the GL_EXT_memory_object_fd string is reported, the following
    commands are added:

    void ImportMemoryFdEXT(uint memory,
                           uint64 size,
                           enum handleType,
                           int fd);"

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:54:29 +02:00
Samuel Pitoiset 39a35eb0c1 radeonsi: try to re-use previously deleted bindless descriptor slots
Currently, when the array is full it is resized but it can grow
over and over because we don't try to re-use descriptor slots.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:37 +02:00
Samuel Pitoiset c2dfa9b111 radeonsi: use slot indexes for bindless handles
Using VRAM address as bindless handles is not a good idea because
we have to use LLVMIntToPTr and the LLVM CSE pass can't optimize
because it has no information about the pointer.

Instead, use slots indexes like the existing descriptors. Note
that we use fixed 16-dword slots for both samplers and images.
This doesn't really matter because no real apps use image handles.

This improves performance with DOW3 by +7%.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:29 +02:00
Samuel Pitoiset 50349f404d radeonsi: add si_emit_global_shader_pointers() helper
To share common code between rw buffers and bindless descriptors.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:24 +02:00
Samuel Pitoiset a5ff4a8e2e radeonsi: only initialize dirty_mask when CE is used
Looks like it's useless to initialize that field when CE is
unused. This will also allow to declare more than 64 elements
for the array of bindless descriptors.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:23 +02:00
Samuel Pitoiset a29ef75565 radeonsi: make some si_descriptors fields 32-bit
The number of bindless descriptors is dynamic and we definitely
have to support more than 256 slots.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:21 +02:00
Samuel Pitoiset 781a13c475 radeonsi: declare new user SGPR indices for bindless samplers/images
A new pair of user SGPR is needed for loading the bindless
descriptors from shaders. Because the descriptors are global for
all stages, there is no need to add separate indices for GFX9.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:15 +02:00
Samuel Pitoiset e2793def40 gallium/util: add new module that allocate "numbers"
Will be used for allocating bindless descriptor slots for
RadeonSI.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:34:04 +02:00
Nicolai Hähnle 472c906d9f radeonsi/gfx9: add performance counters
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:55:16 +02:00
Nicolai Hähnle e271607668 radeonsi: extract common code of si_upload_{graphics,compute}_shader_descriptors
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:55:05 +02:00
Nicolai Hähnle a6e7693882 gallium: remove unused PIPE_DUMP_* defines
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:53:35 +02:00
Nicolai Hähnle 635a930ad3 ddebug: remove dd_draw_record::driver_state_log
It is no longer used.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:53:35 +02:00
Nicolai Hähnle f4c1d5a76d radeonsi: emit string markers to log context
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:53:34 +02:00
Nicolai Hähnle 0c3f8aca7f radeonsi: log decompress blits
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:53:34 +02:00
Nicolai Hähnle 420c438589 radeonsi: log draw and compute state into log context
Also add missing trace emits and CS logging for compute launches.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:53:34 +02:00
Nicolai Hähnle 4c3f36ec6b radeonsi: print saved CS to the log context
Use the auto logger facility, so that CS chunks will be interleaved
with other log info.

v2:
- fix some crashes when not using CE
- fix skipping "previous" chunks of current (unflushed) IB
- fix error handling in si_begin_cs_debug

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:53:14 +02:00
Nicolai Hähnle bc93339799 radeonsi: start using u_log_context for debugging
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:51:00 +02:00
Nicolai Hähnle ad33f2ddd8 radeonsi: re-order debug state dumping
Keep together the parts that won't use the deferred logging mechanism.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:57 +02:00
Nicolai Hähnle 40697e8678 radeonsi: make si_shader_selector_reference globally visible
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:55 +02:00
Nicolai Hähnle 4bbf6ded20 radeonsi: add reference count to si_compute
To allow keep-alive for deferred logging.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:53 +02:00
Nicolai Hähnle bbaad18c04 radeonsi: implement pipe_context::set_log_context
We'll add radeonsi-specific code to set_log_context in later patches,
but we may want to log from common code. Hence keep the log pointer
in r600_common_context.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:48 +02:00
Nicolai Hähnle fbbb5f71cd amd/common: split out ac_parse_ib_chunk from ac_parse_ib
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:46 +02:00
Nicolai Hähnle 81d7577d48 ddebug: add driver log to record dumps
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:44 +02:00
Nicolai Hähnle 1966d9ff41 gallium: add pipe_context::set_log_context
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:42 +02:00
Nicolai Hähnle 177144cefc util/log: add auto logger facility
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:40 +02:00
Nicolai Hähnle 1cc2fd57d1 util: add chunk logging module
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 09:50:31 +02:00
Ian Romanick b3a481779b glsl/linker: Make several functions not static
copy_constant_to_storage, set_uniform_initializer,
populate_consumer_input_sets, and get_matching_input are all used by
tests in src/compiler/glsl/tests:

glsl/tests/varyings_test.o: In function `link_varyings_single_simple_input_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:131: undefined reference to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)'
glsl/tests/varyings_test.o: In function `link_varyings_gl_ClipDistance_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:159: undefined reference to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)'
glsl/tests/varyings_test.o: In function `link_varyings_gl_CullDistance_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:186: undefined reference to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)'
glsl/tests/varyings_test.o: In function `link_varyings_single_interface_input_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:208: undefined reference to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)'
glsl/tests/varyings_test.o: In function `link_varyings_one_interface_and_one_simple_input_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:241: undefined reference to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)'
glsl/tests/varyings_test.o:src/compiler/glsl/tests/varyings_test.cpp:272: more undefined references to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)' follow
glsl/tests/varyings_test.o: In function `link_varyings_interface_field_doesnt_match_noninterface_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:289: undefined reference to `linker::get_matching_input(void*, ir_variable const*, hash_table*, hash_table*, ir_variable**)'
glsl/tests/varyings_test.o: In function `link_varyings_interface_field_doesnt_match_noninterface_vice_versa_Test::TestBody()':
src/compiler/glsl/tests/varyings_test.cpp:314: undefined reference to `linker::populate_consumer_input_sets(void*, exec_list*, hash_table*, hash_table*, ir_variable**)'
src/compiler/glsl/tests/varyings_test.cpp:328: undefined reference to `linker::get_matching_input(void*, ir_variable const*, hash_table*, hash_table*, ir_variable**)'

Fixes: ca73c3358c ("glsl: Mark functions static")

Signed-off-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-08-22 17:43:40 +10:00
Jason Ekstrand 0ae9ce0f29 i965/clear: Quantize the depth clear value based on the format
In f9fd976e8a we changed the clear value to be stored as an
isl_color_value.  This had the side-effect same clear value check is now
happening directly between the f32[0] field of the isl_color_value and
ctx->Depth.Clear.  This isn't what we want for two reasons.  One is that
the comparison happens in floating point even for Z16 and Z24 formats.
Worse than that, ctx->Depth.Clear is a double so, even for 32-bit float
formats, we were comparing as doubles and not floats.  This means that
the test basically always fails for anything other than 0.0f and 1.0f.
This caused a slight performance regression in Lightsmark 2008 because
it was using a depth clear value of 0.999 which can't be stored in a
32-bit float so we were doing unneeded resolves.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/101678
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
2017-08-21 22:18:53 -07:00
Timothy Arceri 3c9ed70d92 mesa/st: simplify some UBO index logic
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 13:32:21 +10:00
Timothy Arceri 36431cf979 i965: enable STD430 packing by default on IVB+
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-22 11:29:27 +10:00
Timothy Arceri 4c2422067b glsl: pass UseSTD430AsDefaultPacking to where it will be used
Here we also make use of the UseSTD430AsDefaultPacking constant
and call the new get_internal_ifc_packing() helper.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:29:27 +10:00
Timothy Arceri 12e1f0c696 glsl: add get_internal_ifc_packing() type helper
This is used to avoid code duplication when selecting the
packing type for shared and packed layouts.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:29:27 +10:00
Timothy Arceri 334a27afa7 mesa: add UseSTD430AsDefaultPacking constant
This will be used to enable the STD430 layout as the default for
UBOs and SSBOs with layouts of shared/packed rather than STD140.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 11:29:27 +10:00
Aaron Watry 5e253fe338 clover/device: Calculate CL_DEVICE_MEM_BASE_ADDR_ALIGN in device
The CL CTS queries CL_DEVICE_MEM_BASE_ADDR_ALIGN for a device and
then allocates user pointers aligned to that value for its tests.

The minimum value is defined as:
  the size (in bits) of the largest OpenCL built-in data type supported
  by the device (long16 in FULL profile, long16 or int16 in EMBEDDED
  profile) for devices that are not of type CL_DEVICE_TYPE_CUSTOM.

At the moment, all known devices that support user pointers require
CPU page alignment for buffers created from user pointers, so just
query that from sysconf.

v3: Use std::max instead of MAX2 (Francisco)
    Add missing unistd include
v2: Use system page size instead of a new pipe cap

Signed-off-by: Aaron Watry <awatry@gmail.com>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Reviewed-by (v2): Jan Vesely <jan.vesely@rutgers.edu>
2017-08-21 20:21:52 -05:00
Brian Paul 19e9bd4c11 mesa: optimize _mesa_attr_zero_aliases_vertex()
After the context is initialized, the API and context flags won't
change.  So, we can compute whether vertex attribute 0 aliases
vertex position just once.

This should make the glVertexAttrib*() functions a little quicker.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-21 19:04:51 -06:00
Brian Paul 0ef5aa4128 vbo: use new _is_vertex_position() helper in vbo_attrib_tmp.h
Makes the code a bit more understandable.

Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-21 19:04:51 -06:00
Brian Paul 1850256172 vbo: make vbo_bind_arrays() static
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-21 19:04:51 -06:00
Brian Paul 4d2b21a326 svga: replace gotos with conditionals in array drawing code
No Piglit regressions.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-08-21 19:04:51 -06:00
Brian Paul d50b8b91d7 llvmpipe: add some whitespace between functions in lp_texture.c
Trivial.
2017-08-21 19:04:51 -06:00
Brian Paul 84509779a9 mesa: formatting clean-up in syncobj.c
Line wrap to 78 columns, etc.  Trivial.
2017-08-21 19:04:51 -06:00
Brian Paul 196a0b28a0 svga: whitespace clean-up in svga_draw_private.h
Trivial.
2017-08-21 19:04:51 -06:00
Timothy Arceri 6fceace7bf gallium/docs: remove old llvmpipe TODO
Features are already covered by features.txt like all the other
drivers.

Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-08-22 11:03:08 +10:00
Timothy Arceri a4635c84dc mesa: fix ES only draw if we have vertex positions
This code was separated from the validation code so it could
use used with KHR_no_error paths. The return values were inverted
to reflect the name of the helper, but here the condtion was
mistakenly inverted rather than the return value.

Fixes: 4df2931a87 (mesa/vbo: move some Draw checks out of validation)

Reported-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-22 10:42:18 +10:00
Matt Turner 91b8d874da glsl: Add prototype for udivmod64()
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-08-21 14:45:44 -07:00
Matt Turner ca73c3358c glsl: Mark functions static
Cuts 3224 bytes of .text

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-08-21 14:45:44 -07:00
Matt Turner d37d9f84ac i965: Mark functions static
Cuts 300 bytes of .text

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-08-21 14:45:44 -07:00
Matt Turner f30902629c i965/vec4: Use 'class' src_reg, rather than 'struct' src_reg
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-08-21 14:45:44 -07:00
Matt Turner a77d5b28ac i965/vec4: Return float from spill_cost_for_type()
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
2017-08-21 14:45:44 -07:00
Matt Turner 76f36607b0 anv: Move clamp_int64() inside the IVB check
It's only used in the gen7_cmd_buffer_emit_scissor() function.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-08-21 14:45:44 -07:00
Matt Turner ee2f7aa03b glsl: Remove unused private fields
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-08-21 14:45:44 -07:00
Matt Turner 384e27174d mesa: Don't compare unsigned for < 0
The INTEL_performance_query spec says

   "Performance counter id 0 is reserved as an invalid counter."

GLuint counterid_to_index(GLuint counterid) just returns counterid - 1,
so with unsigned overflow rules, it will generate 0xFFFFFFFF given an
input of 0. 0xFFFFFFFF will trigger the counterIndex >= queryNumCounters
check, so the code worked as is. It just contained a useless comparison.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-08-21 14:45:44 -07:00
Matt Turner 4e97084591 egl: Fix inclusion of egl.h+mesa_glinterop.h
Previously clang would warn about redefinition of typedef EGLDisplay. Avoid
this by adding preprocessor guards to mesa_glinterop.h and including it
after EGL.h is indirectly included.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-08-21 14:45:44 -07:00
Marek Olšák db039d67aa radeonsi: don't prefetch VBO descriptors if vertex elements == NULL
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2017-08-21 23:06:42 +02:00
Marek Olšák ea1b97714d r600g: don't set up and don't call the fetch shader if there are no VS inputs 2017-08-21 23:06:42 +02:00
Matt Turner a98b1a8922 i965: Optimize reading the destination type
brw_hw_type_to_reg_type() needs to know only whether the file is
BRW_IMMEDIATE_VALUE or not, which is not a valid file for the
destination. gcc and clang will evaluate __builtin_strcmp() at compile
time, so we can use it to pass a constant file for the destination.

   text	   data	    bss	    dec	    hex	filename
7816214	 346248	 420496	8582958	 82f72e	i965_dri.so before
7816070	 346248	 420496	8582814	 82f69e	i965_dri.so after

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 91ef949054 i965: Mark brw_hw_type_to_reg_type() as a pure function
text	   data	    bss	    dec	    hex	filename
7816886	 346248	 420496	8583630	 82f9ce	i965_dri.so before
7816214	 346248	 420496	8582958	 82f72e	i965_dri.so after

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner e07fe89035 i965: Hide the register type hardware encodings
So we stop mixing them with the logical enum.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 4fab67a441 i965: Stop using hardware register types directly
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner c746f1c888 i965: Add brw_hw_reg_type_to_letters() and use it in brw_disasm.c
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 6a2471b501 i965: Move brw_reg_type_letters() as well
And add "to_" to the name for consistency with the other functions in
this file.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 1cb0a7941b i965: Switch to using the logical register types
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner cb2cd462b1 i965: Add functions to abstract access to register types
Previously the brw_inst{,_set}_{dst,src0,src1}_reg_type() functions
provided access to the hardware encodings for the register types. We
often mixed these with the logical BRW_REGISTER_TYPE_* enums (which
themselves used to be the hardware format!) with bad results.

With that functionality now available with the hw_ versions (see
previous commit), we now add functions that take the logical
BRW_REGISTER_TYPE_* enums and convert into the hardware format and vice
versa. To do the conversion we also have to provide the file.

Note the asymmetry between the two functions: the new getter reads the
file from the instruction word, and to ensure that is always set the
setter writes both the file and the type.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 9fb8323328 i965: Rename brw_inst's functions that access the register type
Put hw_ in the name so that it's clear these are the hardware encodings.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 3e379af492 i965: Index brw_hw_reg_type_to_size()'s table by logical type
I'll be transitioning everything to use the logical types.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner c1ac1a3d25 i965: Add a brw_hw_type_to_reg_type() function
Will be used in later commits.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner dbe7dd13dd i965: Use a common table to translate logical to hardware types
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner bfcc9aa829 i965: Extract functions dealing with register types to separate file
I'm going to encapsulate all of the logic dealing with register types in
this file.

Rename the parameters for the hardware encodings from type -> hw_type at
the same time.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 890f863da0 i965: Reverse file/type arguments to register type functions
I think of the initial arguments as "state" and the last as the actual
subject.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 92f787ff86 i965: Add support for disassembling 64-bit integer immediates
After the last patch converted things into enums, I helpfully got a
compiler warning about these missing from the switch statement.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner deae25ce37 i965: Use separate enums for register vs immediate types
The hardware encodings often mean different things depending on whether
the source is an immediate.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 8815b9677f i965: Reorder brw_reg_type enum values
These vaguely corresponded to the hardware encodings, but that is purely
historical at this point. Reorder them so we stop making things "almost
work" when mixing enums.

The ordering has been closen so that no enum value is the same as a
compatible hardware encoding.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner ce6b8627d8 i965: Validate destination restrictions with vector immediates
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 1d79c828d8 i965: Don't let raw-move check be tricked by immediate vector types
UB and B type encodings are the same as UV and VF. Noticed when writing
the following patch.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 48aa6ecb87 i965: Only change type of 0.0f to VF if destination stride == 1
The destination stride must be equivalent to a dword if VF is used.

Also, since the only compaction table entires with "i:vf" have the
destination as "r:f" specifically check that the destination is of type
float.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 56a676eed2 i965: Remove CONT/BREAK from instruction compaction test
These cannot be compacted. A similar mistake was fixed in commit
90eaf01616

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 3d661e6062 i965: Test instruction compaction on all supported Gens
Note that there's no point in testing on G45, since its compaction is
the same as Gen5. Same logic applies to Gen7 variants and low-power
parts.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 9ff7d9b853 i965: Silence signed/unsigned comparison warning
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner eac89911e5 i965: Move compaction "prepass" into brw_eu_compact.c
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Matt Turner 17641f6388 i965: Mark src inst pointer const in compaction code
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-08-21 14:05:23 -07:00
Dave Airlie b3f87b87f6 vulkan: import 1.0.59 headers and xml.
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-22 07:00:50 +10:00
Rob Herring 4734bfc02a Android: Fix LLVM duplicated symbols linking for N and M
Both statically linking libLLVMCore and dynamically linking libLLVM causes
duplicated symbols in gallium_dri.so and it fails to dlopen. We don't
really need to link libLLVMCore, but just need generated headers to be
built first. Dynamically linking to libLLVM instead is enough to do
that. Thanks to Qiang Yu for finding the root cause.

With this change, we can align all versions and just have libLLVM as a
shared lib dependency.

This also requires changes in the M and N versions of LLVM to export the
include paths for libLLVM. AOSP master is okay.

Fixes: 26aee6f4d5 ("Android: rework LLVM build support")
Reported-by: Mauro Rossi <issor.oruam@gmail.com>
Cc: 17.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Qiang Yu <Qiang.Yu@amd.com>
Signed-off-by: Rob Herring <robh@kernel.org>
2017-08-21 10:46:21 -05:00
Leo Liu 03b89547b7 st/va: add MJPEG for config
To enable MJPEG HW decode

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 5608f44271 st/va: reallocate surface with YUYV stream
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 2ebc530ca3 st/va: detect MJPEG format from bitstream
To find if the format is supported YUYV by sampling factor which
is embedded from bitstream. So we could use this info for buffer
reallocation on the correct format.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 7319ff8787 radeon/uvd: add YUYV format support for target buffer
Make chroma plane optional for YUYV support

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu c4061bb5fa st/va: reallocate surface when interlaced
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu fceb52a230 radeon/video: MJPEG not support stacked video buffers
So we have to detect it for reallocation of de-interlaced buffers

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu e50ee6d4d5 st/va: make surface allocate functions more usefully
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 130d1f456b radeon/uvd: reconstruct MJPEG bitstream
The current tier 1 mjpeg firmware only supports at the bitstream
level, the later tier 2 support will be at the buffers level with
newer hardware.

Signed-off-by: Leo Liu <leo.liu@amd.com>
Acked-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu ef099e6799 st/va: add slice parameter handling for MJPEG
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 8e9175744e st/va: add huffman table handling for MJPEG
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 93577e6081 st/va: add iq matrix handling for MJPEG
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 535b3c2363 st/va: add picture parameter handling for MJPEG
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 41f17eb5f0 st/va: add handles for MJPEG Buffers
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 38b9686df0 st/va: create decoder for MJPEG format
Mjpeg doesn't need reference

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 0a59477372 st/va: add MJPEG picture to context
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 15f3335577 radeon/video: add MJPEG support
v2: add ASIC and Kernel version check

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 3fe713ce3d radeon/uvd: add MJPEG support
There is no need of dpb buffer for mjpeg codec

v2: check dpb_size instead of format

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu b26cfdaebd radeon/uvd: add MJPEG stream type
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 4ac38ac3de vl: add MJPEG picture description
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 11ccb56e9f vl: add MJPEG profile and format
v2: move util video change to here

Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Leo Liu 2b1eacabfa radeon/uvd: get the target buffer pitch correct for different format
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2017-08-21 10:09:09 -04:00
Samuel Pitoiset 2843c5d15c radeonsi: update non-resident bindless descriptors if needed
Only resident bindless descriptors are currently updated and
re-uploaded, this makes sure that the non-resident ones are
also updated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-21 15:23:56 +02:00
Louis-Francis Ratté-Boulianne 498814a3ca dri3: Move up fourcc utility function
It will be needed in next patches.

Signed-off-by: Louis-Francis Ratté-Boulianne <lfrb@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2017-08-21 12:55:54 +01:00
Daniel Stone 85ef0215dd egl: Add dma_buf_import_modifiers for glvnd
Make sure we advertise the new entrypoints to libglvnd's EGL dispatch.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reported-by: Emmanuel Gil Peyrot <emmanuel.peyrot@collabora.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101982
Fixes: 4c412293d0 ("egl: advertise EGL_EXT_image_dma_buf_import_modifiers")
2017-08-21 12:13:50 +01:00
Topi Pohjolainen 393ec1a507 intel/blorp: Adjust intra-tile x when faking rgb with red-only
v2 (Jason): Adjust directly in surf_fake_rgb_with_red()

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101910

CC: mesa-stable@lists.freedesktop.org
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2017-08-21 09:55:08 +03:00
Dave Airlie b040f51b61 ac/nir: fixup layer/viewport export for GFX9.
GFX9 moved where the viewport index export goes.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-08-21 04:26:37 +01:00
Jason Ekstrand c366943ebf i965/bufmgr: s/BO_ALLOC_FOR_RENDER/BO_ALLOC_BUSY/
"Alloc for render" is a terrible name for a flag because it means
basically nothing.  What the flag really does is allocate a busy BO
which someone theorized at one point in time would be more efficient if
you're planning to immediately render to it.  If the flag really means
"alloc a busy BO" we should just call it that.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-08-20 20:14:49 -07:00
Jason Ekstrand cadcd89278 i965/tex: Change the flags type on create_for_teximage
This matches the actual function declaration.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-08-20 20:14:49 -07:00
Christoph Haag 87556a650a mesa: only copy requested compressed teximage cubemap faces
This is analogous to commit 2259b11 which only fixed the regular case

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102308
Signed-off-by: Christoph Haag <haagch+mesadev@frickel.club>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: mesa-stable@lists.freedesktop.org
2017-08-20 17:01:48 -04:00
Jason Ekstrand f24cf82d6d i965/tex: Don't pass samples to miptree_create_for_teximage
In 76e2f390f9, when Topi switched num_samples from 0 to 1 for
single-sampled, he accidentally switched the last parameter in the call
to miptree_create_for_teximage from 0 to 1 thinking it was num_samples
when it was actually layout_flags.  Switching from 0 to 1 added the
MIPTREE_LAYOUT_ACCELERATED_UPLOAD flag which causes us to allocate a
busy BO instead of an idle one.  This caused the subsequent CPU upload
to consistently stall.  The end result was a 15% performance drop in the
SynMark v7 DrvRes microbenchmark.  This restores the old behavior and
fixes the performance regression.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
Fixes: 76e2f390f9
Bugzilla: https://bugs.freedesktop.org/102260
Cc: mesa-stable@lists.freedesktop.org
2017-08-19 15:39:12 -07:00
Kenneth Graunke 6f8a577ed2 anv: Use ISL for emitting null surface states.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-19 00:46:48 -07:00
Kenneth Graunke 5ae983c85b i965: Use ISL for emitting null surface states.
We handle the Sandybridge multisampled 2D surface hack here, rather
than in ISL, because it requires allocating a BO, and is kind of messy.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-19 00:46:46 -07:00
Kenneth Graunke 5db9757bd7 isl: Add a null surface fill function.
ISL already offers functions to fill out most kinds of SURFACE_STATE,
so why not handle null surfaces too?

Null surfaces are simple, so we can just take the dimensions, rather
than an entirte fill structure.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-19 00:46:36 -07:00
Kenneth Graunke 288621b1b7 i965: Remove tabs in intel_batchbuffer.c.
Our coding style is to use spaces.  Some of this was also messed up
during my bufmgr import series.

(Trivial, just whitespace changes.)
2017-08-18 23:51:56 -07:00
Jason Ekstrand 61d2f3f1c2 i965/miptree: Return NONE from texture_aux_usage when fully resolved
This little optimization improves the performance of SynMark v7
TexFilterTri by almost 10% on Sky Lake GT4 among other improvements.
We've been doing it for some time but somehow it got dropped during
the miptree refactoring.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Bugzilla: https://bugs.freedesktop.org/102258
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
2017-08-18 17:31:02 -07:00
Jason Ekstrand d5e217dbfd i965: Stop looking at NewDriverState when emitting 3DSTATE_URB
Looking at NewDriverState is not safe in general.  The state atom system
is set up to ensure that new bits that get added to NewDriverState get
accumulated into the set of bits used when emitting atoms but it doesn't
go the other way.  If we read NewDriverState, we may not get the full
picture because the per-pipeline state (3D or compute) does not get
added to NewDriverState before state emit is done.  It's especially
dangerous to do this from BLORP (either explicitly or implicitly when
BLORP calls gen7_upload_urb) because that does not happen during one of
the normal state upload paths.

This commit solves the problem by whacking all of the per-shader-stage
URB sizes to zero whenever we change the total URB size.  We still have
to flag BRW_NEW_URB_SIZE to ensure that the gen7_urb atom triggers but
the actual decision in gen7_upload_urb can now be based entirely on URB
sizes rather than on state atoms.  This also makes BLORP correct because
it just asks for a new URB config whenever the vsize is too small and so
any change to the total URB size will trigger blorp to re-emit as well
because 0 < vs_entry_size.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Bugzilla: https://bugs.freedesktop.org/102289
Cc: mesa-stable@lists.freedesktop.org
2017-08-18 17:30:55 -07:00
Kenneth Graunke bc56dfbf3f i965: Mark all EGLimages as non-coherent.
EGLimages are shared with external users, and we don't know what they're
going to do with them.  They might scan them out.  They might access
them in a way that doesn't work with our explicit clflushing.

It's safest to simply mark them non-coherent.

Chris Wilson caught this problem and wrote a similar (though less
aggressive) patch to solve it; the miptree code has since undergone
a lot of refactoring so I had to rewrite it.

Cc: "17.2" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
2017-08-18 16:28:13 -07:00
Eric Anholt a727e03360 broadcom/genxml: Add V3D 3.3 packet definitions.
This will be used by the new vc5 gallium driver, and a future Vulkan
driver.
2017-08-18 12:54:13 -07:00
Eric Anholt 7c576d6091 broadcom/genxml: Check the sub-id field when decoding instructions.
VC5 introduces packet variants where the same opcode has behavior that is
decided by a sub-id field in the early bits of the packet.  Keep iterating
over packets until we find the one with the matching sub-id.
2017-08-18 11:56:58 -07:00
Eric Anholt 14fe9fd3f7 broadcom/genxml: Emit code for default headers for structs as well.
In the vc5 NIR backend, I want to use the XML code-generation to set up
pack/unpack of structs for the texture uniforms, and setting up the
unpacked copy needs a default header.
2017-08-18 11:56:58 -07:00
Eric Anholt 9caba0f16f anv: Move a comment that got left behind in the u_vector refactor. 2017-08-18 11:56:58 -07:00