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radeonsi: make some si_descriptors fields 32-bit 

The number of bindless descriptors is dynamic and we definitely
have to support more than 256 slots.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Samuel Pitoiset 2017-06-28 18:46:31 +02:00
parent 781a13c475
commit a29ef75565
1 changed files with 5 additions and 5 deletions
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10
src/gallium/drivers/radeonsi/si_state.h
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@ -234,7 +234,7 @@ struct si_descriptors {
/* The size of one descriptor. */
ubyte element_dw_size;
/* The maximum number of descriptors. */
ubyte num_elements;
uint32_t num_elements;
/* Offset in CE RAM */
uint16_t ce_offset;
@ -243,16 +243,16 @@ struct si_descriptors {
* range, direct uploads to memory will be used instead. This basically
* governs switching between onchip (CE) and offchip (upload) modes.
*/
ubyte first_ce_slot;
ubyte num_ce_slots;
uint32_t first_ce_slot;
uint32_t num_ce_slots;
/* Slots that are used by currently-bound shaders.
* With CE: It determines which slots are dumped to L2.
* It doesn't skip uploads to CE RAM.
* Without CE: It determines which slots are uploaded.
*/
ubyte first_active_slot;
ubyte num_active_slots;
uint32_t first_active_slot;
uint32_t num_active_slots;
/* Whether CE is used to upload this descriptor array. */
bool uses_ce;