Commit Graph

155702 Commits

Author SHA1 Message Date
Erik Faye-Lund ee9c3d2625 docs: set language to english
It seems recent versions of Sphinx has started issuing a warning when
language isn't set to a recognized value. Since we're building with
warnings as errors on CI, this causes issues for people.

We're writing English docs, so we should set this to English. I probably
confused this setting with the highlight_language setting or something
when I set this up initially.

Fixes: 00cd1346bf ("docs: use sphinx")
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6711
Reviewed-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17159>
2022-06-21 13:54:28 +00:00
Danylo Piliaiev 48540caec9 tu: Disable sample counting for 3d blits during occlusion query
Per Vulkan spec only "Draw" commands should be counted towards
occlusion query.

Apparently RB_SAMPLE_COUNT_CONTROL::UNK0 bool controls whether
sample counting is enabled, so we could use it to disable
sample counting for 3d blits which are sometimes used for
clear/copy/blit/gmem-store/resolve operations.

Fixes GL CTS tests running through Zink:
 dEQP-GLES3.functional.occlusion_query.depth_clear
 dEQP-GLES3.functional.occlusion_query.depth_clear_stencil_clear
 dEQP-GLES3.functional.occlusion_query.scissor_depth_clear_stencil_clear
 dEQP-GLES3.functional.occlusion_query.scissor_stencil_clear
 dEQP-GLES3.functional.occlusion_query.stencil_clear

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6559

Signed-off-by: Danylo Piliaiev <dpiliaiev@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17138>
2022-06-21 13:13:36 +00:00
Gert Wollny 0c3fae4e6e virgl: Don't let ntt optimize the register allocation
Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15995>
2022-06-21 11:24:09 +00:00
Martin Roukala (né Peres) 677a42378b ci/radv: add a missing flake
Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17131>
2022-06-21 13:11:05 +03:00
Martin Roukala (né Peres) f86e12743c ci/radv: move a test from the fail list to the flake list
The test was misidentified as a "fail", when it actually has a very
high failure rate (>95%). The test happened to pass twice within the
last week, so let's mark this test as a flake.

Signed-off-by: Martin Roukala (né Peres) <martin.roukala@mupuf.org>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17131>
2022-06-21 13:10:51 +03:00
Boris Brezillon d232f5a026 dzn: Fix the 2DMSArray case in dzn_image_get_dsv_desc()
Texture2DMSArray element is not initialized, making 2DMSArray DS
views buggy.

Reported-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17158>
2022-06-21 08:39:40 +00:00
Samuel Pitoiset 6cab999d6a radv,aco: rename radv_prolog_binary/radv_shader_prolog to shader_part
The same structures and functions will be re-used for PS epilogs.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17084>
2022-06-21 08:04:50 +00:00
Christian Gmeiner 5cce02325c ir3: Create at least one thread for async shader compile
On a single core CPU system we end with num_threads being 0 and we do
_NOT_ create any async compile threads in util_queue_init(..).

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17124>
2022-06-21 07:18:56 +00:00
Christian Gmeiner 3196bde941 freedreno: Wait for async compile jobs to finish
initial_variants_synchronous(..) allows initial shader variant
compilation asynchronously if debug.debug_message == NULL. If the
debug callback gets changed it seems like a good idea to wait until
all async shader compiles are done.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17124>
2022-06-21 07:18:56 +00:00
Vinson Lee 081b1eeacd microsoft/compiler: Fix assert.
Fix defect reported by Coverity Scan.

Side effect in assertion (ASSERT_SIDE_EFFECT)
assignment_where_comparison_intended: Assignment var->type =
glsl_int_type() has a side effect. This code will work differently in a
non-debug build.

Fixes: afb64e10c1 ("microsoft/compiler: Move d3d12_fix_io_uint_type() to dxil_nir.c")
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17097>
2022-06-21 06:54:18 +00:00
Vinson Lee 2b87073133 radv: Remove unnecessary null check.
Fix defect reported by Coverity Scan.

Dereference before null check (REVERSE_INULL)
check_after_deref: Null-checking subpass suggests that it may be null,
but it has already been dereferenced on all paths leading to the check.

Fixes: 779e09639b ("radv: configure DB_Z_INFO.NUM_SAMPLES correctly on GFX11")
Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17100>
2022-06-21 04:00:46 +00:00
David Heidelberg 9cf3608952 ci: Uprev apitrace to 790380e05854
Better context error reporting, fix crash for replaying PlagueIncEvolved

Reviewed-by: Guilherme Gallo <guilherme.gallo@collabora.com>
Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17136>
2022-06-20 21:51:28 +02:00
Filip Gawin 6cbb19110b r300: prefer old not native swizzle in constant folding
r300 and r400 have strict rules with swizzles, so we
will need to convert swizzle back.

Operating on 0, 1, H in this case unnecessarily makes
rest of r300 overly complicated.
(also it's not currently able to handle this)

helps with:
deqp-gles2@functional@shaders@random@exponential@fragment@24

cc: mesa-stable

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17117>
2022-06-20 19:10:00 +00:00
Alyssa Rosenzweig b6a30b72ab panfrost: Implement provoking vertices on Valhall
Starting with Valhall, the provoking vertex state is specified per-framebuffer
(batch) instead of per-draw. We use the pan_tristate infrastructure to translate
between desktop OpenGL's per-draw semantics to Valhall's per-framebuffer
semantic. This is notably not required for GLES or Vulkan.

If the provoking vertex is unset when the tiler context is generated, it could
be set (incompatibly) later in the batch, and the tiler context's provoking
vertex field would no longer match the framebuffer's. That would violate a
hardware invariant. To ensure that doesn't happen, we make sure to set provoking
vertexes *before* generating the tiler context so it can't change after.

Fixes arb-provoking-vertex-render on Valhall.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17068>
2022-06-20 18:38:16 +00:00
Alyssa Rosenzweig 9cdd32257f panfrost: Add tristate_is_defined helper
This is useful to ensure that the tri-state has been set. It could be inlined,
but the tri-state structure is designed to be opaque so this matches better.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17068>
2022-06-20 18:38:16 +00:00
Alyssa Rosenzweig 950d27f9bf panfrost: Fix batch state changes on Valhall
If we need to change batch state (currently just point coord origins), not only
do we need to flush the old batch, but also set the desired state on the new
batch. That second step was missing. Fix that so this mechanism works as
intended.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Fixes: 3641dfe436 ("panfrost: Flip point coords in hardware")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17068>
2022-06-20 18:38:16 +00:00
Alyssa Rosenzweig e9190c45d5 panfrost: Disable QUADS on Valhall
Even with the fixes in the rest of the series, arb-provoking-vertex-render is
still failing on Valhall for a single subcase (involving QUADS). It seems likely
that QUADS support is broken on Valhall, given it's not used in any of the APIs
for which Arm ships drivers.

Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17068>
2022-06-20 18:38:16 +00:00
Marcin Ślusarz 008163f382 intel/compiler: vectorize task payload loads/stores
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17000>
2022-06-20 17:38:20 +00:00
Marcin Ślusarz 97b53ad759 nir/opt_load_store_vectorize: handle task payloads
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17000>
2022-06-20 17:38:20 +00:00
Karmjit Mahil fad7e858f2 pvr: Extend hard coding infra to allow per stage per device coding.
This commit extends the graphics hard coding infrastructure to
allow the independent hard coding of stages, i.e. hard code fragment
stage and vertex stage separately instead of having to hard code
everything.

It also extends the infrastructure to allow per device hard coding.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17106>
2022-06-20 16:59:01 +00:00
Karmjit Mahil c6933cc9de pvr: Enable 33.15.11.3 (AXE-1-16M).
This commit adds 33.15.11.3 in the supported BVNCs and addresses
differences in the descriptor limits between devices so that the
physical device limit is accurate.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17106>
2022-06-20 16:59:01 +00:00
Frank Binns 62cc9bba06 pvr: Add TI AM62 as a supported device.
The AM62 platform contains an IMG AXE-1-16M GPU.

Co-Authored-By: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Signed-off-by: Frank Binns <frank.binns@imgtec.com>
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17106>
2022-06-20 16:59:01 +00:00
David Heidelberg 57ad38c2fc ci/freedreno: disable non-existing trace
Never existed in the repository.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17137>
2022-06-20 16:36:10 +00:00
Juan A. Suarez Romero c0626a6bd2 v3dv/ci: Update expected results
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17141>
2022-06-20 15:37:39 +00:00
Boris Brezillon 1987fb0091 ci/dzn: Move to a .toml description
This way we don't force a CI run on all platforms anytime we add a
group of test, and, as a bonus, we make dozen CI consistent with other
platforms.

Suggested-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Suggested-by: Emma Anholt <emma@anholt.net>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Erik Faye-Lund <erik.faye-lund@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17074>
2022-06-20 14:48:51 +00:00
David Heidelberg 2bbb11eca2 ci/freedreno: smuggle myself into restricted traces access list
Already have access into traces-db-restricted repository, so this just
allow me to trigger the job without patching.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17016>
2022-06-20 12:42:41 +00:00
David Heidelberg dfe9b856cb ci/freedreno: update restricted traces to the brotli compressed version
Save some space on proxies and speedup network transfer to the runners.

Signed-off-by: David Heidelberg <david.heidelberg@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17016>
2022-06-20 12:42:41 +00:00
Matti Hamalainen 11ac33c2a9 gallium/tools: fixes to option handling
Not all options in the options object are set by all tools.
Instead of using argparse result objects directly, use separate
with default settings and copy relevant attributes there.

Signed-off-by: Matti Hamalainen <ccr@tnsp.org>
Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17108>
2022-06-20 12:35:53 +00:00
Mykhailo Skorokhodov 50b21fb6e4 anv: Use sampleLocationsEnable for sample locations
The spec says: "sampleLocationsEnable controls whether custom sample
locations are used. If sampleLocationsEnable is VK_FALSE, the default
sample locations are used and the values specified in
sampleLocationsInfo are ignored."

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/6675
Signed-off-by: Mykhailo Skorokhodov <mykhailo.skorokhodov@globallogic.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17134>
2022-06-20 11:58:09 +00:00
Erik Faye-Lund 419b8c7f8d dzn: correct order of src_subres and dst_subres args
Fixes: 2d0798440b ("dzn: Add support for dynamic rendering")
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17133>
2022-06-20 11:16:15 +00:00
Georg Lehmann 7afecd8ad8 radv: Check descriptor pool entry count before allocating a new set.
It's simpler and more efficient.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17127>
2022-06-20 10:50:01 +00:00
Georg Lehmann ceb3ae2afb radv: Remove redundant memset in radv_descriptor_set_create.
The memset below also clears this memory, plus the descriptor set header.

Signed-off-by: Georg Lehmann <dadschoorse@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Konstantin Seurer <konstantin.seurer@gmail.com>
Reviewed-by: Mike Blumenkrantz <michael.blumenkrantz@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17127>
2022-06-20 10:50:01 +00:00
Karmjit Mahil 7c25c6f04e pvr: Add graphics pipeline hard coding infrastructure.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16999>
2022-06-20 08:13:11 +00:00
Karmjit Mahil e47350a245 pvr: Remove unused output_selects from vertex shader state.
Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16999>
2022-06-20 08:13:11 +00:00
Karmjit Mahil 66f4c9abc9 pvr: Change compute hard coding infrastructure.
This commit changes the way in which the hard coding is done in
the compute pipeline to allow easier hard coding for demos other
than the simple-compute demo.

Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com>
Acked-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Frank Binns <frank.binns@imgtec.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16999>
2022-06-20 08:13:11 +00:00
Marcin Ślusarz 4e4ef72aac intel/dev: fixup max_cs_workgroup_threads after hwconfig is read
Without it we get max value from gfx12 on gfx>12.

Fixes: d9ff9ea9c3 ("intel/dev: Read hwconfig from i915")

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17063>
2022-06-20 07:43:43 +00:00
Samuel Pitoiset 5485bf7b1b aco: fix validation of SOP1 instructions without definitions
Like s_setpc_b64.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17082>
2022-06-20 07:08:28 +00:00
Samuel Pitoiset 6dd2699e9f radv/amdgpu: do not add "global" BO to the virtual BO list
To avoid dangling BO references if it's destroyed without being
previously unbound. This is under Vulkan spec clarification but it
looks like the "global" BO fix is simple enough to workaround the
issue for now.

This fixes a CPU hang with Halo Infinite because the kernel rejects
a submission (invalid BO handle found).

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17085>
2022-06-20 06:43:53 +00:00
Samuel Pitoiset b4cc10b342 radv/amdgpu: make sure to reset the number of BO when there is no ranges
If an application binds a sparse resource and then unbind it with NULL,
the number of "real" BOs in the virtual BO list should be reset to 0.
Otherwise, it might use a dangling BO reference if it's destroyed just
after being unbound.

Cc: mesa-stable
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17085>
2022-06-20 06:43:53 +00:00
Samuel Pitoiset 29f34cc806 ci: uprev vkd3d-proton to 39d07dea2cef34bfb3ed39741f026bc637e3eec4
The 2.6 version is old (released 4 months ago), the latest contains
even more useful tests (+2900 tests). Use the master branch by default,
so it could be regularly updated.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Martin Roukala <martin.roukala@mupuf.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17105>
2022-06-20 07:52:02 +02:00
Mike Blumenkrantz 6072d5d8dc zink: ci updates
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
2022-06-20 00:50:48 +00:00
Mike Blumenkrantz 420270cb4f zink: relax zink_resource_buffer_needs_barrier checks
this now matches zink_resource_image_needs_barrier

cc: mesa-stable

Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
2022-06-20 00:50:48 +00:00
Mike Blumenkrantz f889bece46 zink: don't short-circuit gfx stage finding during barrier generation
according to spec, all stages must be specified, not just the first one

Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
2022-06-20 00:50:48 +00:00
Mike Blumenkrantz 1fa3f03442 zink: collect gfx stages for all bindings during barrier generation
it's important to get the full mask in order to accurately provide
dependency info

Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
2022-06-20 00:50:48 +00:00
Mike Blumenkrantz 9e3ed65324 zink: add a #define for vk shader bits
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
2022-06-20 00:50:48 +00:00
Mike Blumenkrantz 80569f9e5f zink: track image binds
track all the things

Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
2022-06-20 00:50:48 +00:00
Mike Blumenkrantz 47361daffc zink: rework buffer barrier generation
by passing through the draw buffers, more accurate barriers can be generated
to ensure synchronization for both the draw buffer scopes and
descriptor binding scopes

ref #6597

Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
2022-06-20 00:50:48 +00:00
Mike Blumenkrantz db0fda6f36 zink: track vertex buffer bind counts on resources
Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
2022-06-20 00:50:48 +00:00
Mike Blumenkrantz 7b88dbfd78 zink: move draw-time barrier generation down a little
ensure that this occurs after potential rebind handling

Acked-by: Dave Airlie <airlied@redhat.com>
Reviewed-By: Tatsuyuki Ishi <ishitatsuyuki@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17111>
2022-06-20 00:50:48 +00:00
Mike Blumenkrantz 9ca0c0b4b4 mesa/st: increment num_uniforms for hw accel select shaders
this otherwise breaks nir_lower_uniforms_to_ubo() and probably lots
of drivers

Fixes: 9b22ab4167 ("mesa/st: implement hardware accelerated GL_SELECT")

Reviewed-by: Qiang Yu <yuq825@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17092>
2022-06-18 20:18:18 +00:00