pvr: Extend hard coding infra to allow per stage per device coding.
This commit extends the graphics hard coding infrastructure to allow the independent hard coding of stages, i.e. hard code fragment stage and vertex stage separately instead of having to hard code everything. It also extends the infrastructure to allow per device hard coding. Signed-off-by: Karmjit Mahil <Karmjit.Mahil@imgtec.com> Reviewed-by: Rajnesh Kanwal <rajnesh.kanwal@imgtec.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17106>
This commit is contained in:
Karmjit Mahil
Marge Bot
parent
c6933cc9de
commit
fad7e858f2
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@ -27,7 +27,9 @@
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#include <string.h>
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#include <vulkan/vulkan_core.h>
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#include "compiler/shader_enums.h"
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#include "hwdef/rogue_hw_utils.h"
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#include "pvr_device_info.h"
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#include "pvr_hardcode.h"
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#include "pvr_private.h"
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#include "rogue/rogue.h"
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@ -42,19 +44,30 @@
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* This should eventually be deleted as the compiler becomes more capable.
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*/
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#define PVR_AXE_1_16M_BVNC PVR_BVNC_PACK(33, 15, 11, 3)
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#define PVR_GX6250_BVNC PVR_BVNC_PACK(4, 40, 2, 51)
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enum pvr_hard_code_shader_type {
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PVR_HARD_CODE_SHADER_TYPE_COMPUTE,
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PVR_HARD_CODE_SHADER_TYPE_GRAPHICS,
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};
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/* Applications for which the compiler is capable of generating valid shaders.
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/* Table indicating which demo and for which device the compiler is capable of
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* generating valid shaders.
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*/
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static const char *const compilable_progs[] = {
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"triangle",
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static struct {
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const char *const name;
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uint64_t bvncs[3];
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} compatiblity_table[] = {
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{
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.name = "triangle",
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.bvncs = { PVR_GX6250_BVNC, },
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},
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};
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static const struct pvr_hard_coding_data {
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const char *const name;
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uint64_t bvnc;
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enum pvr_hard_code_shader_type type;
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union {
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@ -69,6 +82,9 @@ static const struct pvr_hard_coding_data {
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} compute;
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struct {
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/* Mask of MESA_SHADER_* (gl_shader_stage). */
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uint32_t flags;
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struct rogue_shader_binary *const *const vert_shaders;
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struct rogue_shader_binary *const *const frag_shaders;
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@ -85,6 +101,7 @@ static const struct pvr_hard_coding_data {
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} hard_coding_table[] = {
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{
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.name = "simple-compute",
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.bvnc = PVR_GX6250_BVNC,
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.type = PVR_HARD_CODE_SHADER_TYPE_COMPUTE,
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.compute = {
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@ -118,23 +135,42 @@ static const struct pvr_hard_coding_data {
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},
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};
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bool pvr_hard_code_shader_required(void)
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static inline uint64_t
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pvr_device_get_bvnc(const struct pvr_device_info *const dev_info)
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{
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const struct pvr_device_ident *const ident = &dev_info->ident;
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return PVR_BVNC_PACK(ident->b, ident->v, ident->n, ident->c);
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}
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bool pvr_hard_code_shader_required(const struct pvr_device_info *const dev_info)
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{
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const char *const program = util_get_process_name();
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const uint64_t bvnc = pvr_device_get_bvnc(dev_info);
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for (uint32_t i = 0; i < ARRAY_SIZE(compilable_progs); i++) {
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if (strcmp(program, compilable_progs[i]) == 0)
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return false;
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for (uint32_t i = 0; i < ARRAY_SIZE(compatiblity_table); i++) {
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for (uint32_t j = 0; j < ARRAY_SIZE(compatiblity_table[0].bvncs); j++) {
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if (bvnc != compatiblity_table[i].bvncs[j])
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continue;
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if (strcmp(program, compatiblity_table[i].name) == 0)
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return false;
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}
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}
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return true;
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}
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static const struct pvr_hard_coding_data *pvr_get_hard_coding_data()
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static const struct pvr_hard_coding_data *
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pvr_get_hard_coding_data(const struct pvr_device_info *const dev_info)
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{
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const char *const program = util_get_process_name();
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const uint64_t bvnc = pvr_device_get_bvnc(dev_info);
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for (uint32_t i = 0; i < ARRAY_SIZE(hard_coding_table); i++) {
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if (bvnc != hard_coding_table[i].bvnc)
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continue;
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if (strcmp(program, hard_coding_table[i].name) == 0)
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return &hard_coding_table[i];
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}
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@ -151,7 +187,8 @@ VkResult pvr_hard_code_compute_pipeline(
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{
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const uint32_t cache_line_size =
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rogue_get_slc_cache_line_size(&device->pdevice->dev_info);
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const struct pvr_hard_coding_data *const data = pvr_get_hard_coding_data();
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const struct pvr_hard_coding_data *const data =
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pvr_get_hard_coding_data(&device->pdevice->dev_info);
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assert(data->type == PVR_HARD_CODE_SHADER_TYPE_COMPUTE);
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@ -167,79 +204,128 @@ VkResult pvr_hard_code_compute_pipeline(
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&shader_state_out->bo);
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}
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void pvr_hard_code_graphics_shaders(
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uint32_t pipeline_n,
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struct rogue_shader_binary **const vert_shader_out,
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struct rogue_shader_binary **const frag_shader_out)
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uint32_t
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pvr_hard_code_graphics_get_flags(const struct pvr_device_info *const dev_info)
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{
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const struct pvr_hard_coding_data *const data = pvr_get_hard_coding_data();
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const struct pvr_hard_coding_data *const data =
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pvr_get_hard_coding_data(dev_info);
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assert(data->type == PVR_HARD_CODE_SHADER_TYPE_GRAPHICS);
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return data->graphics.flags;
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}
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void pvr_hard_code_graphics_shader(const struct pvr_device_info *const dev_info,
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uint32_t pipeline_n,
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gl_shader_stage stage,
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struct rogue_shader_binary **const shader_out)
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{
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const struct pvr_hard_coding_data *const data =
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pvr_get_hard_coding_data(dev_info);
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assert(data->type == PVR_HARD_CODE_SHADER_TYPE_GRAPHICS);
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assert(pipeline_n < data->graphics.shader_count);
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assert(data->graphics.flags & BITFIELD_BIT(stage));
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mesa_logd("Hard coding graphics pipeline for %s", data->name);
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mesa_logd("Hard coding %s stage shader for \"%s\" demo.",
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_mesa_shader_stage_to_string(stage),
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data->name);
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*vert_shader_out = data->graphics.vert_shaders[pipeline_n];
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*frag_shader_out = data->graphics.frag_shaders[pipeline_n];
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switch (stage) {
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case MESA_SHADER_VERTEX:
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*shader_out = data->graphics.vert_shaders[pipeline_n];
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break;
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case MESA_SHADER_FRAGMENT:
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*shader_out = data->graphics.frag_shaders[pipeline_n];
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break;
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default:
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unreachable("Unsupported stage.");
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}
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}
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void pvr_hard_code_graphics_vertex_state(
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const struct pvr_device_info *const dev_info,
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uint32_t pipeline_n,
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struct pvr_vertex_shader_state *const vert_state_out)
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{
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const struct pvr_hard_coding_data *const data = pvr_get_hard_coding_data();
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const struct pvr_hard_coding_data *const data =
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pvr_get_hard_coding_data(dev_info);
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assert(data->type == PVR_HARD_CODE_SHADER_TYPE_GRAPHICS);
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assert(pipeline_n < data->graphics.shader_count);
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assert(data->graphics.flags & BITFIELD_BIT(MESA_SHADER_VERTEX));
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*vert_state_out = *data->graphics.vert_shader_states[0];
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}
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void pvr_hard_code_graphics_fragment_state(
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const struct pvr_device_info *const dev_info,
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uint32_t pipeline_n,
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struct pvr_fragment_shader_state *const frag_state_out)
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{
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const struct pvr_hard_coding_data *const data = pvr_get_hard_coding_data();
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const struct pvr_hard_coding_data *const data =
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pvr_get_hard_coding_data(dev_info);
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assert(data->type == PVR_HARD_CODE_SHADER_TYPE_GRAPHICS);
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assert(pipeline_n < data->graphics.shader_count);
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assert(data->graphics.flags & BITFIELD_BIT(MESA_SHADER_FRAGMENT));
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*frag_state_out = *data->graphics.frag_shader_states[0];
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}
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void pvr_hard_code_graphics_inject_build_info(
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void pvr_hard_code_graphics_get_build_info(
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const struct pvr_device_info *const dev_info,
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uint32_t pipeline_n,
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struct rogue_build_ctx *ctx,
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struct pvr_explicit_constant_usage *const vert_common_data_out,
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struct pvr_explicit_constant_usage *const frag_common_data_out)
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gl_shader_stage stage,
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struct rogue_common_build_data *const common_build_data,
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struct rogue_build_data *const build_data,
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struct pvr_explicit_constant_usage *const explicit_const_usage)
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{
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const struct pvr_hard_coding_data *const data = pvr_get_hard_coding_data();
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const struct pvr_hard_coding_data *const data =
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pvr_get_hard_coding_data(dev_info);
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assert(data->type == PVR_HARD_CODE_SHADER_TYPE_GRAPHICS);
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assert(pipeline_n < data->graphics.shader_count);
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assert(data->graphics.flags & BITFIELD_BIT(stage));
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ctx->stage_data = data->graphics.build_infos[pipeline_n]->stage_data;
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ctx->common_data[MESA_SHADER_VERTEX] =
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data->graphics.build_infos[pipeline_n]->vert_common_data;
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ctx->common_data[MESA_SHADER_FRAGMENT] =
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data->graphics.build_infos[pipeline_n]->frag_common_data;
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switch (stage) {
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case MESA_SHADER_VERTEX:
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assert(
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data->graphics.build_infos[pipeline_n]->vert_common_data.temps ==
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data->graphics.vert_shader_states[pipeline_n]->stage_state.temps_count);
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assert(
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ctx->common_data[MESA_SHADER_VERTEX].temps ==
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data->graphics.vert_shader_states[pipeline_n]->stage_state.temps_count);
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assert(
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ctx->common_data[MESA_SHADER_FRAGMENT].temps ==
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data->graphics.frag_shader_states[pipeline_n]->stage_state.temps_count);
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assert(data->graphics.build_infos[pipeline_n]->vert_common_data.coeffs ==
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data->graphics.vert_shader_states[pipeline_n]
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->stage_state.coefficient_size);
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assert(ctx->common_data[MESA_SHADER_VERTEX].coeffs ==
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data->graphics.vert_shader_states[pipeline_n]
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->stage_state.coefficient_size);
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assert(ctx->common_data[MESA_SHADER_FRAGMENT].coeffs ==
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data->graphics.frag_shader_states[pipeline_n]
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->stage_state.coefficient_size);
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build_data->vs = data->graphics.build_infos[pipeline_n]->stage_data.vs;
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*common_build_data =
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data->graphics.build_infos[pipeline_n]->vert_common_data;
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*explicit_const_usage =
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data->graphics.build_infos[pipeline_n]->vert_explicit_conts_usage;
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*vert_common_data_out =
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data->graphics.build_infos[pipeline_n]->vert_explicit_conts_usage;
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*frag_common_data_out =
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data->graphics.build_infos[pipeline_n]->frag_explicit_conts_usage;
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break;
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case MESA_SHADER_FRAGMENT:
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assert(
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data->graphics.build_infos[pipeline_n]->frag_common_data.temps ==
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data->graphics.frag_shader_states[pipeline_n]->stage_state.temps_count);
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assert(data->graphics.build_infos[pipeline_n]->frag_common_data.coeffs ==
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data->graphics.frag_shader_states[pipeline_n]
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->stage_state.coefficient_size);
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build_data->fs = data->graphics.build_infos[pipeline_n]->stage_data.fs;
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*common_build_data =
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data->graphics.build_infos[pipeline_n]->frag_common_data;
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*explicit_const_usage =
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data->graphics.build_infos[pipeline_n]->frag_explicit_conts_usage;
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break;
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default:
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unreachable("Unsupported stage.");
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}
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}
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@ -28,6 +28,7 @@
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#include <stdint.h>
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#include <vulkan/vulkan_core.h>
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#include "compiler/shader_enums.h"
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#include "rogue/rogue_build_data.h"
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/**
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@ -40,6 +41,7 @@
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struct pvr_compute_pipeline_shader_state;
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struct pvr_device;
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struct pvr_fragment_shader_state;
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struct pvr_hard_coding_data;
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struct pvr_vertex_shader_state;
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struct pvr_explicit_constant_usage {
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@ -73,36 +75,47 @@ struct pvr_hard_code_graphics_build_info {
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/* Returns true if the shader for the currently running program requires hard
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* coded shaders.
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*/
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bool pvr_hard_code_shader_required(void);
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bool pvr_hard_code_shader_required(const struct pvr_device_info *const dev_info);
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VkResult pvr_hard_code_compute_pipeline(
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struct pvr_device *const device,
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struct pvr_compute_pipeline_shader_state *const shader_state_out,
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struct pvr_hard_code_compute_build_info *const build_info_out);
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/* Returns a mask of MESA_SHADER_* (gl_shader_stage) indicating which stage
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* needs to be hard coded.
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*/
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uint32_t
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pvr_hard_code_graphics_get_flags(const struct pvr_device_info *const dev_info);
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/* pipeline_n:
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* The pipeline number. Each pipeline created requires unique hard
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* coding so a pipeline number is necessary to identify which data to use.
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* This pipeline number to request data for the first pipeline to be created
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* is 0 and should be incremented for each subsequent pipeline.
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*/
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void pvr_hard_code_graphics_shaders(
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void pvr_hard_code_graphics_shader(
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const struct pvr_device_info *const dev_info,
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uint32_t pipeline_n,
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struct rogue_shader_binary **const vert_shader_out,
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struct rogue_shader_binary **const frag_shader_out);
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gl_shader_stage stage,
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struct rogue_shader_binary **const shader_out);
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void pvr_hard_code_graphics_vertex_state(
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const struct pvr_device_info *const dev_info,
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uint32_t pipeline_n,
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struct pvr_vertex_shader_state *vert_state);
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struct pvr_vertex_shader_state *const vert_state_out);
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void pvr_hard_code_graphics_fragment_state(
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uint32_t pipelien_n,
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struct pvr_fragment_shader_state *frag_state);
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void pvr_hard_code_graphics_inject_build_info(
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const struct pvr_device_info *const dev_info,
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uint32_t pipeline_n,
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struct rogue_build_ctx *ctx,
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struct pvr_explicit_constant_usage *const vert_common_data_out,
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struct pvr_explicit_constant_usage *const frag_common_data_out);
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struct pvr_fragment_shader_state *const frag_state_out);
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void pvr_hard_code_graphics_get_build_info(
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const struct pvr_device_info *const dev_info,
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uint32_t pipeline_n,
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gl_shader_stage stage,
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struct rogue_common_build_data *const common_build_data,
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struct rogue_build_data *const build_data,
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struct pvr_explicit_constant_usage *const explicit_const_usage);
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#endif /* PVR_HARDCODE_SHADERS_H */
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@ -1020,7 +1020,7 @@ static VkResult pvr_compute_pipeline_compile(
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uint32_t usc_temps;
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VkResult result;
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if (pvr_hard_code_shader_required()) {
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if (pvr_hard_code_shader_required(&device->pdevice->dev_info)) {
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struct pvr_hard_code_compute_build_info build_info;
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result = pvr_hard_code_compute_pipeline(device,
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@ -1399,7 +1399,6 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
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struct pvr_explicit_constant_usage frag_explicit_const_usage = {
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.start_offset = 0,
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};
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const bool requires_hard_coding = pvr_hard_code_shader_required();
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static uint32_t hard_code_pipeline_n = 0;
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const VkPipelineVertexInputStateCreateInfo *const vertex_input_state =
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@ -1415,61 +1414,98 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
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if (!ctx)
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return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
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if (requires_hard_coding) {
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pvr_hard_code_graphics_shaders(hard_code_pipeline_n,
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&ctx->binary[MESA_SHADER_VERTEX],
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&ctx->binary[MESA_SHADER_FRAGMENT]);
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} else {
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/* NIR middle-end translation. */
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for (gl_shader_stage stage = MESA_SHADER_FRAGMENT;
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stage > MESA_SHADER_NONE;
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stage--) {
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const VkPipelineShaderStageCreateInfo *create_info;
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size_t stage_index = gfx_pipeline->stage_indices[stage];
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/* NIR middle-end translation. */
|
||||
for (gl_shader_stage stage = MESA_SHADER_FRAGMENT; stage > MESA_SHADER_NONE;
|
||||
stage--) {
|
||||
const VkPipelineShaderStageCreateInfo *create_info;
|
||||
size_t stage_index = gfx_pipeline->stage_indices[stage];
|
||||
|
||||
/* Skip unused/inactive stages. */
|
||||
if (stage_index == ~0)
|
||||
if (pvr_hard_code_shader_required(&device->pdevice->dev_info)) {
|
||||
if (pvr_hard_code_graphics_get_flags(&device->pdevice->dev_info) &
|
||||
BITFIELD_BIT(stage)) {
|
||||
continue;
|
||||
|
||||
create_info = &pCreateInfo->pStages[stage_index];
|
||||
|
||||
/* SPIR-V to NIR. */
|
||||
ctx->nir[stage] = pvr_spirv_to_nir(ctx, stage, create_info);
|
||||
if (!ctx->nir[stage]) {
|
||||
ralloc_free(ctx);
|
||||
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
|
||||
}
|
||||
}
|
||||
|
||||
/* Pre-back-end analysis and optimization, driver data extraction. */
|
||||
/* TODO: Analyze and cull unused I/O between stages. */
|
||||
/* TODO: Allocate UBOs between stages;
|
||||
* pipeline->layout->set_{count,layout}.
|
||||
*/
|
||||
/* Skip unused/inactive stages. */
|
||||
if (stage_index == ~0)
|
||||
continue;
|
||||
|
||||
/* Back-end translation. */
|
||||
for (gl_shader_stage stage = MESA_SHADER_FRAGMENT;
|
||||
stage > MESA_SHADER_NONE;
|
||||
stage--) {
|
||||
if (!ctx->nir[stage])
|
||||
continue;
|
||||
create_info = &pCreateInfo->pStages[stage_index];
|
||||
|
||||
ctx->rogue[stage] = pvr_nir_to_rogue(ctx, ctx->nir[stage]);
|
||||
if (!ctx->rogue[stage]) {
|
||||
ralloc_free(ctx);
|
||||
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
|
||||
}
|
||||
|
||||
ctx->binary[stage] = pvr_rogue_to_binary(ctx, ctx->rogue[stage]);
|
||||
if (!ctx->binary[stage]) {
|
||||
ralloc_free(ctx);
|
||||
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
|
||||
}
|
||||
/* SPIR-V to NIR. */
|
||||
ctx->nir[stage] = pvr_spirv_to_nir(ctx, stage, create_info);
|
||||
if (!ctx->nir[stage]) {
|
||||
ralloc_free(ctx);
|
||||
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
|
||||
}
|
||||
}
|
||||
|
||||
if (requires_hard_coding) {
|
||||
pvr_hard_code_graphics_vertex_state(hard_code_pipeline_n,
|
||||
/* Pre-back-end analysis and optimization, driver data extraction. */
|
||||
/* TODO: Analyze and cull unused I/O between stages. */
|
||||
/* TODO: Allocate UBOs between stages;
|
||||
* pipeline->layout->set_{count,layout}.
|
||||
*/
|
||||
|
||||
/* Back-end translation. */
|
||||
for (gl_shader_stage stage = MESA_SHADER_FRAGMENT; stage > MESA_SHADER_NONE;
|
||||
stage--) {
|
||||
if (pvr_hard_code_shader_required(&device->pdevice->dev_info) &&
|
||||
pvr_hard_code_graphics_get_flags(&device->pdevice->dev_info) &
|
||||
BITFIELD_BIT(stage)) {
|
||||
const struct pvr_device_info *const dev_info =
|
||||
&device->pdevice->dev_info;
|
||||
struct pvr_explicit_constant_usage *explicit_const_usage;
|
||||
|
||||
switch (stage) {
|
||||
case MESA_SHADER_VERTEX:
|
||||
explicit_const_usage = &vert_explicit_const_usage;
|
||||
break;
|
||||
|
||||
case MESA_SHADER_FRAGMENT:
|
||||
explicit_const_usage = &frag_explicit_const_usage;
|
||||
break;
|
||||
|
||||
default:
|
||||
unreachable("Unsupported stage.");
|
||||
}
|
||||
|
||||
pvr_hard_code_graphics_shader(dev_info,
|
||||
hard_code_pipeline_n,
|
||||
stage,
|
||||
&ctx->binary[stage]);
|
||||
|
||||
pvr_hard_code_graphics_get_build_info(dev_info,
|
||||
hard_code_pipeline_n,
|
||||
stage,
|
||||
&ctx->common_data[stage],
|
||||
&ctx->stage_data,
|
||||
explicit_const_usage);
|
||||
|
||||
continue;
|
||||
}
|
||||
|
||||
if (!ctx->nir[stage])
|
||||
continue;
|
||||
|
||||
ctx->rogue[stage] = pvr_nir_to_rogue(ctx, ctx->nir[stage]);
|
||||
if (!ctx->rogue[stage]) {
|
||||
ralloc_free(ctx);
|
||||
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
|
||||
}
|
||||
|
||||
ctx->binary[stage] = pvr_rogue_to_binary(ctx, ctx->rogue[stage]);
|
||||
if (!ctx->binary[stage]) {
|
||||
ralloc_free(ctx);
|
||||
return vk_error(device, VK_ERROR_OUT_OF_HOST_MEMORY);
|
||||
}
|
||||
}
|
||||
|
||||
if (pvr_hard_code_shader_required(&device->pdevice->dev_info) &&
|
||||
pvr_hard_code_graphics_get_flags(&device->pdevice->dev_info) &
|
||||
BITFIELD_BIT(MESA_SHADER_VERTEX)) {
|
||||
pvr_hard_code_graphics_vertex_state(&device->pdevice->dev_info,
|
||||
hard_code_pipeline_n,
|
||||
&gfx_pipeline->vertex_shader_state);
|
||||
} else {
|
||||
pvr_vertex_state_init(gfx_pipeline,
|
||||
|
|
@ -1485,8 +1521,11 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
|
|||
if (result != VK_SUCCESS)
|
||||
goto err_free_build_context;
|
||||
|
||||
if (requires_hard_coding) {
|
||||
if (pvr_hard_code_shader_required(&device->pdevice->dev_info) &&
|
||||
pvr_hard_code_graphics_get_flags(&device->pdevice->dev_info) &
|
||||
BITFIELD_BIT(MESA_SHADER_FRAGMENT)) {
|
||||
pvr_hard_code_graphics_fragment_state(
|
||||
&device->pdevice->dev_info,
|
||||
hard_code_pipeline_n,
|
||||
&gfx_pipeline->fragment_shader_state);
|
||||
} else {
|
||||
|
|
@ -1507,13 +1546,6 @@ pvr_graphics_pipeline_compile(struct pvr_device *const device,
|
|||
* case the optimization doesn't happen.
|
||||
*/
|
||||
|
||||
if (requires_hard_coding) {
|
||||
pvr_hard_code_graphics_inject_build_info(hard_code_pipeline_n,
|
||||
ctx,
|
||||
&vert_explicit_const_usage,
|
||||
&frag_explicit_const_usage);
|
||||
}
|
||||
|
||||
/* TODO: The programs we use are hard coded for now, but these should be
|
||||
* selected dynamically.
|
||||
*/
|
||||
|
|
|
|||
Loading…
Reference in New Issue