Commit Graph

126569 Commits

Author SHA1 Message Date
Rob Clark b721d336da freedreno: slurp in rnndb
Pull in all of $envytools/rnndb (including display, etc) from envytools
commit 6ccdda33ac4d88e19d2a70e1b4edaaab5ec4b026

This changes the directory structure to match the organization in the
envytools tree.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>
2020-07-28 09:45:08 +00:00
Rob Clark 7de0842d42 freedreno: make gen_header.py check parent directory
With the next commit, the xml files will be no longer be all in the same
directory.  But checking up a single directory level to resolve import
will be sufficient.

Signed-off-by: Rob Clark <robdclark@chromium.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6070>
2020-07-28 09:45:08 +00:00
Bas Nieuwenhuizen 05b2783270 radv: Fix host->host signalling with legacy timeline semaphores.
Fixes: 88d41367b8 "radv: Add timelines with a VK_KHR_timeline_semaphore impl."
Reviewed-by: Dave Airlie <airlied@redhat.com>
Tested-by: Andres Rodriguez <andresx7@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6097>
2020-07-28 09:33:59 +00:00
Dave Airlie 9746e84a7e radv: cleanup locking around timeline waiting.
Just noticed in passing that this looked extra complicated,
Bas said it was for legacy design reasons, so clean it up.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6099>
2020-07-28 12:31:30 +10:00
Chris Forbes a0a70879c5 bifrost: Add support for nir_op_imul
Unfortunately this doesn't map nicely to the existing instruction
classes, so we'll make a new one for now.

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6091>
2020-07-28 01:13:09 +00:00
Chris Forbes 718d444e51 bifrost: Add support for nir_op_uge
Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6091>
2020-07-28 01:13:09 +00:00
Chris Forbes 946ff9b439 bifrost: Add support for nir_op_ishl
Bifrost's bitwise ops include the shift capability. Previously we had
hardcoded the shift to zero in all cases.

There's room in future to emit slightly better code if a shift and a
bitwise operation can be folded together, but not going after that for
now.

This change also removes the separate BI_SHIFT instruction class as
BI_BITWISE can cover both cases.

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6091>
2020-07-28 01:13:09 +00:00
Chris Forbes 539ea08736 bifrost: Add support for nir_op_inot
Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6091>
2020-07-28 01:13:09 +00:00
Caio Marcelo de Oliveira Filho 12dd5455f4 spirv: Handle most execution modes earlier
For convenience in e68871f6a4 ("spirv: Handle constants and types
before execution modes") we moved all execution mode parsing after the
constants and types, so that those using OpExecutionModeId could be
handled together.

Later in 84781e1f1d ("spirv/nir: keep track of SPV_KHR_float_controls
execution modes") we had to parse certain non-ID execution modes
before handling constants.

Instead of handling just the float controls related execution modes
early, handle all modes that don't need an ID.  This is a more
"natural" split and will allow other type handling to rely on
execution mode in the future.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6062>
2020-07-27 17:10:23 +00:00
Chris Forbes ef781880eb bifrost: Add lowering for b2i32
Since the bool representation is 0/~0, we can convert to int
just by &1.

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6079>
2020-07-27 16:53:52 +00:00
Chris Forbes 1a168c90a0 bifrost: Document d3d/gl comparison control bit
Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6079>
2020-07-27 16:53:52 +00:00
Chris Forbes ec37c7126d bifrost: Emit "d3d" variant of comparison instructions
The "d3d" variant uses ~0 as the true value. This is consistent
with NIR's nir_lower_bool_to_int32 pass.

Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6079>
2020-07-27 16:53:52 +00:00
Chris Forbes 0ffefad791 bifrost: Lower x->bool conversions to != 0
Signed-off-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6079>
2020-07-27 16:53:52 +00:00
Connor Abbott 8e8baecd6a tu: Enable resource dynamic indexing
This has actually worked since bindless support was merged.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6086>
2020-07-27 16:38:17 +00:00
Connor Abbott 8bc060ab81 ir3: Fix incorrect src flags for samp_tex
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6086>
2020-07-27 16:38:17 +00:00
Connor Abbott e73a8a2b39 ir3: Remove redundant samp_tex validation
It's already checked in ir3_validate. This way we don't have to fix it
up for bindless.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6086>
2020-07-27 16:38:17 +00:00
Connor Abbott 3adc23f667 ir3: Validate bindless samp_tex correctly
It's full instead of half precision, because the maximum number of
textures/samplers is much larger.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6086>
2020-07-27 16:38:17 +00:00
Connor Abbott d542bfc306 tu: Fix descriptor update templates with input attachments
Found via
dEQP-VK.binding_model.descriptorset_random.sets4.noarray.ubolimitlow.sbolimitlow.sampledimglow.outimgonly.noiub.nouab.frag.ialimitlow.0

Fixes: 159a1300ce ("turnip: input attachment descriptor set rework")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6087>
2020-07-27 12:36:36 +00:00
Jonathan Marek 9ece61269d turnip: fix SP_HS_UNKNOWN_A831 value for A650
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5765>
2020-07-27 12:17:38 +00:00
Jonathan Marek e646e77e18 turnip: use patchControlPoints for HS_INPUT_SIZE value
It should be calculated from patchControlPoints, not tcs_vertices_out.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5765>
2020-07-27 12:17:38 +00:00
Jonathan Marek da49a45351 turnip: move WFI out of draw state to fix a650 hangs
Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5765>
2020-07-27 12:17:38 +00:00
Jonathan Marek e5f4527f20 freedreno/ir3: fix wrong local_primitive_id_start type
When changing the patch to use an offset instead of a bool, the type was
accidentally left as bool.

Fixes: f472c98443 ("freedreno/ir3: add support for a650 tess shared storage")

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5765>
2020-07-27 12:17:38 +00:00
Bas Nieuwenhuizen 7cb4d4f24e vulkan/wsi: Convert usage of -1 to UINT32_MAX.
The integers are unsigned so they do the same but this makes it
locally more clear what happened.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6071>
2020-07-27 11:30:22 +00:00
Bas Nieuwenhuizen e1147caecb vulkan/wsi/x11: report device-group present rectangles with prime.
dEQP-VK.wsi.xlib.surface.query_devgroup_present_modes with prime
fail when 0 rectangles are reported. While I believe that test
tests this unintentionally (trying to test the VK_INCOMPLETE return),
I believe it makes sense to always return a rectangle.

In particular we require the data from the given rectangle for
presentation even if we use prime and given that prime is completely
transparent for the app it still counts as local from the perspective
as the application.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6071>
2020-07-27 11:30:22 +00:00
Daniel Schürmann af0bc71015 radv: call radv_nir_lower_ycbcr_textures after first optimizations
There might still be tex instructions with undef texture/sampler before
the first round of optimizations. No pipelinedb changes.

Fixes: 14a12b771d ('spirv: Rework our handling of images and samplers')
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6083>
2020-07-27 10:03:20 +00:00
David McFarland fffc287d44 radv: link with ld_args_build_id
This is needed for radv_device_get_cache_uuid to work correctly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6081>
2020-07-27 09:45:53 +00:00
Iago Toral Quiroga d1677c8f8c v3d/compiler: request fragment shader clip lowering to be vulkan compatible.
Vulkan allows fragment shaders to read gl_ClipDistance[], in which case
the SPIR-V compiler will inject a compact array variable at
VARYING_SLOT_CLIP_DIST0. Request the lowering to always work in terms
of a compact array variable so we don't have to care about the API
in use.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6022>
2020-07-27 08:25:57 +02:00
Iago Toral Quiroga 71d5c19241 v3d/compiler: handle compact varyings
We are going to need this in Vulkan because the SPIR-V compiler
defines clip distances as a single compact array of scalars, so
our compiler needs to know what to do with them.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6022>
2020-07-27 08:25:57 +02:00
Iago Toral Quiroga 17fd191eed nir/lower_clip: make the pass compatible with Vulkan semantics
Vulkan allows fragment shaders to read gl_ClipDistance[], in which
case the SPIR-V compiler inserts a single compact array variable for
VARYING_SLOW_CLIP_DIST0 and the lowering should not try to inject
its own variables, but instead work in terms of the existing one.
Vulkan drivers are expected to call this with use_clipdist_array set
to true to be consistent with this setup.

Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6022>
2020-07-27 08:25:57 +02:00
Bas Nieuwenhuizen 18fe130ec9 radv: Fix uninitialized variable in renderpass.
Fixes some dEQP-VK.renderpass2.* flakes. Valgrind:

Test case 'dEQP-VK.renderpass2.dedicated_allocation.attachment.8.724'..
==754520== Conditional jump or move depends on uninitialised value(s)
==754520==    at 0x575B21C: radv_layout_is_htile_compressed (radv_image.c:1690)
==754520==    by 0x572F470: radv_handle_depth_image_transition (radv_cmd_buffer.c:5855)
==754520==    by 0x572F2F2: radv_handle_image_transition (radv_cmd_buffer.c:6123)
==754520==    by 0x572EEC6: radv_handle_subpass_image_transition (radv_cmd_buffer.c:3385)
==754520==    by 0x572A104: radv_cmd_buffer_begin_subpass (radv_cmd_buffer.c:4843)
==754520==    by 0x572A007: radv_CmdBeginRenderPass (radv_cmd_buffer.c:4913)
==754520==    by 0x572A197: radv_CmdBeginRenderPass2 (radv_cmd_buffer.c:4921)

Why false?

A renderloop happens when the same attachment is both used as input
attachment and output (color, ds) attachment in a subpass. Of course
this doesn't happen outside of a renderpass and hence we can initialize
it to false at the start of the renderpass.

Fixes: 66131ceb8b "radv: Pass through render loop detection to internal layout decisions."
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Daniel Schürmann <daniel@schuermann.dev>
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3074
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6068>
2020-07-26 13:35:16 +00:00
Karol Herbst e2e89fb137 nir/lower_io: assert that offsets are used for shader_in
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Acked-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6059>
2020-07-25 08:51:48 +00:00
Christian Gmeiner 60915f87c7 etnaviv: do register setup only once
Register set setup should be done once at backend
initializaion, as ra_set_finalize is O(r^2*c^2).

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5996>
2020-07-24 20:01:04 +00:00
Christian Gmeiner 7ee146aad4 etnaviv: move shader_count to etna_compiler
Also fix data race on making the shader's id.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5996>
2020-07-24 20:01:04 +00:00
Christian Gmeiner 5839a7d64a etnaviv: introduce struct etna_compiler
This struct will be used to for state saved across compiler
invocations.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5996>
2020-07-24 20:01:04 +00:00
Connor Abbott 9e596cc2c2 tu: Enable vertex & fragment stores & atomics
Note that there are some extra tess fails, but they're probably
unrelated to the actual feature. There were also some xfails that were
created as part of an earlier attempt to enable the feature which were
fixed in the meantime, so remove them.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5738>
2020-07-24 18:43:40 +00:00
Connor Abbott f7f29a04b4 tu: Detect invalid-for-binning renderpass dependencies
This is all that was missing for stores & atomics.

Closes: #3196
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5738>
2020-07-24 18:43:40 +00:00
Connor Abbott d6d75fcd91 tu: Fix hangs for DS with no output
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5738>
2020-07-24 18:43:40 +00:00
Connor Abbott 7ad962bf89 tu: Fix empty blit scissor case
With vertexPipelineStoresAndAtomics enabled, fixes:
dEQP-VK.tessellation.invariance.one_minus_tess_coord_component.quads_fractional_even_spacing_cw_point_mode
dEQP-VK.tessellation.invariance.tess_coord_component_range.triangles_fractional_even_spacing_ccw_point_mode

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5738>
2020-07-24 18:43:40 +00:00
Jason Ekstrand 63cf8adb12 spirv: Also copy over binding information for atomic counters
I missed this if statement so atomic counters weren't getting bindings
and, when you have more than one of them, that meant they were all
getting combined into one.

Fixes: 3584cb09bc15 "spirv: Give atomic counters their own variable mode"
Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6060>
2020-07-24 18:17:38 +00:00
Connor Abbott 6cbdffd79c tu: Implement VK_KHR_draw_indirect_count
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6007>
2020-07-24 19:21:07 +02:00
Connor Abbott 52ec35f5a6 tu: Add missing wfi to tu6_emit_hw()
It needs to be there before changing CCU state. This was accidentally
deleted in f494799a7f when it should've
been moved.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6007>
2020-07-24 19:20:44 +02:00
Connor Abbott a0ca688a67 tu: Integrate WFI/WAIT_FOR_ME/WAIT_MEM_WRITES with cache tracking
Track them via pending_flush_bits. Previously WFI was only tracked in
flush_bits and WAIT_FOR_ME was emitted directly. This means that we don't
emit WAIT_FOR_ME or WAIT_FOR_IDLE if there wasn't a cache flush or other
write by the GPU. Also split up host writes from sysmem writes, as only
the former require WFI/WAIT_FOR_ME.

Along the way, I also realized that we were missing proper handling of
transform feedback counter writes which require WAIT_MEM_WRITES. Plumb
that through as well. And CmdDrawIndirectByteCountEXT needs a
WAIT_FOR_ME as it does not wait for WFI internally.

As an example of what this does, a typical barrier for transform
feedback with srcAccess = VK_TRANSFORM_FEEDBACK_WRITE_COUNTER_BIT_EXT
and dstAccess = VK_ACCESS_INDIRECT_COMMAND_READ_BIT used to emit on
A650:

- WAIT_FOR_IDLE

and now we emit:

- WAIT_MEM_WRITES
- WAIT_FOR_ME

So we've eliminated a useless WFI and added some necessary waits.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6007>
2020-07-24 19:20:44 +02:00
Connor Abbott cd78a7a5ff freedreno: Add INDIRECT_COUNT CP_DRAW_INDIRECT_MULTI variants
These have an indirect count which is loaded from an iova, and the
minimum is taken between the indirect and direct counts. Note, I also
had to fix gen_header.py to deal with the extra-long names we get.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6007>
2020-07-24 19:20:44 +02:00
Connor Abbott 8da31ee15f freedreno: Clean up CP_DRAW_MULTI_INDIRECT definition
Depends on the envytools changes to make the "addvariant" magic work in
order to decode this correctly, and to be able to print the register
names directly.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6007>
2020-07-24 19:20:44 +02:00
Jonathan Marek 1747f9fdd0 turnip: remove extra gmem alignment
Now that we clear the PITCHALIGN" field when filling GMEM input attachment
descriptors, we can get rid of the extra tile width alignment on a630/a640.

With the "block_align_shift" value change, this brings down the default
gmem_align from 16k to 4k on a630/a640 and down from 24k to 12k on a650,
to match the gallium driver.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5528>
2020-07-24 13:44:42 +00:00
Christian Gmeiner 8534f49bf9 etnaviv: explicitly set nir_variable_mode
No functional changes - fixes the following assert:
  nir_lower_io_impl: Assertion `!(modes & ~supported_modes)' failed.

Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5997>
2020-07-24 13:33:47 +00:00
Samuel Pitoiset 5b300bec9a radv: clean up remaining pipeline init functions
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5837>
2020-07-24 12:30:03 +00:00
Samuel Pitoiset 5575ce0a28 radv: remove useless return value to radv_pipeline_scratch_init()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5837>
2020-07-24 12:30:03 +00:00
Samuel Pitoiset 0721e2d1ab radv: add radv_pipeline_init_shader_stages_state()
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5837>
2020-07-24 12:30:03 +00:00
Samuel Pitoiset f3774ec9ac radv: constify all radv_pipeline_generate_*() helpers
To make clear that the pipeline should be read only.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5837>
2020-07-24 12:30:03 +00:00