bifrost: Add support for nir_op_ishl
Bifrost's bitwise ops include the shift capability. Previously we had hardcoded the shift to zero in all cases. There's room in future to emit slightly better code if a shift and a bitwise operation can be folded together, but not going after that for now. This change also removes the separate BI_SHIFT instruction class as BI_BITWISE can cover both cases. Signed-off-by: Chris Forbes <chrisforbes@google.com> Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6091>
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@ -1168,8 +1168,6 @@ bi_pack_fma(bi_clause *clause, bi_bundle bundle, bi_registers *regs)
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return bi_pack_fma_addmin(bundle.fma, regs);
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case BI_MOV:
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return bi_pack_fma_1src(bundle.fma, regs, BIFROST_FMA_OP_MOV);
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case BI_SHIFT:
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unreachable("Packing todo");
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case BI_SELECT:
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return bi_pack_fma_select(bundle.fma, regs);
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case BI_ROUND:
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@ -1733,7 +1731,6 @@ bi_pack_add(bi_clause *clause, bi_bundle bundle, bi_registers *regs, gl_shader_s
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case BI_MINMAX:
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return bi_pack_add_addmin(bundle.add, regs);
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case BI_MOV:
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case BI_SHIFT:
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case BI_STORE:
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unreachable("Packing todo");
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case BI_STORE_VAR:
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@ -149,7 +149,6 @@ bi_class_name(enum bi_class cl)
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case BI_MINMAX: return "minmax";
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case BI_MOV: return "mov";
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case BI_SELECT: return "select";
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case BI_SHIFT: return "shift";
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case BI_STORE: return "store";
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case BI_STORE_VAR: return "store_var";
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case BI_SPECIAL: return "special";
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@ -49,7 +49,6 @@ unsigned bi_class_props[BI_NUM_CLASSES] = {
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[BI_MOV] = BI_SCHED_ALL,
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[BI_FMOV] = BI_MODS | BI_SCHED_ALL,
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[BI_REDUCE_FMA] = BI_SCHED_FMA,
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[BI_SHIFT] = BI_SCHED_ALL,
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[BI_STORE] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD | BI_VECTOR | BI_DATA_REG_SRC,
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[BI_STORE_VAR] = BI_SCHED_HI_LATENCY | BI_SCHED_ADD | BI_VECTOR | BI_DATA_REG_SRC,
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[BI_SPECIAL] = BI_SCHED_ADD | BI_SCHED_SLOW,
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@ -516,6 +516,7 @@ bi_class_for_nir_alu(nir_op op)
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case nir_op_ior:
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case nir_op_ixor:
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case nir_op_inot:
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case nir_op_ishl:
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return BI_BITWISE;
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BI_CASE_CMP(nir_op_flt)
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@ -807,6 +808,16 @@ emit_alu(bi_context *ctx, nir_alu_instr *instr)
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alu.op.bitwise = BI_BITWISE_OR;
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alu.bitwise.src_invert[0] = true;
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alu.src[1] = BIR_INDEX_ZERO;
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/* zero shift */
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alu.src[2] = BIR_INDEX_ZERO;
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alu.src_types[2] = alu.src_types[1];
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break;
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case nir_op_ishl:
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alu.op.bitwise = BI_BITWISE_OR;
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/* move src1 to src2 and replace with zero. underlying op is (src0 << src2) | src1 */
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alu.src[2] = alu.src[1];
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alu.src_types[2] = alu.src_types[1];
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alu.src[1] = BIR_INDEX_ZERO;
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break;
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case nir_op_fmax:
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case nir_op_imax:
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@ -843,12 +854,21 @@ emit_alu(bi_context *ctx, nir_alu_instr *instr)
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break;
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case nir_op_iand:
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alu.op.bitwise = BI_BITWISE_AND;
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/* zero shift */
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alu.src[2] = BIR_INDEX_ZERO;
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alu.src_types[2] = alu.src_types[1];
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break;
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case nir_op_ior:
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alu.op.bitwise = BI_BITWISE_OR;
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/* zero shift */
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alu.src[2] = BIR_INDEX_ZERO;
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alu.src_types[2] = alu.src_types[1];
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break;
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case nir_op_ixor:
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alu.op.bitwise = BI_BITWISE_XOR;
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/* zero shift */
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alu.src[2] = BIR_INDEX_ZERO;
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alu.src_types[2] = alu.src_types[1];
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break;
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case nir_op_f2i32:
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alu.roundmode = BIFROST_RTZ;
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@ -889,10 +909,6 @@ emit_alu(bi_context *ctx, nir_alu_instr *instr)
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bi_fuse_cond(&alu, instr->src[0],
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&constants_left, &constant_shift, comps, false);
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#endif
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} else if (alu.type == BI_BITWISE) {
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/* Implicit shift argument... at some point we should fold */
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alu.src[2] = BIR_INDEX_ZERO;
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alu.src_types[2] = alu.src_types[1];
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}
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bi_emit(ctx, alu);
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@ -70,7 +70,6 @@ enum bi_class {
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BI_MOV,
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BI_REDUCE_FMA,
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BI_SELECT,
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BI_SHIFT,
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BI_STORE,
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BI_STORE_VAR,
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BI_SPECIAL, /* _FAST on supported GPUs */
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