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turnip: use patchControlPoints for HS_INPUT_SIZE value 

It should be calculated from patchControlPoints, not tcs_vertices_out.

Signed-off-by: Jonathan Marek <jonathan@marek.ca>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5765>
This commit is contained in:
Jonathan Marek 2020-07-14 10:11:11 -04:00 committed by Marge Bot
parent da49a45351
commit e646e77e18
6 changed files with 13 additions and 13 deletions
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4
src/freedreno/registers/a6xx.xml
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@ -2765,8 +2765,8 @@ to upconvert to 32b float internally?
<reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX" low="0" high="5" type="uint"/>
<!-- always 0x0 ? -->
<reg32 offset="0x9801" name="PC_UNKNOWN_9801">
<bitfield name="UNK0" low="0" high="10"/>
<reg32 offset="0x9801" name="PC_HS_INPUT_SIZE">
<bitfield name="SIZE" low="0" high="10"/>
<bitfield name="UNK13" pos="13"/>
</reg32>

2
src/freedreno/vulkan/tu_clear_blit.c
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@ -451,7 +451,7 @@ r3d_common(struct tu_cmd_buffer *cmd, struct tu_cs *cs, bool blit, uint32_t num_
tu_cs_emit_regs(cs, A6XX_PC_PRIMITIVE_CNTL_0());
tu_cs_emit_regs(cs, A6XX_VFD_CONTROL_0());
tu6_emit_vpc(cs, &vs, NULL, NULL, NULL, &fs);
tu6_emit_vpc(cs, &vs, NULL, NULL, NULL, &fs, 0);
/* REPL_MODE for varying with RECTLIST (2 vertices only) */
tu_cs_emit_regs(cs, A6XX_VPC_VARYING_INTERP_MODE(0, 0));

1
src/freedreno/vulkan/tu_cmd_buffer.c
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@ -816,7 +816,6 @@ tu6_init_hw(struct tu_cmd_buffer *cmd, struct tu_cs *cs)
tu_cs_emit_regs(cs, A6XX_VPC_SO_DISABLE(true));
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9801, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_UNKNOWN_9980, 0);
tu_cs_emit_write_reg(cs, REG_A6XX_PC_PRIMITIVE_CNTL_6, 0);

14
src/freedreno/vulkan/tu_pipeline.c
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@ -740,7 +740,8 @@ tu6_emit_vpc(struct tu_cs *cs,
const struct ir3_shader_variant *hs,
const struct ir3_shader_variant *ds,
const struct ir3_shader_variant *gs,
const struct ir3_shader_variant *fs)
const struct ir3_shader_variant *fs,
uint32_t patch_control_points)
{
/* note: doesn't compile as static because of the array regs.. */
const struct reg_config {
@ -916,9 +917,8 @@ tu6_emit_vpc(struct tu_cs *cs,
tu_cs_emit(cs, hs_info->tess.tcs_vertices_out);
/* Total attribute slots in HS incoming patch. */
tu_cs_emit_pkt4(cs, REG_A6XX_PC_UNKNOWN_9801, 1);
tu_cs_emit(cs,
hs_info->tess.tcs_vertices_out * vs->output_size / 4);
tu_cs_emit_pkt4(cs, REG_A6XX_PC_HS_INPUT_SIZE, 1);
tu_cs_emit(cs, patch_control_points * vs->output_size / 4);
tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
tu_cs_emit(cs, vs->output_size);
@ -1371,6 +1371,8 @@ tu6_emit_program(struct tu_cs *cs,
const struct ir3_shader_variant *gs = builder->variants[MESA_SHADER_GEOMETRY];
const struct ir3_shader_variant *fs = builder->variants[MESA_SHADER_FRAGMENT];
gl_shader_stage stage = MESA_SHADER_VERTEX;
uint32_t cps_per_patch = builder->create_info->pTessellationState ?
builder->create_info->pTessellationState->patchControlPoints : 0;
STATIC_ASSERT(MESA_SHADER_VERTEX == 0);
@ -1403,7 +1405,7 @@ tu6_emit_program(struct tu_cs *cs,
tu_cs_emit_pkt4(cs, REG_A6XX_SP_HS_UNKNOWN_A831, 1);
tu_cs_emit(cs, 0);
tu6_emit_vpc(cs, vs, hs, ds, gs, fs);
tu6_emit_vpc(cs, vs, hs, ds, gs, fs, cps_per_patch);
tu6_emit_vpc_varying_modes(cs, fs);
if (fs) {
@ -1423,8 +1425,6 @@ tu6_emit_program(struct tu_cs *cs,
}
if (gs || hs) {
uint32_t cps_per_patch = builder->create_info->pTessellationState ?
builder->create_info->pTessellationState->patchControlPoints : 0;
tu6_emit_geom_tess_consts(cs, vs, hs, ds, gs, cps_per_patch);
}
}

3
src/freedreno/vulkan/tu_private.h
View File

@ -1188,7 +1188,8 @@ tu6_emit_vpc(struct tu_cs *cs,
const struct ir3_shader_variant *hs,
const struct ir3_shader_variant *ds,
const struct ir3_shader_variant *gs,
const struct ir3_shader_variant *fs);
const struct ir3_shader_variant *fs,
uint32_t patch_control_points);
void
tu6_emit_fs_inputs(struct tu_cs *cs, const struct ir3_shader_variant *fs);

2
src/gallium/drivers/freedreno/a6xx/fd6_program.c
View File

@ -565,7 +565,7 @@ setup_stateobj(struct fd_ringbuffer *ring, struct fd_screen *screen,
OUT_RING(ring, hs_info->tess.tcs_vertices_out);
/* Total attribute slots in HS incoming patch. */
OUT_PKT4(ring, REG_A6XX_PC_UNKNOWN_9801, 1);
OUT_PKT4(ring, REG_A6XX_PC_HS_INPUT_SIZE, 1);
OUT_RING(ring, hs_info->tess.tcs_vertices_out * vs->output_size / 4);
OUT_PKT4(ring, REG_A6XX_SP_HS_UNKNOWN_A831, 1);