Marek Olšák
50d7553600
radeonsi: add a debug option to enable NGG culling for tessellation
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5524 >
2020-06-30 10:56:41 +00:00
Marek Olšák
9049e39804
radeonsi: always use Wave32 for GS fast launch, because Wave64 hangs
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5524 >
2020-06-30 10:56:41 +00:00
Marek Olšák
1c1d34a67a
radeonsi: rename init_config states to cs_preamble states
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5603 >
2020-06-26 07:02:57 +00:00
Marek Olšák
430d384c31
radeonsi: set BIG_PAGE fields on gfx10.3
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5383 >
2020-06-09 16:17:36 +00:00
Marek Olšák
85a6bcca61
radeonsi: pass at most 3 images and/or shader buffers via user SGPRs for compute
...
This should slightly decrease shader lifetime.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5209 >
2020-06-02 20:47:49 +00:00
Marek Olšák
7b6b35c6b5
radeonsi: move resetting tracked registers into a new function
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5095 >
2020-05-23 03:45:07 -04:00
Marek Olšák
7356144fe4
radeonsi: disable the L2 cache for most CPU mappings of textures
...
for faster blits over PCIe and no need to flush L2
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935 >
2020-05-15 22:12:35 +00:00
Marek Olšák
2c4c1b0499
radeonsi: rename SI_RESOURCE_FLAG_TRANSFER to FORCE_LINEAR
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4935 >
2020-05-15 22:12:35 +00:00
Pierre-Eric Pelloux-Prayer
8873ea0e25
radeonsi: determine secure flag must be set for gfx IB
...
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4401 >
2020-05-11 10:25:53 +02:00
Blaž Tomažič
808eb20186
radeonsi: Fix omitted flush when moving suballocated texture
...
Fixes: 5e805cc74b
"radeonsi: flush the context after resource_copy_region for buffer exports"
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4925 >
2020-05-07 17:00:08 -04:00
Marek Olšák
0d83e7f4b9
radeonsi: enable TC-compatible HTILE on demand for best Z/S performance
...
I haven't measured this, but it can only help.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4866 >
2020-05-05 16:27:29 +00:00
Pierre-Eric Pelloux-Prayer
64662dd5ba
radeonsi: add workaround for issue 2647
...
For unknown reasons pixel shaders in KSP game get executed with
infinite interpolation coefficients and this causes an infinite
loop in the shader.
This commit adds a hacky workaround that kills pixel shaders if
invalid interp coeffs are detected and enables it for KSP.
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2174
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2647
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4700 >
2020-05-05 09:41:14 +00:00
Marek Olšák
d6acdbd935
radeonsi: implement and use compute-based DCC decompression on gfx9-10
...
DCC_DECOMPRESS doesn't work. Instead of trying to figure out why,
use a compute blit where the load is compressed and the store is
uncompressed.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761 >
2020-04-30 22:27:31 +00:00
Marek Olšák
d3da73954a
radeonsi: add SI_IMAGE_ACCESS_DCC_OFF to ignore DCC for shader images
...
A shader-based DCC decompress pass will use this.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4761 >
2020-04-30 22:27:31 +00:00
Pierre-Eric Pelloux-Prayer
d7008fe46a
radeonsi: switch to 3-spaces style
...
Generated automatically using clang-format and the following config:
AlignAfterOpenBracket: true
AlignConsecutiveMacros: true
AllowAllArgumentsOnNextLine: false
AllowShortCaseLabelsOnASingleLine: false
AllowShortFunctionsOnASingleLine: false
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BinPackParameters: true
BreakBeforeBraces: Custom
ColumnLimit: 100
ContinuationIndentWidth: 3
Cpp11BracedListStyle: false
Cpp11BracedListStyle: true
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IncludeBlocks: Regroup
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PenaltyBreakBeforeFirstCallParameter: 1
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SpaceAfterCStyleCast: false
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SpacesInContainerLiterals: false
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4319 >
2020-03-30 11:05:52 +00:00
Marek Olšák
4ef1c8d60b
radeonsi/gfx10: fix the wave size for compute-based culling
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4269 >
2020-03-28 00:58:34 +00:00
Pierre-Eric Pelloux-Prayer
771f16cf61
radeonsi: remove AMD_DEBUG=sisched option
...
sisched is not maintained anymore in LLVM.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4059 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4059 >
2020-03-06 11:35:12 +01:00
Pierre-Eric Pelloux-Prayer
a803d41248
radeonsi: move AMD_DEBUG tests to AMD_TEST
...
AMD_DEBUG env var is stored in a 64 bits int and has 64 different values.
This commit makes some space by moving the test* special values to AMD_TEST.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3492 >
2020-01-27 09:29:10 +01:00
Marek Olšák
c046551e60
radeonsi: print shader cache stats with AMD_DEBUG=cache_stats
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929 >
2020-01-24 20:29:29 -05:00
Marek Olšák
0db74f479b
radeonsi: use the live shader cache
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/2929 >
2020-01-24 20:29:29 -05:00
Marek Olšák
735a3ba007
radeonsi/gfx10: enable GS fast launch for triangles and strips with NGG culling
...
Only non-indexed triangle lists and strips are supported. This increases
performance if there is something to cull.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
8db00a51f8
radeonsi/gfx10: implement NGG culling for 4x wave32 subgroups
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-20 16:16:11 -05:00
Marek Olšák
df34fa14bb
radeonsi: don't invoke decompression inside internal launch_grid
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Decompress resources properly but don't do it inside launch_grid
to prevent recursion.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Cc: 19.3 <mesa-stable@lists.freedesktop.org>
2020-01-20 15:40:08 -05:00
Marek Olšák
8070402a30
radeonsi: separate code computing info for small primitive culling
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-15 14:59:11 -05:00
Pierre-Eric Pelloux-Prayer
7b0b085c94
radeonsi: drop the negation from fmask_is_not_identity
...
This change eases code reading ("fmask_is_identity = true" is clearer than
"fmask_is_not_identity = false").
Initialization is not changed so fmask_is_identity is false when a texture is
created.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Tested-by: Marge Bot <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174 >
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3174 >
2020-01-15 10:10:15 +00:00
Marek Olšák
5fa2ab831e
radeonsi: fork tgsi_shader_info and tgsi_tessctrl_info
...
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Marek Olšák
7f4a54d5bd
radeonsi: remove TGSI from comments
...
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Marek Olšák
b1badf4ad6
radeonsi: rename DBG_NO_TGSI -> DBG_NO_NIR
...
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2020-01-14 18:46:07 -05:00
Marek Olšák
2bb88b2fdc
radeonsi: don't enable VBOs in user SGPRs if compute-based culling can be used
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-13 15:57:07 -05:00
Marek Olšák
363b4027fc
radeonsi: put up to 5 VBO descriptors into user SGPRs
...
gfx6-8: 1 VBO descriptor in user SGPRs
gfx9-10: 5 VBO descriptors in user SGPRs
We no longer pull up to 5 VBO descriptors from GTT when SDMA is disabled.
Totals from affected shaders:
SGPRS: 1110528 -> 1170528 (5.40 %)
VGPRS: 952896 -> 951936 (-0.10 %)
Spilled SGPRs: 83 -> 61 (-26.51 %)
Spilled VGPRs: 0 -> 0 (0.00 %)
Private memory VGPRs: 0 -> 0 (0.00 %)
Scratch size: 0 -> 0 (0.00 %) dwords per thread
Code Size: 23766296 -> 22843920 (-3.88 %) bytes
LDS: 0 -> 0 (0.00 %) blocks
Max Waves: 179344 -> 179344 (0.00 %)
Wait states: 0 -> 0 (0.00 %)
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-13 15:57:07 -05:00
Marek Olšák
c278c73f13
radeonsi: add si_context::num_vertex_elements
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-13 15:57:07 -05:00
Marek Olšák
269953e779
radeonsi/gfx9: force the micro tile mode for MSAA resolve correctly on gfx9
...
Fixes: 69ea473
"amd/addrlib: update to the latest version"
Closes : #2325
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-09 16:28:28 -05:00
Marek Olšák
fd84e422b6
radeonsi: clean up messy si_emit_rasterizer_prim_state
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2020-01-08 15:48:49 -05:00
Marek Olšák
991328498b
radeonsi: move SI and CIK+ SDMA code into 1 common function for cleanups
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:35 -05:00
Marek Olšák
3c265c2586
radeonsi: rename dma_cs -> sdma_cs
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:33 -05:00
Marek Olšák
cd6a4f7631
radeonsi: add AMD_DEBUG=nodmacopyimage for debugging
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:32 -05:00
Marek Olšák
0c9e7a67f9
radeonsi: add AMD_DEBUG=nodmaclear for debugging
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:30 -05:00
Marek Olšák
503bd821fa
radeonsi: rename SDMA debug flags
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-By: Timur Kristóf <timur.kristof@gmail.com>
2020-01-06 15:38:11 -05:00
Marek Olšák
aa3df12fc2
radeonsi/gfx10: enable NGG passthrough for eligible shaders
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-12-27 13:50:57 -05:00
Pierre-Eric Pelloux-Prayer
f5c1cb2383
radeonsi: dcc dirty flag
...
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-10 09:25:28 +01:00
Sonny Jiang
6c901f0675
radeonsi: use compute shader for clear 12-byte buffer
...
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-12-09 23:25:57 -05:00
Dylan Baker
ee4f1bc187
util: rename PIPE_ARCH_*_ENDIAN to UTIL_ARCH_*_ENDIAN
...
As requested by Tim.
This was generated with:
grep 'PIPE_ARCH_.*_ENDIAN' -rIl | xargs sed -ie 's@PIPE_ARCH_\(.*\)_ENDIAN@UTIL_ARCH_\1_ENDIAN@'g
v2: - add this patch
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-05 16:39:55 +00:00
Dylan Baker
f9f60da813
util/u_endian: set PIPE_ARCH_*_ENDIAN to 1
...
This will allow it to be used as a drop in replacement for
_mesa_little_endian in a number of cases.
v2: - Always define PIPE_ARCH_LITTLE_ENDIAN and PIPE_ARCH_BIG_ENDIAN,
define the one that reflects the host system to 1 and the other to 0
- replace all uses of #ifdef, #ifndef, and #if defined() with #if
and #if ! with PIPE_ARCH_*_ENDIAN
Reviewed-by: Eric Engestrom <eric@engestrom.ch>
2019-11-05 16:39:55 +00:00
Marek Olšák
4d1e43badb
radeonsi: initialize shader compilers in threads on demand
...
It takes a noticable amount of time with piglit.
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2019-10-28 21:36:18 -04:00
Marek Olšák
438ede3ca3
radeonsi: call the reset callback if get_device_reset_status returns a failure
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-10-17 14:56:24 -04:00
Marek Olšák
095a58204d
radeonsi: expand FMASK before MSAA image stores are used
...
Image stores don't use FMASK, so we have to turn it into identity.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-10-09 17:12:36 -04:00
Marek Olšák
0f7c9dad44
radeonsi: allocate planar multimedia formats in 1 buffer
...
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-10-09 17:06:54 -04:00
Marek Olšák
eec7b0a865
radeonsi: use simple_mtx_t instead of mtx_t
...
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2019-10-07 20:05:07 -04:00
Marek Olšák
235ebe9163
radeonsi/gfx10: fix corruption for chips with harvested TCCs
...
Cc: 19.2 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-09-30 13:36:20 -04:00
Marek Olšák
ef919d8dcb
radeonsi: remove redundant si_texture offset and size fields
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-09-09 23:43:03 -04:00
Marek Olšák
360cf3c4b0
radeonsi: fix scratch buffer WAVESIZE setting leading to corruption
...
Cc: 19.2 19.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:52:32 -04:00
Marek Olšák
467df4b90a
radeonsi/gfx10: add AMD_DEBUG=nongg
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:16:08 -04:00
Marek Olšák
e121d75de9
radeonsi/gfx10: add as_ngg variant for VS as ES to select Wave32/64
...
Legacy GS only works with Wave64.
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-27 16:16:08 -04:00
Samuel Pitoiset
fd54fc85aa
ac: add has_ls_vgpr_init_bug to ac_gpu_info
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-27 08:04:47 +02:00
Samuel Pitoiset
1bf2572dff
ac: add has_msaa_sample_loc_bug to ac_gpu_info
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-27 08:04:44 +02:00
Samuel Pitoiset
021feb1bf6
ac: add rbplus_allowed to ac_gpu_info
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-27 08:04:41 +02:00
Samuel Pitoiset
b55919cf2a
ac: add has_gfx9_scissor_bug to ac_gpu_info
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-27 08:04:32 +02:00
Samuel Pitoiset
2b9c371575
ac: add cpdma_prefetch_writes_memory to ac_gpu_info
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-27 08:04:29 +02:00
Samuel Pitoiset
63c0b89b8f
ac: add has_rbplus to ac_gpu_info
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-27 08:04:19 +02:00
Samuel Pitoiset
44a46c09de
ac: add has_dcc_constant_encode to ac_gpu_info
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-27 08:04:16 +02:00
Samuel Pitoiset
c08401f035
ac: add has_distributed_tess to ac_gpu_info
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-27 08:04:11 +02:00
Samuel Pitoiset
d62d2840c4
ac: add has_clear_state to ac_gpu_info
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-08-27 08:04:05 +02:00
Marek Olšák
5d37194d43
radeonsi: remove the unsafemath debug option
...
unlikely to be used in the future
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-19 17:23:38 -04:00
Marek Olšák
91227a1e17
radeonsi/gfx10: add global use_ngg and use_ngg_streamout flags
...
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:09:02 -04:00
Marek Olšák
8d90157d49
radeonsi: make sure that rasterizer state != NULL and remove all NULL checking
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:08:39 -04:00
Marek Olšák
8b8819e88a
radeonsi: make sure that DSA state != NULL and remove all NULL checking
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:08:39 -04:00
Marek Olšák
b758eed9c3
radeonsi: make sure that blend state != NULL and remove all NULL checking
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-08-06 17:08:39 -04:00
Marek Olšák
417ab8ef6b
radeonsi: add AMD_DEBUG=nogfx for testing
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
2019-07-29 17:52:53 -04:00
Marek Olšák
47f41af06c
radeonsi: return success from vi_dcc_clear_level to simplify callers
...
Reviewed-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-19 20:16:54 -04:00
Marek Olšák
1d82240f55
radeonsi/gfx10: add debug options to enable/disable Wave32
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-19 20:16:19 -04:00
Marek Olšák
8f72f137ad
radeonsi/gfx10: add as_ngg variant for TES as ES to select Wave32/64
...
Legacy GS has to use Wave64, so TES before GS has to use Wave64 too.
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-19 20:16:19 -04:00
Marek Olšák
88efb63caf
radeonsi/gfx10: implement Wave32
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-19 20:16:19 -04:00
Marek Olšák
7f0ada3f3e
radeonsi/gfx10: set GE_CTNL.PACKET_TO_ONE_PA for NGG
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-07-19 20:16:19 -04:00
Samuel Pitoiset
e510c5ee3b
ac: import ac_get_compute_resource_limits() from RadeonSI
...
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-12 17:47:11 +02:00
Marek Olšák
d7e80ba1e7
radeonsi: set FLUSH_ON_BINNING_TRANSITION when needed
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2019-07-09 17:24:16 -04:00
Marek Olšák
9dbe63ceea
radeonsi/gfx10: use the new scan converter when binning is disabled
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2019-07-09 17:24:16 -04:00
Marek Olšák
5b50fb9b7f
radeonsi/gfx10: no need to invalidate L2 for framebuffer -> texture coherency
...
Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Acked-by: Dave Airlie <airlied@redhat.com>
2019-07-09 17:24:16 -04:00
Marek Olšák
f66ee5af2f
radeonsi: determine the rasterization primitive type accurately (v2)
...
v2: reworked version to fix bugs and make it more efficient
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
b680f723f8
radeonsi/gfx10: export correct PrimitiveID from NGG vertex shaders
...
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
07aacdbfd5
radeonsi/gfx10: add a workaround for stencil HTILE with mipmapping
...
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
6eb219e963
radeonsi/gfx10: fix intensity formats
...
move the ALPHA_IS_ON_MSB fixup into vi_alpha_is_on_msb
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Marek Olšák
6944f99176
radeonsi/gfx10: allocate GDS BOs for streamout
...
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Nicolai Hähnle
792a638b03
radeonsi/gfx10: implement streamout-related queries
...
The NGG hardware pipeline doesn't track these statistics automatically,
and in fact *cannot* track them automatically when API geometry shaders
are involved, so we accumulate statistics in the shader using atomic
adds.
This implementation accumulates statistics via the memory system and
the RW buffer descriptor setup. We could use GDS, but since these
atomics aren't latency-sensitive, that basically just trades off
L2$ bandwidth vs. export bus bandwidth. One single memory transaction
per shader workgroup doesn't seem too bad. The result ring buffer in
memory is needed either way to avoid pipeline stalls.
The shader code contains the atomic unconditionally, though the
GFX10_GS_QUERY_BUF is a null buffer when no queries are active. The
atomic is simply discarded by the shader hardware in that case.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:13 -04:00
Nicolai Hähnle
5726ec0d24
radeonsi/gfx10: implement si_build_vgt_shader_config
...
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
Nicolai Hähnle
b45c3debe8
radeonsi/gfx10: keep track of whether NGG is used
...
We always use NGG by default, except when tessellation is enabled with
extreme geometry shader amplification.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
Nicolai Hähnle
7bb9bb0540
radeonsi/gfx10: implement gfx10_emit_cache_flush
...
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
Nicolai Hähnle
0c6c6810bd
radeonsi/gfx10: add si_context::emit_cache_flush
...
The introduction of GCR_CNTL makes cache flush handling on gfx10
sufficiently different that it makes sense to just use a separate
function.
Since emit_cache_flush is called quite early during context init,
we initialize the pointer explicitly in si_create_context.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
Nicolai Hähnle
08e2a62b07
radeonsi/gfx10: implement DB registers
...
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
Nicolai Hähnle
372652bccc
radeonsi/gfx10: set CB registers
...
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
Nicolai Hähnle
595a7f7c47
radeonsi/gfx10: add pipe_screen::make_texture_descriptor
...
Texture descriptors in gfx10 are very different.
Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-07-03 15:51:12 -04:00
Marek Olšák
c53e6ea05d
radeonsi: use a fragment shader blit instead of DB->CB copy for ZS CPU mappings
...
This mainly removes and simplifies code that is no longer needed.
There were some issues with the DB->CB stencil copy on gfx10, so let's
just use a fragment shader blit for all ZS mappings. It's more reliable.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2019-07-03 15:51:12 -04:00
Marek Olšák
1d6e358c36
radeonsi: rename and re-document cache flush flags
...
SMEM and VMEM caches are L0 on gfx10.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-24 21:04:10 -04:00
Nicolai Hähnle
610e1a81f7
radeonsi: refactor si_update_vgt_shader_config
...
We'll have to extend this at some point, and using a bitfield union in
this way makes it easier to get the right index without excessive
branching.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-06-24 21:04:10 -04:00
Nicolai Hähnle
bf8a1ca902
radeonsi: use the new run-time linker for shaders
...
v2:
- fix a memory leak
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-06-12 20:28:23 -04:00
Marek Olšák
b5697c311b
Change a few frequented uses of DEBUG to !NDEBUG
...
debugoptimized builds don't define NDEBUG, but they also don't define
DEBUG. We want to enable cheap debug code for these builds.
I only chose those occurences that I care about.
Reviewed-by: Mathias Fröhlich <Mathias.Froehlich@web.de>
2019-05-29 21:13:35 -04:00
Marek Olšák
894e017c9c
r600+radeonsi: use ctx_query_reset_status on radeon
...
This allows a nice cleanup, because the winsys always handles it.
2019-05-16 13:15:36 -04:00
Marek Olšák
78e35df52a
radeonsi: update buffer descriptors in all contexts after buffer invalidation
...
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108824
Cc: 19.1 <mesa-stable@lists.freedesktop.org>
2019-05-16 13:15:36 -04:00
Marek Olšák
9f505ce21d
radeonsi: disable primitive restart for triangles for DiRT Rally
...
It may decrease performance and it prevents compute-based primitive culling.
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-05-16 13:13:36 -04:00
Marek Olšák
0252fb92b8
radeonsi: add primitive culling stats to the HUD
...
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-05-16 13:13:36 -04:00
Marek Olšák
c9b7a37b8f
radeonsi: cull primitives with async compute for large draw calls
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-05-16 13:13:34 -04:00
Marek Olšák
07c83d25fd
radeonsi: add a cs parameter into si_cp_copy_data
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-05-16 13:06:57 -04:00
Marek Olšák
ce264d19a0
radeonsi: add a cs parameter into si_cp_release_mem
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-05-16 13:06:56 -04:00
Marek Olšák
9624855f13
radeonsi: add threadgroups_per_cu param into si_get_compute_resource_limits
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-05-16 13:06:54 -04:00
Marek Olšák
49a016ec5d
radeonsi: make si_initialize_compute reusable
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-05-16 13:06:51 -04:00
Marek Olšák
c44c6951d4
radeonsi: extract COMPUTE_RESOURCE_LIMITS code into a helper
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-05-16 13:06:49 -04:00
Marek Olšák
ccfcb9d818
ac: rename SI-CIK-VI to GFX6-GFX7-GFX8
...
Acked-by: Dave Airlie <airlied@redhat.com>
We already use GFX9 and I don't want us to have confusing naming
in the driver. GFXn naming is better from the driver perspective,
because it's the real version of the gfx portion of the hw. Also,
CIK means Bonaire-Kaveri-Kabini, it doesn't mean CI.
It shouldn't confuse our SDMA, UVD, VCE etc. code much. Those have
nothing to do with GFXn and they have their own version numbers.
2019-05-15 20:54:10 -04:00
Nicolai Hähnle
d814c21b1b
radeonsi: overhaul the vertex fetch fixup mechanism
...
The overall goal is to support unaligned loads from vertex buffers
natively on SI.
In the unaligned case, we fall back to the general case implementation in
ac_build_opencoded_load_format. Since this function is fully general,
we will also use it going forward for cases requiring fully manual format
conversions of dwords anyway.
This requires a different encoding of the fix_fetch array, which will now
contain the entire format information if a fixup is required.
Having to check the alignment of vertex buffers is awkward. To keep the
impact on the fast path minimal, the si_context will keep track of which
vertex buffers are (not) at least dword-aligned, while the
si_vertex_elements will note which vertex buffers have some (at most dword)
alignment requirement. Vertex buffers should be dword-aligned most of the
time, which allows a fast early-out in almost all cases.
Add the radeonsi_vs_fetch_always_opencode configuration variable for
testing purposes. Note that it can only be used reliably on LLVM >= 9,
because support for byte and short load is required.
v2:
- add a missing check to si_bind_vertex_elements
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-05-13 17:07:23 +02:00
Marek Olšák
383f406591
radeonsi: remove dirty slot masks from scissor and viewport states
...
All registers in the array need to be updated if any of them is changed.
Only apps writing gl_ViewportIndex were affected by this bug.
2019-04-25 11:49:38 -04:00
Marek Olšák
440135e5a0
radeonsi/gfx9: rework the gfx9 scissor bug workaround (v2)
...
Needed to track context rolls caused by streamout and ACQUIRE_MEM.
ACQUIRE_MEM can occur outside of draw calls.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=110355
v2: squashed patches and done more rework
Cc: 19.0 <mesa-stable@lists.freedesktop.org>
2019-04-25 11:49:38 -04:00
Nicolai Hähnle
8bef4df196
radeonsi: add si_debug_options for convenient adding/removing of options
...
Move the definition of radeonsi_clear_db_cache_before_clear there,
as well as radeonsi_enable_nir.
This removes the AMD_DEBUG=nir option.
We currently still have two places for options: the driconf machinery
and AMD_DEBUG/R600_DEBUG. If we are to have a single place for options,
then the driconf machinery should be preferred since it's more flexible.
The only downside of the driconf machinery was that adding new options
was quite inconvenient. With this change, a simple boolean option can
be added with a single line of code, same as for AMD_DEBUG.
One technical limitation of this particular implementation is that while
almost all driconf features are available, the translation machinery doesn't
pick up the description strings for options added in si_debvug_options. In
practice, translations haven't been provided anyway, and this is intended
for developer options, so I'm not too worried. It could always be added
later if anybody really cares.
v2:
- use bool instead of uint8_t for options
- si_debug_options.inc -> si_debug_options.h
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2019-04-25 12:31:02 +02:00
Marek Olšák
951d60f8cd
radeonsi: delay adding BOs at the beginning of IBs until the first draw
...
so that bound compute shader resources won't be added when they are not
needed and same for graphics.
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23 11:36:36 -04:00
Marek Olšák
09bb8c8557
radeonsi: add helper si_get_minimum_num_gfx_cs_dwords
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23 11:36:34 -04:00
Marek Olšák
c59d238bb0
radeonsi: add si_cp_copy_data
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
Acked-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-04-23 11:36:33 -04:00
Marek Olšák
b58e5fb6f3
radeonsi: use CP DMA for the null const buffer clear on CIK
...
This is a workaround for a thread deadlock that I have no idea
why it occurs.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=108879
Fixes: 9b331e462e
Acked-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2019-04-22 16:05:52 -04:00
Marek Olšák
1f21396431
radeonsi: add support for displayable DCC for multi-RB chips
...
A compute shader is used to reorder DCC data from aligned to unaligned.
2019-04-04 09:53:24 -04:00
Marek Olšák
029bfa3d25
radeonsi: add ability to bind images as image buffers
...
so that we can bind DCC (texture) as an image buffer.
2019-04-04 09:53:24 -04:00
Marek Olšák
fe3bfd7971
radeonsi/gfx9: add support for PIPE_ALIGNED=0
...
Needed by displayable DCC.
We need to flush L2 after rendering if PIPE_ALIGNED=0 and DCC is enabled.
2019-04-04 09:53:24 -04:00
Marek Olšák
b9e02fe138
gallium: add pipe_grid_info::last_block
...
The OpenMAX state tracker will use this.
RadeonSI is adapted to use pipe_grid_info::last_block instead of its
internal state.
Acked-by: Leo Liu <leo.liu@amd.com>
2019-03-15 11:53:08 -04:00
Marek Olšák
a1378639ab
radeonsi: always use compute rings for clover on CI and newer (v2)
...
initialize all non-compute context functions to NULL.
v2: fix SI
2019-02-26 14:58:55 -05:00
Marek Olšák
edbd2c1ff5
radeonsi: use SDMA for uploading data through const_uploader
...
v2: use tc.stream_uploader in si buffer_transfer_map if not called from
the driver thread
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com> (v1)
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2019-02-20 21:04:29 -05:00
Marek Olšák
5068dec5de
radeonsi: clear allocator_zeroed_memory with SDMA
...
so that it can be used in parallel IBs.
This also removes the SO_FILLED_SIZE hack.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-02-06 11:17:21 -05:00
Marek Olšák
7d4c935654
radeonsi: initialize textures using DCC to black when possible
...
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2019-02-06 11:17:21 -05:00
Marek Olšák
a03ecbaeec
radeonsi: handle render_condition_enable in si_compute_clear_render_target
2019-02-04 18:46:25 -05:00
Sonny Jiang
984fd73515
radeonsi: use compute for clear_render_target when possible
...
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-02-04 18:46:25 -05:00
Marek Olšák
260ff57647
radeonsi: rename rbo, rbuffer to buf or buffer
...
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-01-22 13:34:01 -05:00
Marek Olšák
501ff90a95
radeonsi: rename r600_resource -> si_resource
...
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-01-22 13:32:18 -05:00
Marek Olšák
1cfbed7587
radeonsi: remove r600 from comments
...
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-01-22 12:26:45 -05:00
Sonny Jiang
1b25d340b7
radeonsi: use compute for resource_copy_region when possible
...
v2: marek: fix snorm8 blits
Signed-off-by: Sonny Jiang <sonny.jiang@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2019-01-22 12:24:35 -05:00
Jiang, Sonny
8daf5bb209
radeonsi: add compute_last_block to configure the partial block fields
2019-01-22 12:22:46 -05:00
Marek Olšák
4d5f8f39f3
radeonsi: move PKT3_WRITE_DATA generation into a helper function
...
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2019-01-22 12:14:26 -05:00
Marek Olšák
54bc87469a
radeonsi: make si_cp_wait_mem more configurable
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2019-01-02 15:01:54 -05:00
Marek Olšák
d28e208213
radeonsi: don't emit redundant PKT3_NUM_INSTANCES packets
...
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2019-01-02 15:01:50 -05:00
Nicolai Hähnle
e2b9329f17
radeonsi: move remaining perfcounter code into si_perfcounter.c
...
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-12-19 12:01:57 +01:00
Nicolai Hähnle
5c841a1b1e
radeonsi: rename SI_RESOURCE_FLAG_FORCE_TILING to clarify its purpose
...
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-12-19 12:01:39 +01:00
Marek Olšák
075fd5d8f2
radeonsi: add memory management stress tests for GDS
...
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-28 20:20:27 -05:00
Marek Olšák
d7a4fa91f0
radeonsi: allow si_cp_dma_clear_buffer to clear GDS from any IB
...
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-11-28 20:20:27 -05:00
Marek Olšák
9dc776f3f2
radeonsi: don't set the CB clear color registers for 0/1 clear colors on Raven2
...
and add has_dcc_constant_encode.
2018-11-09 14:55:04 -05:00
Marek Olšák
99835fff08
radeonsi/gfx9: set optimal OVERWRITE_COMBINER_WATERMARK
2018-10-30 16:03:02 -04:00
Marek Olšák
77bcbe712e
radeonsi: clamp point size to the limit
...
This fixes dEQP-GLES2.functional.rasterization.limits.points.
Broken by: ea039f789d
Tested-by: Jakob Bornecrantz <jakob@collabora.com>
2018-10-18 16:08:56 -04:00
Marek Olšák
fcc70e4855
radeonsi: track context rolls better for the Vega scissor bug workaround
...
We should get fewer context rolls with the SET_CONTEXT_REG optimization,
but it would have been for nothing if the scissor state rolled the context
anyway. Don't emit the scissor state if there is no context roll.
2018-10-16 17:23:25 -04:00
Marek Olšák
9b331e462e
radeonsi: use compute shaders for clear_buffer & copy_buffer
...
Fast color clears should be much faster. Also, fast color clears on
evicted buffers should be 200x faster on GFX8 and older.
2018-10-16 17:23:25 -04:00
Marek Olšák
ea039f789d
radeonsi: use higher subpixel precision (QUANT_MODE) for smaller viewports
2018-10-16 15:28:22 -04:00
Marek Olšák
41a6c3de1f
radeonsi: don't re-upload the sample position constant buffer repeatedly
2018-10-16 15:28:22 -04:00
Marek Olšák
fedc1fda30
radeonsi: save raster config in screen, add se_tile_repeat
2018-10-16 15:28:22 -04:00
Marek Olšák
67f02cf810
radeonsi: add GDS support to CP DMA
2018-10-16 15:28:22 -04:00
Marek Olšák
0d05581578
radeonsi: rename si_gfx_* functions to si_cp_*
...
and write_event_eop -> release_mem
2018-10-16 15:28:22 -04:00
Marek Olšák
6e1cf6532d
radeonsi: make si_gfx_write_event_eop more configurable
2018-10-16 15:28:22 -04:00
Marek Olšák
203ef19f48
radeonsi: split si_copy_buffer
...
compute and SDMA will be added into it.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-09-10 15:19:56 -04:00
Marek Olšák
1119fe5c25
radeonsi: merge SI and CI dma_clear_buffer and remove the callback
...
also use assertions for the requirements that offset and size are a multiple
of 4.
Tested-by: Dieter Nützel <Dieter@nuetzel-hh.de>
2018-09-10 15:19:56 -04:00
Marek Olšák
93b8b987d0
radeonsi: add a thorough clear/copy_buffer benchmark
2018-08-29 15:31:42 -04:00