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ac: add has_rbplus to ac_gpu_info 

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Samuel Pitoiset 2019-08-02 12:21:04 +02:00
parent 44a46c09de
commit 63c0b89b8f
8 changed files with 8 additions and 9 deletions
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3
src/amd/common/ac_gpu_info.c
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@ -454,6 +454,9 @@ bool ac_query_gpu_info(int fd, void *dev_p,
info->family == CHIP_RENOIR ||
info->chip_class >= GFX10;
info->has_rbplus = info->family == CHIP_STONEY ||
info->chip_class >= GFX9;
/* Get the number of good compute units. */
info->num_good_compute_units = 0;
for (i = 0; i < info->max_se; i++)

1
src/amd/common/ac_gpu_info.h
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@ -61,6 +61,7 @@ struct radeon_info {
bool has_clear_state;
bool has_distributed_tess;
bool has_dcc_constant_encode;
bool has_rbplus; /* if RB+ registers exist */
/* There are 2 display DCC codepaths, because display expects unaligned DCC. */
/* Disable RB and pipe alignment to skip the retile blit. (1 RB chips only) */

1
src/amd/vulkan/radv_device.c
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@ -356,7 +356,6 @@ radv_physical_device_init(struct radv_physical_device *device,
if (device->rad_info.family == CHIP_STONEY ||
device->rad_info.chip_class >= GFX9) {
device->has_rbplus = true;
device->rbplus_allowed = device->rad_info.family == CHIP_STONEY ||
device->rad_info.family == CHIP_VEGA12 ||
device->rad_info.family == CHIP_RAVEN ||

6
src/amd/vulkan/radv_pipeline.c
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@ -865,7 +865,7 @@ radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
}
if (pipeline->device->physical_device->has_rbplus) {
if (pipeline->device->physical_device->rad_info.has_rbplus) {
/* Disable RB+ blend optimizations for dual source blending. */
if (blend.mrt0_is_dual_src) {
for (i = 0; i < 8; i++) {
@ -3329,7 +3329,7 @@ radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
if (pipeline->device->physical_device->has_rbplus) {
if (pipeline->device->physical_device->rad_info.has_rbplus) {
radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
@ -4054,7 +4054,7 @@ radv_compute_db_shader_control(const struct radv_device *device,
else
z_order = V_02880C_LATE_Z;
bool disable_rbplus = device->physical_device->has_rbplus &&
bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
!device->physical_device->rbplus_allowed;
/* It shouldn't be needed to export gl_SampleMask when MSAA is disabled

1
src/amd/vulkan/radv_private.h
View File

@ -280,7 +280,6 @@ struct radv_physical_device {
int master_fd;
struct wsi_device wsi_device;
bool has_rbplus; /* if RB+ register exist */
bool rbplus_allowed; /* if RB+ is allowed */
bool cpdma_prefetch_writes_memory;
bool has_scissor_bug;

2
src/gallium/drivers/radeonsi/si_pipe.c
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@ -1181,8 +1181,6 @@ radeonsi_screen_create_impl(struct radeon_winsys *ws,
*/
if (sscreen->info.family == CHIP_STONEY ||
sscreen->info.chip_class >= GFX9) {
sscreen->has_rbplus = true;
sscreen->rbplus_allowed =
!(sscreen->debug_flags & DBG(NO_RB_PLUS)) &&
(sscreen->info.family == CHIP_STONEY ||

1
src/gallium/drivers/radeonsi/si_pipe.h
View File

@ -512,7 +512,6 @@ struct si_screen {
/* Whether shaders are monolithic (1-part) or separate (3-part). */
bool use_monolithic_shaders;
bool record_llvm_ir;
bool has_rbplus; /* if RB+ registers exist */
bool rbplus_allowed; /* if RB+ is allowed */
bool dcc_msaa_allowed;
bool cpdma_prefetch_writes_memory;

2
src/gallium/drivers/radeonsi/si_state.c
View File

@ -1482,7 +1482,7 @@ static void si_emit_db_render_state(struct si_context *sctx)
if (!rs->multisample_enable)
db_shader_control &= C_02880C_MASK_EXPORT_ENABLE;
if (sctx->screen->has_rbplus &&
if (sctx->screen->info.has_rbplus &&
!sctx->screen->rbplus_allowed)
db_shader_control |= S_02880C_DUAL_QUAD_DISABLE(1);