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radeonsi: add si_debug_options for convenient adding/removing of options 

Move the definition of radeonsi_clear_db_cache_before_clear there,
as well as radeonsi_enable_nir.

This removes the AMD_DEBUG=nir option.

We currently still have two places for options: the driconf machinery
and AMD_DEBUG/R600_DEBUG. If we are to have a single place for options,
then the driconf machinery should be preferred since it's more flexible.

The only downside of the driconf machinery was that adding new options
was quite inconvenient. With this change, a simple boolean option can
be added with a single line of code, same as for AMD_DEBUG.

One technical limitation of this particular implementation is that while
almost all driconf features are available, the translation machinery doesn't
pick up the description strings for options added in si_debvug_options. In
practice, translations haven't been provided anyway, and this is intended
for developer options, so I'm not too worried. It could always be added
later if anybody really cares.

v2:
- use bool instead of uint8_t for options
- si_debug_options.inc -> si_debug_options.h

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Nicolai Hähnle 2019-03-15 14:56:36 +01:00
parent 5078d66a86
commit 8bef4df196
8 changed files with 89 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

12
src/gallium/drivers/radeonsi/driinfo_radeonsi.h
View File

@ -11,6 +11,14 @@ DRI_CONF_SECTION_PERFORMANCE
DRI_CONF_SECTION_END
DRI_CONF_SECTION_DEBUG
DRI_CONF_RADEONSI_CLEAR_DB_CACHE_BEFORE_CLEAR("false")
DRI_CONF_RADEONSI_ENABLE_NIR("false")
//= BEGIN VERBATIM
#define OPT_BOOL(name, dflt, description) \
DRI_CONF_OPT_BEGIN_B(radeonsi_##name, #dflt) \
DRI_CONF_DESC(en, description) \
DRI_CONF_OPT_END
#include "radeonsi/si_debug_options.h"
//= END VERBATIM
DRI_CONF_SECTION_END

2
src/gallium/drivers/radeonsi/si_clear.c
View File

@ -638,7 +638,7 @@ static void si_clear(struct pipe_context *ctx, unsigned buffers,
* This hack decreases back-to-back ClearDepth performance.
*/
if ((sctx->db_depth_clear || sctx->db_stencil_clear) &&
sctx->screen->clear_db_cache_before_clear)
sctx->screen->options.clear_db_cache_before_clear)
sctx->flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
}

4
src/gallium/drivers/radeonsi/si_debug_options.h Normal file
View File

@ -0,0 +1,4 @@
OPT_BOOL(clear_db_cache_before_clear, false, "Clear DB cache before fast depth clear")
OPT_BOOL(enable_nir, false, "Enable NIR")
#undef OPT_BOOL

6
src/gallium/drivers/radeonsi/si_get.c
View File

@ -204,7 +204,7 @@ static int si_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
RADEON_SPARSE_PAGE_SIZE : 0;
case PIPE_CAP_PACKED_UNIFORMS:
if (sscreen->debug_flags & DBG(NIR))
if (sscreen->options.enable_nir)
return 1;
return 0;
@ -419,11 +419,11 @@ static int si_get_shader_param(struct pipe_screen* pscreen,
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
return SI_NUM_IMAGES;
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
if (sscreen->debug_flags & DBG(NIR))
if (sscreen->options.enable_nir)
return 0;
return 32;
case PIPE_SHADER_CAP_PREFERRED_IR:
if (sscreen->debug_flags & DBG(NIR))
if (sscreen->options.enable_nir)
return PIPE_SHADER_IR_NIR;
return PIPE_SHADER_IR_TGSI;
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:

22
src/gallium/drivers/radeonsi/si_pipe.c
View File

@ -62,7 +62,6 @@ static const struct debug_named_value debug_options[] = {
/* Shader compiler options (with no effect on the shader cache): */
{ "checkir", DBG(CHECK_IR), "Enable additional sanity checks on shader IR" },
{ "nir", DBG(NIR), "Enable experimental NIR shaders" },
{ "mono", DBG(MONOLITHIC_SHADERS), "Use old-style monolithic shaders compiled on demand" },
{ "nooptvariant", DBG(NO_OPT_VARIANT), "Disable compiling optimized shader variants." },
@ -839,8 +838,7 @@ static void si_disk_cache_create(struct si_screen *sscreen)
#define ALL_FLAGS (DBG(FS_CORRECT_DERIVS_AFTER_KILL) | \
DBG(SI_SCHED) | \
DBG(GISEL) | \
DBG(UNSAFE_MATH) | \
DBG(NIR))
DBG(UNSAFE_MATH))
uint64_t shader_debug_flags = sscreen->debug_flags &
ALL_FLAGS;
@ -848,7 +846,11 @@ static void si_disk_cache_create(struct si_screen *sscreen)
* how 32-bit addresses are expanded to 64 bits.
*/
STATIC_ASSERT(ALL_FLAGS <= UINT_MAX);
shader_debug_flags |= (uint64_t)sscreen->info.address32_hi << 32;
assert((int16_t)sscreen->info.address32_hi == (int32_t)sscreen->info.address32_hi);
shader_debug_flags |= (uint64_t)(sscreen->info.address32_hi & 0xffff) << 32;
if (sscreen->options.enable_nir)
shader_debug_flags |= 1ull << 48;
sscreen->disk_shader_cache =
disk_cache_create(sscreen->info.name,
@ -932,8 +934,6 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
sscreen->debug_flags |= DBG(FS_CORRECT_DERIVS_AFTER_KILL);
if (driQueryOptionb(config->options, "radeonsi_enable_sisched"))
sscreen->debug_flags |= DBG(SI_SCHED);
if (driQueryOptionb(config->options, "radeonsi_enable_nir"))
sscreen->debug_flags |= DBG(NIR);
if (sscreen->debug_flags & DBG(INFO))
ac_print_gpu_info(&sscreen->info);
@ -1081,8 +1081,14 @@ struct pipe_screen *radeonsi_screen_create(struct radeon_winsys *ws,
driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
sscreen->commutative_blend_add =
driQueryOptionb(config->options, "radeonsi_commutative_blend_add");
sscreen->clear_db_cache_before_clear =
driQueryOptionb(config->options, "radeonsi_clear_db_cache_before_clear");
{
#define OPT_BOOL(name, dflt, description) \
sscreen->options.name = \
driQueryOptionb(config->options, "radeonsi_"#name);
#include "si_debug_options.h"
}
sscreen->has_msaa_sample_loc_bug = (sscreen->info.family >= CHIP_POLARIS10 &&
sscreen->info.family <= CHIP_POLARIS12) ||
sscreen->info.family == CHIP_VEGA10 ||

7
src/gallium/drivers/radeonsi/si_pipe.h
View File

@ -147,7 +147,6 @@ enum {
/* Shader compiler options (with no effect on the shader cache): */
DBG_CHECK_IR,
DBG_NIR,
DBG_MONOLITHIC_SHADERS,
DBG_NO_OPT_VARIANT,
@ -469,7 +468,6 @@ struct si_screen {
bool has_out_of_order_rast;
bool assume_no_z_fights;
bool commutative_blend_add;
bool clear_db_cache_before_clear;
bool has_msaa_sample_loc_bug;
bool has_ls_vgpr_init_bug;
bool has_dcc_constant_encode;
@ -477,6 +475,11 @@ struct si_screen {
bool dfsm_allowed;
bool llvm_has_working_vgpr_indexing;
struct {
#define OPT_BOOL(name, dflt, description) bool name:1;
#include "si_debug_options.h"
} options;
/* Whether shaders are monolithic (1-part) or separate (3-part). */
bool use_monolithic_shaders;
bool record_llvm_ir;

58
src/util/merge_driinfo.py
View File

@ -52,6 +52,14 @@ class Option(object):
self.defaults = defaults
class Verbatim(object):
"""
Represent a chunk of code that is copied into the result file verbatim.
"""
def __init__(self):
self.string = ''
class Section(object):
"""
Represent a config section description as:
@ -75,8 +83,29 @@ def parse_inputs(input_filenames):
section = None
linenum = 0
verbatim = None
for line in infile:
linenum += 1
if line.startswith('//= BEGIN VERBATIM'):
if verbatim is not None:
print('{}:{}: nested verbatim'
.format(input_filename, linenum))
success = False
continue
verbatim = Verbatim()
if verbatim is not None:
verbatim.string += line
if line.startswith('//= END VERBATIM'):
if section is None:
sections.append(verbatim)
else:
section.options.append(verbatim)
verbatim = None
continue
line = line.strip()
if not line:
continue
@ -144,12 +173,17 @@ def merge_sections(section_list):
assert section.name == merged_section.name
for orig_option in section.options:
for merged_option in merged_section.options:
if orig_option.name == merged_option.name:
merged_option.defaults = orig_option.defaults
break
if isinstance(orig_option, Option):
for merged_option in merged_section.options:
if not isinstance(merged_option, Option):
continue
if orig_option.name == merged_option.name:
merged_option.defaults = orig_option.defaults
break
else:
merged_section.options.append(Option(orig_option.name, orig_option.defaults))
else:
merged_section.options.append(Option(orig_option.name, orig_option.defaults))
merged_section.options.append(orig_option)
return merged_section
@ -164,6 +198,10 @@ def merge_sections_lists(sections_lists):
for idx,sections in enumerate(sections_lists):
for base_section in sections:
if not isinstance(base_section, Section):
merged_sections.append(base_section)
continue
original_sections = [base_section]
for next_sections in sections_lists[idx+1:]:
for j,section in enumerate(next_sections):
@ -201,15 +239,23 @@ static const char driinfo_xml[] =
DRI_CONF_BEGIN
% for section in sections:
% if isinstance(section, Section):
DRI_CONF_SECTION_${section.name}
% for option in section.options:
% if isinstance(option, Option):
DRI_CONF_${option.name}(${option.defaults})
% else:
${option.string}
% endif
% endfor
DRI_CONF_SECTION_END
% else:
${section.string}
% endif
% endfor
DRI_CONF_END""")
print(driinfo_h_template.render(sections=merged_sections_list))
print(driinfo_h_template.render(sections=merged_sections_list, Section=Section, Option=Option))
return True

9
src/util/xmlpool/t_options.h
View File

@ -343,17 +343,8 @@ DRI_CONF_OPT_BEGIN_B(radeonsi_commutative_blend_add, def) \
DRI_CONF_DESC(en,gettext("Commutative additive blending optimizations (may cause rendering errors)")) \
DRI_CONF_OPT_END
#define DRI_CONF_RADEONSI_CLEAR_DB_CACHE_BEFORE_CLEAR(def) \
DRI_CONF_OPT_BEGIN_B(radeonsi_clear_db_cache_before_clear, def) \
DRI_CONF_DESC(en,"Clear DB cache before fast depth clear") \
DRI_CONF_OPT_END
#define DRI_CONF_RADEONSI_ZERO_ALL_VRAM_ALLOCS(def) \
DRI_CONF_OPT_BEGIN_B(radeonsi_zerovram, def) \
DRI_CONF_DESC(en,"Zero all vram allocations") \
DRI_CONF_OPT_END
#define DRI_CONF_RADEONSI_ENABLE_NIR(def) \
DRI_CONF_OPT_BEGIN_B(radeonsi_enable_nir, def) \
DRI_CONF_DESC(en,gettext("Enable NIR")) \
DRI_CONF_OPT_END