Commit Graph

103318 Commits

Author SHA1 Message Date
Lionel Landwerlin 78d5c1c82a util: u_queue: fix android build error
mesa/src/util/u_queue.c:242:15: error: address of array 'queue->name'
  will always evaluate to 'true' [-Werror,-Wpointer-bool-conversion]

Fixes: b238e33bc9 "kutil/queue: add a process name into a thread name"
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-07-05 15:42:26 +01:00
Benedikt Schemmer 93a5c9bc99 Util: fix msvc build
The MSVC preprocessor doesnt understand #warning

Fixes: 2e1e6511f7 ("util: extract get_process_name from xmlconfig.c")
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2018-07-05 14:24:08 +01:00
Mathieu Bridon f9b6dfd919 python: Specify the JSON separators
On Python 2, the default JSON separators are ', ' for items and ': ' for
dicts.

On Python 3, the default is the same when no indent is specified, but if
one is (and we do specify one) then the default items separator becomes
',' (the dict separator remains unchanged).

This change explicitly specifies the Python 3 default, which helps
ensuring that the output is identical, whether it was generated by
Python 2 or 3.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-07-05 12:52:38 +01:00
Mathieu Bridon fe8a153648 python: Stabilize some script outputs
In Python, dictionaries and sets are unordered, and as a result their
is no guarantee that running this script twice will produce the same
output.

Using ordered dicts and explicitly sorting items makes the build more
reproducible, and will make it possible to verify that we're not
breaking anything when we move the build scripts to Python 3.

Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-07-05 12:52:12 +01:00
Lionel Landwerlin d337713ec4 intel: tools: remove drm-uapi defines
We already embed the headers, no need to redefine defines/structs.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin 87915baa23 intel: intel_dump_gpu: use simulator id in captures
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin aab21cedc6 intel: devinfo: add simulator id
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Scott D Phillips 0f53948c59 intel: tools: dump-gpu: dump 48-bit addresses
For gen8+, write out PPGTT tables in aub files so that full 48-bit
addresses can be serialized.

v2: Fix handling of `end` index in map_ppgtt

v3: Correctly mark GGTT entry as present (Rafael)

Signed-off-by: Scott D Phillips <scott.d.phillips@intel.com>
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin 6e37b949d5 intel: tools: import intel_aubdump
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Acked-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin fa00b9c1c9 intel: tools: update intel_aub.h
Scott added new stuff in IGT.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin 5ffa35b64d intel: batch-decoder: add missing return line
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin 28476c9d81 intel: batch-decoder: don't asks for constant BO until decoding
With PPGTT mappings, our aubinator implementation can be quite slow if
we request a buffer that doesn't exist. Instead of doing a PPGTT walk
for invalid addresses (0 lengths), wait until we're sure we want to
decode the data.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Scott D Phillips c262ec19d0 intel/batch-decoder: handle non-contiguous binding table / surface state
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-07-05 11:57:45 +01:00
Scott D Phillips 3ebee627cb intel/tools/aubinator: aubinate ppgtt aubs
v2: by Lionel
    Fix memfd_create compilation issue
    Fix pml4 address stored on 32 instead of 64bits
    Return no buffer if first ppgtt page is not mapped

v3: Drop additional memfd_create() (Rafael)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin 3228335b55 intel: aubinator: handle GGTT mappings
We use memfd to store physical pages as they get read/written to and
the GGTT entries translating virtual address to physical pages.

Based on a commit by Scott Phillips.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Jason Ekstrand 2602ea89d5 util: rb-tree: A simple, invasive, red-black tree
This is a simple, invasive, liberally licensed red-black tree
implementation. It's an invasive data structure similar to the
Linux kernel linked-list where the intention is that you embed a
rb_node struct the data structure you intend to put into the
tree.

The implementation is mostly based on the one in "Introduction to
Algorithms", third edition, by Cormen, Leiserson, Rivest, and
Stein. There were a few other key design points:

 * It's an invasive data structure similar to the [Linux kernel
   linked list].

 * It uses NULL for leaves instead of a sentinel. This means a few
   algorithms differ a small bit from the ones in "Introduction to
   Algorithms".

 * All search operations are inlined so that the compiler can
   optimize away the function pointer call.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin 144b40db54 intel: aubinator: drop the 1Tb GTT mapping
Now that we're softpinning the address of our BOs in anv & i965, the
addresses selected start at the top of the addressing space. This is a
problem for the current implementation of aubinator which uses only a
40bit mmapped address space.

This change keeps track of all the memory writes from the aub file and
fetch them on request by the batch decoder. As a result we can get rid
of the 1<<40 mmapped address space and only rely on the mmap aub file
\o/

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin 9d08ef6335 intel: aubinator: rework register writes handling
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin 86cb05a6d3 intel: aubinator: remove standard input processing option
On a follow up commit in this series, we stop copying the data from
the mmap'ed file into our big gtt mmap, and start referencing data in
it directly. So reallocating the read buffer and adding more data from
stdin wouldn't work. For that reason, let's stop supporting stdin
process.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Lionel Landwerlin 08d85a8301 intel: aubinator: remove unused variables
These memory offsets are stored in the gen_batch_decode_ctx.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2018-07-05 11:57:45 +01:00
Mathieu Bridon 3153bcc73e gallium/auxiliary: Fix string matching
Commit f69bc797e1 did the following:

-        if format.layout in ('bptc', 'astc'):
+        if format.layout in ('astc'):

The intention was to go from matching either 'bptc' or 'astc' to
matching only 'astc'.

But the new code doesn't respect this intention any more, because in
Python `('astc')` is not a tuple containing a string, it is just the
string. (the parentheses are simply ignored)

That means we now match any substring of 'astc', for example 'a'.

This commit fixes the test to respect the original intention.

Fixes: f69bc797e1 "gallium/auxiliary: Add helper support for
                             bptc format compress/decompress"
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-07-05 11:48:47 +01:00
Samuel Pitoiset 8339ba827b radv: optimize vkCmd{Set,Reset}Event() a little bit
Always emitting a bottom-of-pipe event is quite dumb. Instead,
start to optimize these functions by syncing PFP for the
top-of-pipe and syncing ME for the post-index-fetch event.

This can still be improved by emitting EOS events for
syncing PS and CS stages.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-07-05 11:31:06 +02:00
Samuel Pitoiset f635109140 radv: optimize radv_CmdWaitEvents()
This introduces radv_barrier() (same as the draw/dispatch codepath).
This helper is used for merging the code from CmdWaitEvents() and
CmdPipelineBarrier because it's quite similar.

We do ignore the source stage mask for CmdWaitEvents because
it's irrelevant when event objects are used.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2018-07-05 11:31:03 +02:00
Roland Scheidegger 620626a371 nir/linker: fix msvc build
Empty initializer braces aren't valid c (it's a gnu extension, and
it's valid in c++).
Hopefully fixes appveyor / msvc build...

Fixes 6677e131b8
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-07-05 09:27:05 +02:00
Gert Wollny 806a42fc47 r600: compare structure elements instead of doing a memcmp
Structures might be padded by the compiler and these padding bytes remain
un-initialized which in turn makes memcmp return a difference where from
the logical point of view there is none.

 Fixes valgrind:
     Conditional jump or move depends on uninitialised value(s)
       at 0x4C32CBA: __memcmp_sse4_1 (vg_replace_strmem.c:1099)
       by 0xB8D2537: r600_set_vertex_buffers (r600_state_common.c:573)
       by 0xB71D44A: u_vbuf_set_driver_vertex_buffers (u_vbuf.c:1129)
       by 0xB71F7BB: u_vbuf_draw_vbo (u_vbuf.c:1153)
       by 0xB3B92CB: st_draw_vbo (st_draw.c:235)
       by 0xB36B1AE: vbo_draw_arrays (vbo_exec_array.c:391)
       by 0xB36BB0D: vbo_exec_DrawArrays (vbo_exec_array.c:550)
       by 0x10A989: piglit_display (textureSize.c:157)
       by 0x4F8F174: run_test (piglit_fbo_framework.c:52)
       by 0x4F7BA12: piglit_gl_test_run (piglit-framework-gl.c:229)
       by 0x10A60A: main (textureSize.c:71)
     Uninitialised value was created by a stack allocation
       at 0xB3948FD: st_update_array (st_atom_array.c:388)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-07-05 07:59:07 +02:00
Gert Wollny 9c1ae6a1a1 r600: Add R4G4B4A4 and A1B5G5R5 to supported vertex formats
Below tests would fail with an error message
  "Vertex format (R4G4B4A4|R5G5B5A1) not supported."
Add the formate to the translation routine to enable these formats.

Fixes:
  dEQP-GLES3.functional.texture.specification.teximage2d_pbo.rgba4_2d
  dEQP-GLES3.functional.texture.specification.teximage2d_pbo.rgba4_cube
  dEQP-GLES3.functional.texture.specification.teximage2d_pbo.rgb5_a1_2d
  dEQP-GLES3.functional.texture.specification.teximage2d_pbo.rgb5_a1_cube
  dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgba4_2d
  dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgba4_cube
  dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb5_a1_2d
  dEQP-GLES3.functional.texture.specification.texsubimage2d_pbo.rgb5_a1_cube
  dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgba4_2d_array
  dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgba4_3d
  dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb5_a1_2d_array
  dEQP-GLES3.functional.texture.specification.teximage3d_pbo.rgb5_a1_3d
  dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgba4_2d_array
  dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgba4_3d
  dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb5_a1_2d_array
  dEQP-GLES3.functional.texture.specification.texsubimage3d_pbo.rgb5_a1_3d
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-07-05 07:57:28 +02:00
Gert Wollny 5278436d67 r600: force LOD range to be only one value when mip.min filter is NONE
For a texture that has only one LOD defined, but for which
GL_TEXTURE_MAX_LEVEL is the default (1000) and
GL_TEXTURE_MIN_LOD != GL_TEXTURE_MAX_LOD the reading from the texture does
not properly resolve the LOD level and texture lookup might fail. Hence,
when no mipmap filter is given (indicating that no mip-mapping takes place),
force the LOD range to contain only value.

Fixes:
  dEQP-GLES3.functional.shaders.texture_functions.texture*.(i|u)sampler2d*
  dEQP-GLES3.functional.texture.format.sized.cube.rgb*
  out of VK_GL_CTS/android/cts/master/gles3-master.txt
Signed-off-by: Gert Wollny <gw.fossdev@gmail.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2018-07-05 07:57:28 +02:00
Gert Wollny e7dd1a84a0 mesa/st: draw_vbo: initialize restart_index too
restart_index is later always used in a comparison, so it should be
initialized properly.

Fixes valgrind warning:
 Conditional jump or move depends on uninitialised value(s)
    at 0xB8D682F: r600_draw_vbo (r600_state_common.c:2153)
    by 0xB71F743: u_vbuf_draw_vbo (u_vbuf.c:1156)
    by 0xB3B92DB: st_draw_vbo (st_draw.c:235)
    by 0xB36B1AE: vbo_draw_arrays (vbo_exec_array.c:391)
    by 0xB36BB0D: vbo_exec_DrawArrays (vbo_exec_array.c:550)
    by 0x10A989: piglit_display (textureSize.c:157)
    by 0x4F8F174: run_test (piglit_fbo_framework.c:52)
    by 0x4F7BA12: piglit_gl_test_run (piglit-framework-gl.c:229)
    by 0x10A60A: main (textureSize.c:71)
 Uninitialised value was created by a stack allocation
    at 0xB3B90B0: st_draw_vbo (st_draw.c:143)

Signed-off-by: Gert Wollny <gert.wollny@collabora.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
Reviewed-by: Brian Paul <brianp@vmware.com>
2018-07-05 07:57:16 +02:00
Timothy Arceri 0cb6537dee mesa: enable ARB_direct_state_access in OpenGL 4.5 compat profile
Its unlikely anyone will add proper ARB_direct_state_access compat
support before we branch 18.2. Enabling the extension in 4.5 at
least allows users to make use of MESA_GL_VERSION_OVERRIDE=4.5COMPAT
for games like No Mans Sky.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-07-05 13:15:34 +10:00
Timothy Arceri 39063334d3 util/drirc: turn on force_glsl_extensions_warn for No Mans Sky
The game forgets to enable multiple extensions in its shaders, one
of those extesions is EXT_texture_array. But enabling this config
entry fixes at least one other rendering issue that enabling
EXT_texture_array on its own doesn't fix.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-07-05 13:05:47 +10:00
Marek Olšák 9b4c4fe334 util/queue: remove leftover debug code 2018-07-04 22:19:47 -04:00
Marek Olšák 7fab8a4b37 Shorten u_queue names
There is a 15-character limit for thread names shared by the queue name
and process name. Shorten the thread name to make space for the process
name.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2018-07-04 22:03:35 -04:00
Marek Olšák b238e33bc9 kutil/queue: add a process name into a thread name
v2: simplifications

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com> (v1)
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com> (v1)
2018-07-04 21:54:39 -04:00
Marek Olšák 7149bffe66 gallium/os: use util_get_process_name when possible
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-07-04 21:16:57 -04:00
Marek Olšák 2e1e6511f7 util: extract get_process_name from xmlconfig.c
Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
Reviewed-by: Eric Engestrom <eric.engestrom@intel.com>
2018-07-04 21:16:03 -04:00
Marek Olšák 4695984dbc ac: fold LLVMContext creation into ac_llvm_context_init
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-07-04 15:48:18 -04:00
Marek Olšák f5cb4194c9 radeonsi: reorder code in si_llvm_context_init
Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-07-04 15:48:18 -04:00
Marek Olšák ff330055e9 radeonsi: use ac_compile_module_to_binary to reduce compile times
Compile times of simple shaders are reduced by ~20%.
Compile times of prologs and epilogs are reduced by up to 40%.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-07-04 15:48:18 -04:00
Marek Olšák 0075e5fed8 ac: add reusable helpers for direct LLVM compilation
This is basically LLVMTargetMachineEmitToMemoryBuffer inlined and reworked.

struct ac_compiler_passes (opaque type) contains the main pass manager.

ac_create_llvm_passes -- the result can go to thread local storage
ac_destroy_llvm_passes -- can be called by a destructor in TLS
ac_compile_module_to_binary -- from LLVMModuleRef to ac_shader_binary

The motivation is to do the expensive call addPassesToEmitFile once
per context or thread.

Reviewed-by: Dave Airlie <airlied@redhat.com>
2018-07-04 15:48:18 -04:00
Rhys Perry c2ae9b4052 nvc0: implement multisampled images on Maxwell+
Changes in v2:
- make loadSuInfo32() protected without making the rest protected
- move NVC0_SU_INFO_* into nv50_ir_lowering_nvc0.h instead of duplicating
  NVC0_SU_INFO_MS

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Karol Herbst <kherbst@redhat.com>
2018-07-04 16:04:23 +02:00
Neil Roberts 2d5ddbe960 i965: Fix output register sizes when variable ranges are interleaved
In 6f5abf3146 this code was fixed to calculate the maximum size of
an attribute in a seperate pass and then allocate the registers to
that size. However this wasn’t taking into account ranges that overlap
but don’t have the same starting location. For example:

layout(location = 0, component = 0) out float a[4];
layout(location = 2, component = 1) out float b[4];

Previously, if ‘a’ was processed first then it would allocate a
register of size 4 for location 0 and it wouldn’t allocate another
register for location 2 because it would already be covered by the
range of 0. Then if something tries to write to b[2] it would try to
write past the end of the register allocated for ‘a’ and it would hit
an assert.

This patch changes it to scan for any overlapping ranges that start
within each range to calculate the maximum extent and allocate that
instead.

Fixed Piglit’s arb_enhanced_layouts/execution/component-layout/
vs-fs-array-interleave-range.shader_test

Reviewed-by: Caio Marcelo de Oliveira Filho <caio.oliveira@intel.com>
Fixes: 6f5abf3146 "i965: Fix output register sizes when multiple variables
       share a slot."
2018-07-04 10:57:51 +02:00
Dave Airlie 8c51caab24 r600/sb: cleanup if_conversion iterator to be legal C++
The current code causes:
/usr/include/c++/8/debug/safe_iterator.h:207:
Error: attempt to copy from a singular iterator.

This is due to the iterators getting invalidated, fix the
reverse iterator to use the return value from erase, and
cast it properly.

(used Mathias suggestion)
Cc: <mesa-stable@lists.freedesktop.org>
Reviewed-by: Mathias Fröhlich <mathias.froehlich@web.de>
2018-07-04 07:42:22 +01:00
Marek Olšák 45f9d58668 radeonsi: fix compiler breakage
Broken by d853d3a59b.
2018-07-04 00:13:38 -04:00
Dave Airlie 5b32b246cf ac: make some fns static
Some of the compiler functions are no longer called outside
the util file.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-07-04 10:29:26 +10:00
Dave Airlie 7398913a62 ac/radv: move llvm compiler info to struct and init in one place
This ports radv to the shared code, however due to a bug in LLVM
version prior to 7, radv cannot add target info at this stage,
as it would leak one for every shader compile, however I'd prefer
to keep this llvm damage in the shared code, since it isn't the
driver at fault here. We just add a flag to denote if the driver
can support leaking the target info or not, and the common code
does the right thing depending on the llvm version.

 Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-07-04 10:29:16 +10:00
Dave Airlie d853d3a59b ac/radeonsi: port compiler init/destroy out of radeonsi.
We want to share this code with radv in the future, so port
it out of radeonsi.

Add a return value as radv will want that to know if this
succeeds

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-07-04 10:29:03 +10:00
Dave Airlie 35c82af539 radv/radeonsi: add a check ir tm options
This doesn't do much yet, but it makes it easier to move the code
to a common shared code base.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-07-04 05:32:35 +10:00
Dave Airlie 0eb65b4944 radeonsi: rename si_compiler -> ac_llvm_compiler
As precursor to moving init to common code, just rename the struct
and move it.

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-07-04 05:31:32 +10:00
Dave Airlie 887ba45c93 ac: add target library info helpers
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-07-04 05:31:29 +10:00
Dave Airlie e1387eaf12 radv: create/destroy passmgr at the higher level.
This is prep work for moving this to a per-thread struct

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2018-07-04 05:31:05 +10:00