radv/radeonsi: add a check ir tm options

This doesn't do much yet, but it makes it easier to move the code
to a common shared code base.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
This commit is contained in:
Dave Airlie 2018-07-03 09:44:22 +10:00
parent 0eb65b4944
commit 35c82af539
3 changed files with 7 additions and 3 deletions

View File

@ -59,6 +59,7 @@ enum ac_target_machine_options {
AC_TM_FORCE_ENABLE_XNACK = (1 << 2),
AC_TM_FORCE_DISABLE_XNACK = (1 << 3),
AC_TM_PROMOTE_ALLOCA_TO_SCRATCH = (1 << 4),
AC_TM_CHECK_IR = (1 << 5),
};
enum ac_float_mode {

View File

@ -562,10 +562,12 @@ shader_variant_create(struct radv_device *device,
tm_options |= AC_TM_SUPPORTS_SPILL;
if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
tm_options |= AC_TM_SISCHED;
if (options->check_ir)
tm_options |= AC_TM_CHECK_IR;
radv_init_llvm_once();
tm = ac_create_target_machine(chip_family, tm_options, NULL);
passmgr = ac_create_passmgr(NULL, options->check_ir);
passmgr = ac_create_passmgr(NULL, tm_options & AC_TM_CHECK_IR);
if (gs_copy_shader) {
assert(shader_count == 1);
radv_compile_gs_copy_shader(tm, passmgr, *shaders, &binary,

View File

@ -111,7 +111,8 @@ static void si_init_compiler(struct si_screen *sscreen,
(sscreen->debug_flags & DBG(SI_SCHED) ? AC_TM_SISCHED : 0) |
(sscreen->info.chip_class >= GFX9 ? AC_TM_FORCE_ENABLE_XNACK : 0) |
(sscreen->info.chip_class < GFX9 ? AC_TM_FORCE_DISABLE_XNACK : 0) |
(!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0);
(!sscreen->llvm_has_working_vgpr_indexing ? AC_TM_PROMOTE_ALLOCA_TO_SCRATCH : 0) |
(sscreen->debug_flags & DBG(CHECK_IR) ? AC_TM_CHECK_IR : 0);
const char *triple;
ac_init_llvm_once();
@ -126,7 +127,7 @@ static void si_init_compiler(struct si_screen *sscreen,
return;
compiler->passmgr = ac_create_passmgr(compiler->target_library_info,
(sscreen->debug_flags & DBG(CHECK_IR)));
tm_options & AC_TM_CHECK_IR);
if (!compiler->passmgr)
return;
}