Commit Graph

222 Commits

Author SHA1 Message Date
Dylan Baker 42b89276e6 iris|anv: gfx version 12.5 data cache flush is not a workaround
This was not a workaround, it was simply missing from the documentation.
So remove the workaround language.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17797>
2022-07-28 22:08:46 +00:00
Dylan Baker 180af73101 anv: add gfx version 12.5 flushes to CCS path
This was already added to the MCS path in !17218, so this is just
adding it in the CCS path as well.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17797>
2022-07-28 22:08:46 +00:00
Tapani Pälli a6857ee43e anv: implement Wa_14015264727 for DG2
On DG2 we need to flush data cache before fast clear operation.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17218>
2022-07-22 14:59:06 +00:00
Jason Ekstrand 81603e7dc2 anv: Use the common image<->buffer copy helper
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16873>
2022-06-07 17:57:42 +00:00
Jason Ekstrand 2c2b3e68e1 vulkan,anv: Move the image offset/extent sanitize helpers to common code
Reviewed-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16873>
2022-06-07 17:57:41 +00:00
Lionel Landwerlin 09caa8902c anv: move internal RT shaders to the internal cache
Those shaders are just like the blorp ones.

v2: Use a single internal cache for blorp/RT (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Fixes: 7f1e82306c ("anv: Switch to the new common pipeline cache")
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16741>
2022-05-28 10:14:03 +00:00
Jason Ekstrand 5d0b09be5b anv: Use the base vk_buffer struct
This mostly gets us the vk_buffer_range() helper but may be useful in
the future.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16607>
2022-05-27 18:38:57 -05:00
Jason Ekstrand 2d3b3b757a anv: Clean up pipeline cache helpers a bit
Instead of having two different helpers, delete the pipeline_cache ones.
Also, instead of manually handling the cache == NULL case in every
vkCreateFooPipelines call, handle it inside the helpers.  This means
that BLORP can use them too by passing cache=NULL.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13184>
2022-04-22 19:38:52 +00:00
Jason Ekstrand 7f1e82306c anv: Switch to the new common pipeline cache
This patch is intended to be somewhat minimal.  There's a lot of cleanup
work that can be done but we'll leave that to later patches.

Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13184>
2022-04-22 19:38:52 +00:00
Lionel Landwerlin 08f3950d6b anv: stop using old entrypoint/struct/enum names for 1.3
v2: More replacements

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason.ekstrand@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com> (v1)
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15920>
2022-04-13 21:13:56 +00:00
Jason Ekstrand 3501a3f9ed anv: Convert to 100% dynamic rendering
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14961>
2022-03-16 13:13:36 -05:00
Jason Ekstrand d65dbe8018 anv: Allow MSAA resolve with different numbers of planes
The Vulkan spec for VK_KHR_depth_stencil_resolve allows a format
mismatch between the primary attachment and the resolve attachment
within certain limits.  In particular,

    VUID-VkSubpassDescriptionDepthStencilResolve-pDepthStencilResolveAttachment-03181

    If pDepthStencilResolveAttachment is not NULL and does not have the
    value VK_ATTACHMENT_UNUSED and VkFormat of
    pDepthStencilResolveAttachment has a depth component, then the
    VkFormat of pDepthStencilAttachment must have a depth component with
    the same number of bits and numerical type

    VUID-VkSubpassDescriptionDepthStencilResolve-pDepthStencilResolveAttachment-03182

    If pDepthStencilResolveAttachment is not NULL and does not have the
    value VK_ATTACHMENT_UNUSED, and VkFormat of
    pDepthStencilResolveAttachment has a stencil component, then the
    VkFormat of pDepthStencilAttachment must have a stencil component
    with the same number of bits and numerical type

So you can resolve from a depth/stencil format to a depth-only or
stencil-only format so long as the number of bits matches.
Unfortunately, this has never been tested because the CTS tests which
purport to test this are broken and actually test with a destination
combined depth/stencil format.

Fixes: 5e4f9ea363 ("anv: Implement VK_KHR_depth_stencil_resolve")
Reviewed-by: Ivan Briano <ivan.briano@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15333>
2022-03-11 22:25:42 +00:00
Jason Ekstrand 5a15c3eff7 anv: Drop anv_cmd_buffer::pool
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14917>
2022-02-11 08:06:25 +00:00
Caio Oliveira ef04caea9b anv: Implement Mesh Shading pipeline
The Mesh pipeline is implemented as a variant of the
regular (primitive) Graphics Pipeline.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Marcin Ślusarz <marcin.slusarz@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13662>
2022-02-02 18:17:57 +00:00
Nanley Chery 912acbf963 anv,iris: Flush HDC before color fast clears
Needed for XeHP (see Bspec 47704).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14024>
2022-01-12 01:30:34 +00:00
Nanley Chery f3c629733f anv,iris: PSS Stall Sync around color fast clears
Needed for XeHP (see Bspec 47704).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14024>
2022-01-12 01:30:34 +00:00
Nanley Chery de5f1cdd31 anv,iris: Depth stall around color fast clears
Needed for TGL (see Bspec 47704).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14024>
2022-01-12 01:30:34 +00:00
Nanley Chery 34c8371e2a anv,iris: Flush tile cache after color fast clears
Needed for TGL (see Bspec 47704).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14024>
2022-01-12 01:30:34 +00:00
Nanley Chery 18cd0a5409 anv: Drop code from get_blorp_surf_for_anv_buffer
The code to handle ASTC surfaces hasn't been needed since commit
dd92179a72 ("anv: Canonicalize buffer formats for image/buffer copies").

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13881>
2021-11-30 13:36:35 +00:00
Nanley Chery 355f318843 anv: Allow transfer-only linear ASTC images
Some apps depend on this to run.

Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/2397

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13881>
2021-11-30 13:36:35 +00:00
Caio Oliveira 8fc6a11f0e intel/blorp: Add option to emit packets that disable Mesh
If a driver doesn't support Mesh, don't emit anything.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/13660>
2021-11-04 14:41:06 -07:00
Nanley Chery 10be870c72 anv: Tile cache flush for depth before fast clear
Instead of doing a tile cache flush after slow clears, resolves, and
ambiguates, do it before fast clears of HIZ_CCS_WT surfaces. This agrees
with the Bspec.

Reviewed-by: Felix DeGrood <felix.j.degrood@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11539>
2021-10-12 18:05:46 +00:00
Jordan Justen 6ce3bb1354 anv/blorp: Force compute blorp on compute-only queues
Reworks:
 * Set BLORP_BATCH_USE_COMPUTE in anv_blorp_batch_init (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
2021-09-30 17:41:33 +00:00
Jordan Justen 136672154c anv/blorp: Add anv_blorp_batch_init, anv_blorp_batch_finish
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
2021-09-30 17:41:33 +00:00
Jordan Justen 2123d59693 intel/blorp: Convert blorp_clear color_write_disable to a bitmask
Reworks:
 * Various cleanups adding BITFIELD_* (s-b Jason)
 * Add /* color_write_disable */ comment (s-b Jason)

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11564>
2021-09-30 17:41:33 +00:00
Jason Ekstrand 83b4d4f17d anv,vulkan: Move VkImageSubresource* helpers from ANV
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>
2021-08-17 21:29:35 +00:00
Jason Ekstrand 25d4cffabf anv: Make anv_image derive from vk_image
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12023>
2021-08-17 21:29:34 +00:00
Jason Ekstrand 56fe30cbfc anv: Make anv_image_aspect_to_plane take an anv_image*
It's called anv_image_* so it really should take an anv_image.  For the
couple of cases where we really want to pass in a set of aspects, we
leave an anv_aspect_to_plane() helper.  anv_image_aspect_to_plane() is
then just a wrapper around it which grabs the aspects from the image.

While we're in the area, sprinkle some const around.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Jason Ekstrand 4518ae8284 anv: Rename anv_get_format_plane to anv_get_format_aspect
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Jason Ekstrand 5dd55b0881 anv/blorp: Use the isl_surf for computing level_width/height in anv_image_ccs_op
Don't manually monkey around with the denominator scales.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Jason Ekstrand 9a267be039 anv/blorp: Drop some can_ycbcr checks
Vulkan allows us to, in theory, support ycbcr on single-plane formats if
the client really wants it.  Also, these functions should work on a
multi-plane color image as long as the client specifies the right
aspect.  This gets rid of our usage of can_ycbcr outside of anv_image.c.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12141>
2021-08-09 16:07:23 +00:00
Felix DeGrood a49b145e8d anv: Replace DC Flush with HDC Pipeline Flush
HDC Pipeline Flush is the correct method for flushing HDC
pipeline on Gfx12+ HW. Continue using DC Flush for earlier HW.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
2021-06-15 12:57:42 +00:00
Felix DeGrood 6f26a51f47 anv: remove unnecessary Tile Cache flushes
On Gfx12+, flushing tile cache ensures color/depth values are
globally visible, but that's expensive.  Most operations only
need values to be GT-visible which can be achieved with depth
or rt flush.  Remove a bunch of unnecessary Tile Cache flushes.
Fast clears and slow depth clears still require Tile Cache flush.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
2021-06-15 12:57:42 +00:00
Felix DeGrood fc5cb54008 anv: Add debug messages for DEBUG_PIPE_CONTROL
Enable with INTEL_DEBUG=pc.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9834>
2021-06-15 12:57:42 +00:00
Sagar Ghuge be2d9c113b anv: Avoid corrupting indirect depth clear values
We don't need to initialize the BO since blorp updates the clear color
BO content with fast clear value i.e ANV_HZ_FC_VAL for depth surface.

With this approach, we can get rid of possibility of corruption since we
are no longer sharing the same clear BO for depth formats.

Closes: #3614

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9941>
2021-04-14 21:00:41 +00:00
Sagar Ghuge ca01d68fb3 anv: Set correct fast clear value for depth during blorp operation
Previously, on the platforms which support the indirect clear color
values, we were just setting the clear color address and not enforcing
any clear color values but some of the blorp operations were using the
wrong fast clear value.

With this patch, we make sure to set the correct fast clear color value
during blorp operations.

Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9941>
2021-04-14 21:00:41 +00:00
Anuj Phogat b75f095bc7 intel: Rename genx keyword to gfxx in source files
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "gen[[:digit:]]+" -rIl $SEARCH_PATH | xargs sed -ie "s/gen\([[:digit:]]\+\)/gfx\1/g"

Exclude pack.h and xml changes in this patch:
grep -E "gfx[[:digit:]]+_pack\.h" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+_pack\.h\)/gen\1/g"
grep -E "gfx[[:digit:]]+\.xml" -rIl $SEARCH_PATH | xargs sed -ie "s/gfx\([[:digit:]]\+\.xml\)/gen\1/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Anuj Phogat abe9a71a09 intel: Rename gen field in gen_device_info struct to ver
Commands used to do the changes:
export SEARCH_PATH="src/intel src/gallium/drivers/iris src/mesa/drivers/dri/i965"
grep -E "info\)*(.|->)gen" -rIl $SEARCH_PATH | xargs sed -ie "s/info\()*\)\(\.\|->\)gen/info\1\2ver/g"

Signed-off-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9936>
2021-04-02 18:33:07 +00:00
Chad Versace d978383966 anv/image: Make memory layout more explicit
Future patches for VK_EXT_image_drm_format_modifier will, in some cases,
place the aux surface and fast clear state into a driver-private bo.
This increases the complexity of image memory layout to such a degree
that, to maintain sanity, we must improve how we track the layout.

Define new types:
  - anv_image_memory_range
  - anv_image_memory_binding
  - anv_image_binding

Delete many fields in anv_image (and its children), and replace them
with the new types.

This patch does not change how anv_image tracks (or, rather, does not
track) the memory of gen12 implicit ccs. We should probably do that, but
that's left as a future exercise.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>
2021-03-09 18:42:20 +00:00
Chad Versace bb7d627865 anv/image: Add anv_image_address()
It calculates the address to a surface or to metadata in the image.

Refactor only. No intended change in behavior.

This patch prepares for, and reduces much noise in, the upcoming patch
that rewrites image memory tracking.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>
2021-03-09 18:42:20 +00:00
Chad Versace ffc08351e1 anv: Add anv_surface_is_valid()
Current code checks for surface validity with `surface.isl.size_B > 0`.
Replace the checks with anv_surface_is_valid().

This prepares for adding new members to anv_surface that may
be accidentally used as a validity-indicator.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>
2021-03-09 18:42:20 +00:00
Chad Versace 5065faca00 anv/image: Rename anv_image_plane::surface -> primary_surface
This disambiguates code that accesses `image->planes[*].surface`.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8097>
2021-03-09 18:42:20 +00:00
Jordan Justen 18bc7d9d3f intel: Use devinfo genx10 field
Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9329>
2021-03-01 22:00:08 -08:00
Mike Blumenkrantz 025b57524f anv: for_each_bit -> foreach_bit
Reviewed-by: Rob Clark <robclark@freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9191>
2021-02-24 17:11:44 +00:00
Lionel Landwerlin 207ee2b6a9 isl: add external parameter to isl_mocs()
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9127>
2021-02-18 11:20:59 +02:00
Jason Ekstrand 06f877f6e6 vulkan,anv: Move VK_KHR_copy_commands2 wrappers to common code
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8676>
2021-02-01 18:54:24 +00:00
Jordan Justen 3b953f0f7a intel/anv: Build gen 12.5
Reworks:
 * Jason: call gen125_init_device_state

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7757>
2020-12-01 19:06:22 +00:00
Jason Ekstrand 802fabdaa4 Revert "anv/image: Define anv_image_get_aux_addr (v3)"
This reverts commit 87dc3106b0.

Fixes: 87dc3106b0 "anv/image: Define anv_image_get_aux_addr (v3)"
Closes: https://gitlab.freedesktop.org/mesa/mesa/-/issues/3826
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7670>
2020-11-17 23:27:42 -06:00
Chad Versace 87dc3106b0 anv/image: Define anv_image_get_aux_addr (v3)
Simple refactor. No intended change in behavior.

Replace each derivation of aux address with anv_image_get_aux_addr().

The function will soon do more in support of
VK_EXT_image_drm_format_modifier, where the image bo and aux bo may be
disjoint.

v2:
  - Replace param 'aspect' with 'plane'.
v3:
  - Workaround for stencil ccs. If no aux surface, then return
    ANV_NULL_ADDRESS.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v2)
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> (v3)
2020-11-17 10:36:45 -08:00
Sagar Ghuge d34ab5071a anv: Get aux usage from plane while clearing stencil buffer
Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com>
Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/2942>
2020-10-22 21:42:36 +00:00