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intel: Use devinfo genx10 field 

Signed-off-by: Jordan Justen <jordan.l.justen@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9329>
This commit is contained in:
Jordan Justen 2021-02-27 15:38:53 -08:00
parent d846901d9d
commit 18bc7d9d3f
24 changed files with 125 additions and 156 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

19
src/gallium/drivers/iris/iris_context.c
View File

@ -257,21 +257,20 @@ iris_destroy_context(struct pipe_context *ctx)
}
#define genX_call(devinfo, func, ...) \
switch ((devinfo)->gen) { \
case 12: \
if (gen_device_info_is_12hp(devinfo)) { \
gen125_##func(__VA_ARGS__); \
} else { \
gen12_##func(__VA_ARGS__); \
} \
switch ((devinfo)->genx10) { \
case 125: \
gen125_##func(__VA_ARGS__); \
break; \
case 11: \
case 120: \
gen12_##func(__VA_ARGS__); \
break; \
case 110: \
gen11_##func(__VA_ARGS__); \
break; \
case 9: \
case 90: \
gen9_##func(__VA_ARGS__); \
break; \
case 8: \
case 80: \
gen8_##func(__VA_ARGS__); \
break; \
default: \

19
src/gallium/drivers/iris/iris_screen.c
View File

@ -59,21 +59,20 @@
#include "iris_monitor.h"
#define genX_call(devinfo, func, ...) \
switch ((devinfo)->gen) { \
case 12: \
if (gen_device_info_is_12hp(devinfo)) { \
gen125_##func(__VA_ARGS__); \
} else { \
gen12_##func(__VA_ARGS__); \
} \
switch ((devinfo)->genx10) { \
case 125: \
gen125_##func(__VA_ARGS__); \
break; \
case 11: \
case 120: \
gen12_##func(__VA_ARGS__); \
break; \
case 110: \
gen11_##func(__VA_ARGS__); \
break; \
case 9: \
case 90: \
gen9_##func(__VA_ARGS__); \
break; \
case 8: \
case 80: \
gen8_##func(__VA_ARGS__); \
break; \
default: \

5
src/intel/compiler/brw_fs.cpp
View File

@ -1621,8 +1621,7 @@ fs_visitor::assign_curb_setup()
uint64_t used = 0;
if (stage == MESA_SHADER_COMPUTE &&
(devinfo->gen > 12 || gen_device_info_is_12hp(devinfo))) {
if (stage == MESA_SHADER_COMPUTE && devinfo->genx10 >= 125) {
fs_builder ubld = bld.exec_all().group(8, 0).at(
cfg->first_block(), cfg->first_block()->start());
@ -2269,7 +2268,7 @@ get_subgroup_id_param_index(const gen_device_info *devinfo,
if (prog_data->nr_params == 0)
return -1;
if (devinfo->gen > 12 || gen_device_info_is_12hp(devinfo))
if (devinfo->genx10 >= 125)
return -1;
/* The local thread id is always the last parameter in the list */

4
src/intel/compiler/brw_fs_nir.cpp
View File

@ -108,7 +108,7 @@ fs_visitor::nir_setup_uniforms()
uniforms = nir->num_uniforms / 4;
if ((stage == MESA_SHADER_COMPUTE || stage == MESA_SHADER_KERNEL) &&
devinfo->gen <= 12 && !gen_device_info_is_12hp(devinfo)) {
devinfo->genx10 < 125) {
/* Add uniforms for builtins after regular NIR uniforms. */
assert(uniforms == prog_data->nr_params);
@ -3675,7 +3675,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder &bld,
break;
case nir_intrinsic_load_subgroup_id:
if (devinfo->gen > 12 || gen_device_info_is_12hp(devinfo))
if (devinfo->genx10 >= 125)
bld.AND(retype(dest, BRW_REGISTER_TYPE_UD),
retype(brw_vec1_grf(0, 2), BRW_REGISTER_TYPE_UD),
brw_imm_ud(INTEL_MASK(7, 0)));

21
src/intel/compiler/brw_gen_enum.h
View File

@ -47,15 +47,18 @@ enum gen {
static enum gen
gen_from_devinfo(const struct gen_device_info *devinfo)
{
switch (devinfo->gen) {
case 4: return devinfo->is_g4x ? GEN45 : GEN4;
case 5: return GEN5;
case 6: return GEN6;
case 7: return devinfo->is_haswell ? GEN75 : GEN7;
case 8: return GEN8;
case 9: return GEN9;
case 11: return GEN11;
case 12: return gen_device_info_is_12hp(devinfo) ? GEN125 : GEN12;
switch (devinfo->genx10) {
case 40: return GEN4;
case 45: return GEN45;
case 50: return GEN5;
case 60: return GEN6;
case 70: return GEN7;
case 75: return GEN75;
case 80: return GEN8;
case 90: return GEN9;
case 110: return GEN11;
case 120: return GEN12;
case 125: return GEN125;
default:
unreachable("not reached");
}

1
src/intel/compiler/test_eu_compact.cpp
View File

@ -337,6 +337,7 @@ main(UNUSED int argc, UNUSED char **argv)
if (devinfo->gen == 10)
continue;
devinfo->genx10 = devinfo->gen * 10;
fail |= run_tests(devinfo);
}

1
src/intel/compiler/test_fs_cmod_propagation.cpp
View File

@ -77,6 +77,7 @@ void cmod_propagation_test::SetUp()
v = new cmod_propagation_fs_visitor(compiler, ctx, prog_data, shader);
devinfo->gen = 7;
devinfo->genx10 = devinfo->gen * 10;
}
void cmod_propagation_test::TearDown()

1
src/intel/compiler/test_fs_copy_propagation.cpp
View File

@ -67,6 +67,7 @@ void copy_propagation_test::SetUp()
v = new copy_propagation_fs_visitor(compiler, ctx, prog_data, shader);
devinfo->gen = 4;
devinfo->genx10 = devinfo->gen * 10;
}
void copy_propagation_test::TearDown()

1
src/intel/compiler/test_fs_saturate_propagation.cpp
View File

@ -67,6 +67,7 @@ void saturate_propagation_test::SetUp()
v = new saturate_propagation_fs_visitor(compiler, ctx, prog_data, shader);
devinfo->gen = 6;
devinfo->genx10 = devinfo->gen * 10;
}
void saturate_propagation_test::TearDown()

1
src/intel/compiler/test_fs_scoreboard.cpp
View File

@ -55,6 +55,7 @@ void scoreboard_test::SetUp()
v = new fs_visitor(compiler, NULL, ctx, NULL, &prog_data->base, shader, 8, -1);
devinfo->gen = 12;
devinfo->genx10 = devinfo->gen * 10;
}
void scoreboard_test::TearDown()

1
src/intel/compiler/test_vec4_cmod_propagation.cpp
View File

@ -110,6 +110,7 @@ void cmod_propagation_test::SetUp()
v = new cmod_propagation_vec4_visitor(compiler, ctx, shader, prog_data);
devinfo->gen = 4;
devinfo->genx10 = devinfo->gen * 10;
}
void cmod_propagation_test::TearDown()

1
src/intel/compiler/test_vec4_copy_propagation.cpp
View File

@ -102,6 +102,7 @@ void copy_propagation_test::SetUp()
v = new copy_propagation_vec4_visitor(compiler, ctx, shader, prog_data);
devinfo->gen = 4;
devinfo->genx10 = devinfo->gen * 10;
}
void copy_propagation_test::TearDown()

1
src/intel/compiler/test_vec4_dead_code_eliminate.cpp
View File

@ -100,6 +100,7 @@ void dead_code_eliminate_test::SetUp()
v = new dead_code_eliminate_vec4_visitor(compiler, ctx, shader, prog_data);
devinfo->gen = 4;
devinfo->genx10 = devinfo->gen * 10;
}
void dead_code_eliminate_test::TearDown()

1
src/intel/compiler/test_vec4_register_coalesce.cpp
View File

@ -106,6 +106,7 @@ void register_coalesce_test::SetUp()
v = new register_coalesce_vec4_visitor(compiler, ctx, shader, prog_data);
devinfo->gen = 4;
devinfo->genx10 = devinfo->gen * 10;
}
void register_coalesce_test::TearDown()

6
src/intel/dev/gen_device_info.c
View File

@ -1267,6 +1267,9 @@ gen_get_device_info_from_pci_id(int pci_id,
assert(devinfo->num_slices <= ARRAY_SIZE(devinfo->num_subslices));
if (devinfo->genx10 == 0)
devinfo->genx10 = devinfo->gen * 10;
devinfo->chipset_id = pci_id;
return true;
}
@ -1426,9 +1429,6 @@ gen_get_device_info_from_fd(int fd, struct gen_device_info *devinfo)
return false;
}
if (devinfo->genx10 == 0)
devinfo->genx10 = devinfo->gen * 10;
/* remaining initializion queries the kernel for device info */
if (devinfo->no_hw)
return true;

4
src/intel/dev/gen_device_info.h
View File

@ -283,15 +283,11 @@ struct gen_device_info
#define gen_device_info_is_9lp(devinfo) \
(GEN_GEN == 9 && ((devinfo)->is_broxton || (devinfo)->is_geminilake))
#define gen_device_info_is_12hp(devinfo) false
#else
#define gen_device_info_is_9lp(devinfo) \
((devinfo)->is_broxton || (devinfo)->is_geminilake)
#define gen_device_info_is_12hp(devinfo) false
#endif
static inline bool

48
src/intel/genxml/gen_bits_header.py
View File

@ -79,42 +79,18 @@ from operator import itemgetter
static inline uint32_t ATTRIBUTE_PURE
${item.token_name}_${prop}(const struct gen_device_info *devinfo)
{
switch (devinfo->gen) {
case 12:
%if item.get_prop(prop, 12.5) == item.get_prop(prop, 12):
return ${item.get_prop(prop, 12)};
%else:
if (gen_device_info_is_12hp(devinfo)) {
return ${item.get_prop(prop, 12.5)};
} else {
return ${item.get_prop(prop, 12)};
}
%endif
case 11: return ${item.get_prop(prop, 11)};
case 9: return ${item.get_prop(prop, 9)};
case 8: return ${item.get_prop(prop, 8)};
case 7:
%if item.get_prop(prop, 7.5) == item.get_prop(prop, 7):
return ${item.get_prop(prop, 7)};
%else:
if (devinfo->is_haswell) {
return ${item.get_prop(prop, 7.5)};
} else {
return ${item.get_prop(prop, 7)};
}
%endif
case 6: return ${item.get_prop(prop, 6)};
case 5: return ${item.get_prop(prop, 5)};
case 4:
%if item.get_prop(prop, 4.5) == item.get_prop(prop, 4):
return ${item.get_prop(prop, 4)};
%else:
if (devinfo->is_g4x) {
return ${item.get_prop(prop, 4.5)};
} else {
return ${item.get_prop(prop, 4)};
}
%endif
switch (devinfo->genx10) {
case 125: return ${item.get_prop(prop, 12.5)};
case 120: return ${item.get_prop(prop, 12)};
case 110: return ${item.get_prop(prop, 11)};
case 90: return ${item.get_prop(prop, 9)};
case 80: return ${item.get_prop(prop, 8)};
case 75: return ${item.get_prop(prop, 7.5)};
case 70: return ${item.get_prop(prop, 7)};
case 60: return ${item.get_prop(prop, 6)};
case 50: return ${item.get_prop(prop, 5)};
case 45: return ${item.get_prop(prop, 4.5)};
case 40: return ${item.get_prop(prop, 4)};
default:
unreachable("Invalid hardware generation");
}

45
src/intel/isl/isl.c
View File

@ -2191,43 +2191,38 @@ isl_surf_get_ccs_surf(const struct isl_device *dev,
}
#define isl_genX_call(dev, func, ...) \
switch (ISL_DEV_GEN(dev)) { \
case 4: \
/* G45 surface state is the same as gen5 */ \
if (ISL_DEV_IS_G4X(dev)) { \
isl_gen5_##func(__VA_ARGS__); \
} else { \
isl_gen4_##func(__VA_ARGS__); \
} \
switch (ISL_DEV_GENX10(dev)) { \
case 40: \
isl_gen4_##func(__VA_ARGS__); \
break; \
case 5: \
case 45: \
/* G45 surface state is the same as gen5 */ \
case 50: \
isl_gen5_##func(__VA_ARGS__); \
break; \
case 6: \
case 60: \
isl_gen6_##func(__VA_ARGS__); \
break; \
case 7: \
if (ISL_DEV_IS_HASWELL(dev)) { \
isl_gen75_##func(__VA_ARGS__); \
} else { \
isl_gen7_##func(__VA_ARGS__); \
} \
case 70: \
isl_gen7_##func(__VA_ARGS__); \
break; \
case 8: \
case 75: \
isl_gen75_##func(__VA_ARGS__); \
break; \
case 80: \
isl_gen8_##func(__VA_ARGS__); \
break; \
case 9: \
case 90: \
isl_gen9_##func(__VA_ARGS__); \
break; \
case 11: \
case 110: \
isl_gen11_##func(__VA_ARGS__); \
break; \
case 12: \
if (ISL_DEV_IS_GEN12HP(dev)) { \
isl_gen125_##func(__VA_ARGS__); \
} else { \
isl_gen12_##func(__VA_ARGS__); \
} \
case 120: \
isl_gen12_##func(__VA_ARGS__); \
break; \
case 125: \
isl_gen125_##func(__VA_ARGS__); \
break; \
default: \
assert(!"Unknown hardware generation"); \

8
src/intel/isl/isl.h
View File

@ -61,10 +61,12 @@ struct brw_image_param;
* `gcc -DISL_DEV_GEN(dev)=9 ...`.
*/
#define ISL_DEV_GEN(__dev) ((__dev)->info->gen)
#define ISL_DEV_GENX10(__dev) ((__dev)->info->genx10)
#define ISL_DEV_GEN_SANITIZE(__dev)
#else
#define ISL_DEV_GEN_SANITIZE(__dev) \
(assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen))
(assert(ISL_DEV_GEN(__dev) == (__dev)->info->gen) && \
ISL_DEV_GENX10(__dev) == (__dev)->info->genx10))
#endif
#ifndef ISL_DEV_IS_G4X
@ -85,10 +87,6 @@ struct brw_image_param;
#define ISL_DEV_IS_BAYTRAIL(__dev) ((__dev)->info->is_baytrail)
#endif
#ifndef ISL_DEV_IS_GEN12HP
#define ISL_DEV_IS_GEN12HP(__dev) (gen_device_info_is_12hp((__dev)->info))
#endif
#ifndef ISL_DEV_USE_SEPARATE_STENCIL
/**
* You can define this as a compile-time constant in the CFLAGS. For example,

30
src/intel/vulkan/anv_blorp.c
View File

@ -96,29 +96,27 @@ anv_device_init_blorp(struct anv_device *device)
device->blorp.compiler = device->physical->compiler;
device->blorp.lookup_shader = lookup_blorp_shader;
device->blorp.upload_shader = upload_blorp_shader;
switch (device->info.gen) {
case 7:
if (device->info.is_haswell) {
device->blorp.exec = gen75_blorp_exec;
} else {
device->blorp.exec = gen7_blorp_exec;
}
switch (device->info.genx10) {
case 70:
device->blorp.exec = gen7_blorp_exec;
break;
case 8:
case 75:
device->blorp.exec = gen75_blorp_exec;
break;
case 80:
device->blorp.exec = gen8_blorp_exec;
break;
case 9:
case 90:
device->blorp.exec = gen9_blorp_exec;
break;
case 11:
case 110:
device->blorp.exec = gen11_blorp_exec;
break;
case 12:
if (gen_device_info_is_12hp(&device->info)) {
device->blorp.exec = gen125_blorp_exec;
} else {
device->blorp.exec = gen12_blorp_exec;
}
case 120:
device->blorp.exec = gen12_blorp_exec;
break;
case 125:
device->blorp.exec = gen125_blorp_exec;
break;
default:
unreachable("Unknown hardware generation");

2
src/intel/vulkan/anv_cmd_buffer.c
View File

@ -1068,7 +1068,7 @@ anv_cmd_buffer_cs_push_constants(struct anv_cmd_buffer *cmd_buffer)
const unsigned aligned_total_push_constants_size =
ALIGN(total_push_constants_size, push_constant_alignment);
struct anv_state state;
if (devinfo->gen > 12 || gen_device_info_is_12hp(devinfo)) {
if (devinfo->genx10 >= 125) {
state = anv_state_stream_alloc(&cmd_buffer->general_state_stream,
aligned_total_push_constants_size,
push_constant_alignment);

28
src/intel/vulkan/anv_measure.c
View File

@ -38,27 +38,27 @@ struct anv_measure_batch {
void
anv_measure_device_init(struct anv_physical_device *device)
{
switch (device->info.gen) {
case 12:
if (gen_device_info_is_12hp(&device->info))
device->cmd_emit_timestamp = &gen125_cmd_emit_timestamp;
else
device->cmd_emit_timestamp = &gen12_cmd_emit_timestamp;
switch (device->info.genx10) {
case 125:
device->cmd_emit_timestamp = &gen125_cmd_emit_timestamp;
break;
case 11:
case 120:
device->cmd_emit_timestamp = &gen12_cmd_emit_timestamp;
break;
case 110:
device->cmd_emit_timestamp = &gen11_cmd_emit_timestamp;
break;
case 9:
case 90:
device->cmd_emit_timestamp = &gen9_cmd_emit_timestamp;
break;
case 8:
case 80:
device->cmd_emit_timestamp = &gen8_cmd_emit_timestamp;
break;
case 7:
if (device->info.is_haswell)
device->cmd_emit_timestamp = &gen75_cmd_emit_timestamp;
else
device->cmd_emit_timestamp = &gen7_cmd_emit_timestamp;
case 75:
device->cmd_emit_timestamp = &gen75_cmd_emit_timestamp;
break;
case 70:
device->cmd_emit_timestamp = &gen7_cmd_emit_timestamp;
break;
default:
assert(false);

3
src/intel/vulkan/anv_nir_compute_push_layout.c
View File

@ -92,8 +92,7 @@ anv_nir_compute_push_layout(const struct anv_physical_device *pdevice,
push_end = MAX2(push_end, push_reg_mask_end);
}
if (nir->info.stage == MESA_SHADER_COMPUTE &&
(devinfo->gen <= 12 && !gen_device_info_is_12hp(devinfo))) {
if (nir->info.stage == MESA_SHADER_COMPUTE && devinfo->genx10 < 125) {
/* For compute shaders, we always have to have the subgroup ID. The
* back-end compiler will "helpfully" add it for us in the last push
* constant slot. Yes, there is an off-by-one error here but that's

30
src/intel/vulkan/anv_private.h
View File

@ -4536,29 +4536,27 @@ VK_DEFINE_NONDISP_HANDLE_CASTS(anv_performance_configuration_intel, base,
#define anv_genX(devinfo, thing) ({ \
__typeof(&gen9_##thing) genX_thing; \
switch ((devinfo)->gen) { \
case 7: \
if ((devinfo)->is_haswell) { \
genX_thing = &gen75_##thing; \
} else { \
genX_thing = &gen7_##thing; \
} \
switch ((devinfo)->genx10) { \
case 70: \
genX_thing = &gen7_##thing; \
break; \
case 8: \
case 75: \
genX_thing = &gen75_##thing; \
break; \
case 80: \
genX_thing = &gen8_##thing; \
break; \
case 9: \
case 90: \
genX_thing = &gen9_##thing; \
break; \
case 11: \
case 110: \
genX_thing = &gen11_##thing; \
break; \
case 12: \
if (gen_device_info_is_12hp(devinfo)) { \
genX_thing = &gen125_##thing; \
} else { \
genX_thing = &gen12_##thing; \
} \
case 120: \
genX_thing = &gen12_##thing; \
break; \
case 125: \
genX_thing = &gen125_##thing; \
break; \
default: \
assert(!"Unknown hardware generation"); \