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anv,iris: PSS Stall Sync around color fast clears 

Needed for XeHP (see Bspec 47704).

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Rohan Garg <rohan.garg@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14024>
This commit is contained in:
Nanley Chery 2021-10-08 11:16:35 -07:00 committed by Marge Bot
parent 8ec8298ce4
commit f3c629733f
7 changed files with 24 additions and 3 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/gallium/drivers/iris/iris_clear.c
View File

@ -260,7 +260,8 @@ fast_clear_color(struct iris_context *ice,
PIPE_CONTROL_RENDER_TARGET_FLUSH |
PIPE_CONTROL_TILE_CACHE_FLUSH |
(devinfo->verx10 == 120 ?
PIPE_CONTROL_DEPTH_STALL : 0));
PIPE_CONTROL_DEPTH_STALL : 0) |
PIPE_CONTROL_PSS_STALL_SYNC);
iris_batch_sync_region_start(batch);
@ -287,7 +288,8 @@ fast_clear_color(struct iris_context *ice,
PIPE_CONTROL_RENDER_TARGET_FLUSH |
(devinfo->verx10 == 120 ?
PIPE_CONTROL_TILE_CACHE_FLUSH |
PIPE_CONTROL_DEPTH_STALL : 0));
PIPE_CONTROL_DEPTH_STALL : 0) |
PIPE_CONTROL_PSS_STALL_SYNC);
iris_batch_sync_region_end(batch);
iris_resource_set_aux_state(ice, res, level, box->z,

1
src/gallium/drivers/iris/iris_context.h
View File

@ -339,6 +339,7 @@ enum pipe_control_flags
PIPE_CONTROL_DEPTH_CACHE_FLUSH = (1 << 24),
PIPE_CONTROL_TILE_CACHE_FLUSH = (1 << 25),
PIPE_CONTROL_FLUSH_HDC = (1 << 26),
PIPE_CONTROL_PSS_STALL_SYNC = (1 << 27),
};
#define PIPE_CONTROL_CACHE_FLUSH_BITS \

6
src/gallium/drivers/iris/iris_state.c
View File

@ -7925,7 +7925,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
if (INTEL_DEBUG(DEBUG_PIPE_CONTROL)) {
fprintf(stderr,
" PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64"]: %s\n",
" PC [%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%"PRIx64"]: %s\n",
(flags & PIPE_CONTROL_FLUSH_ENABLE) ? "PipeCon " : "",
(flags & PIPE_CONTROL_CS_STALL) ? "CS " : "",
(flags & PIPE_CONTROL_STALL_AT_SCOREBOARD) ? "Scoreboard " : "",
@ -7950,6 +7950,7 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
(flags & PIPE_CONTROL_WRITE_DEPTH_COUNT) ? "WriteZCount " : "",
(flags & PIPE_CONTROL_WRITE_TIMESTAMP) ? "WriteTimestamp " : "",
(flags & PIPE_CONTROL_FLUSH_HDC) ? "HDC " : "",
(flags & PIPE_CONTROL_PSS_STALL_SYNC) ? "PSS " : "",
imm, reason);
}
@ -7957,6 +7958,9 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
iris_batch_sync_region_start(batch);
iris_emit_cmd(batch, GENX(PIPE_CONTROL), pc) {
#if GFX_VERx10 >= 125
pc.PSSStallSyncEnable = flags & PIPE_CONTROL_PSS_STALL_SYNC;
#endif
#if GFX_VER >= 12
pc.TileCacheFlushEnable = flags & PIPE_CONTROL_TILE_CACHE_FLUSH;
#endif

4
src/intel/vulkan/anv_blorp.c
View File

@ -1880,6 +1880,7 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
ANV_PIPE_TILE_CACHE_FLUSH_BIT |
(devinfo->verx10 == 120 ?
ANV_PIPE_DEPTH_STALL_BIT : 0) |
ANV_PIPE_PSS_STALL_SYNC_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"before fast clear mcs");
@ -1904,6 +1905,7 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
(devinfo->verx10 == 120 ?
ANV_PIPE_TILE_CACHE_FLUSH_BIT |
ANV_PIPE_DEPTH_STALL_BIT : 0) |
ANV_PIPE_PSS_STALL_SYNC_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"after fast clear mcs");
@ -1972,6 +1974,7 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
ANV_PIPE_TILE_CACHE_FLUSH_BIT |
(devinfo->verx10 == 120 ?
ANV_PIPE_DEPTH_STALL_BIT : 0) |
ANV_PIPE_PSS_STALL_SYNC_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"before fast clear ccs");
@ -2001,6 +2004,7 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
(devinfo->verx10 == 120 ?
ANV_PIPE_TILE_CACHE_FLUSH_BIT |
ANV_PIPE_DEPTH_STALL_BIT : 0) |
ANV_PIPE_PSS_STALL_SYNC_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"after fast clear ccs");

1
src/intel/vulkan/anv_private.h
View File

@ -2346,6 +2346,7 @@ enum anv_pipe_bits {
* must reinterpret this flush as ANV_PIPE_DATA_CACHE_FLUSH_BIT.
*/
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT = (1 << 14),
ANV_PIPE_PSS_STALL_SYNC_BIT = (1 << 15),
ANV_PIPE_CS_STALL_BIT = (1 << 20),
ANV_PIPE_END_OF_PIPE_SYNC_BIT = (1 << 21),

2
src/intel/vulkan/anv_util.c
View File

@ -81,6 +81,8 @@ anv_dump_pipe_bits(enum anv_pipe_bits bits)
fputs("+ic_inval ", stderr);
if (bits & ANV_PIPE_STALL_AT_SCOREBOARD_BIT)
fputs("+pb_stall ", stderr);
if (bits & ANV_PIPE_PSS_STALL_SYNC_BIT)
fputs("+pss_stall ", stderr);
if (bits & ANV_PIPE_DEPTH_STALL_BIT)
fputs("+depth_stall ", stderr);
if (bits & ANV_PIPE_CS_STALL_BIT)

7
src/intel/vulkan/genX_cmd_buffer.c
View File

@ -56,6 +56,9 @@ convert_pc_to_bits(struct GENX(PIPE_CONTROL) *pc) {
enum anv_pipe_bits bits = 0;
bits |= (pc->DepthCacheFlushEnable) ? ANV_PIPE_DEPTH_CACHE_FLUSH_BIT : 0;
bits |= (pc->DCFlushEnable) ? ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0;
#if GFX_VERx10 >= 125
bits |= (pc->PSSStallSyncEnable) ? ANV_PIPE_PSS_STALL_SYNC_BIT : 0;
#endif
#if GFX_VER >= 12
bits |= (pc->TileCacheFlushEnable) ? ANV_PIPE_TILE_CACHE_FLUSH_BIT : 0;
bits |= (pc->HDCPipelineFlushEnable) ? ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0;
@ -2234,6 +2237,10 @@ genX(cmd_buffer_apply_pipe_flushes)(struct anv_cmd_buffer *cmd_buffer)
pipe.DepthStallEnable = bits & ANV_PIPE_DEPTH_STALL_BIT;
#endif
#if GFX_VERx10 >= 125
pipe.PSSStallSyncEnable = bits & ANV_PIPE_PSS_STALL_SYNC_BIT;
#endif
pipe.CommandStreamerStallEnable = bits & ANV_PIPE_CS_STALL_BIT;
pipe.StallAtPixelScoreboard = bits & ANV_PIPE_STALL_AT_SCOREBOARD_BIT;