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anv: implement Wa_14015264727 for DG2 

On DG2 we need to flush data cache before fast clear operation.

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17218>
This commit is contained in:
Tapani Pälli 2022-07-20 15:29:22 +03:00 committed by Marge Bot
parent da7a7c9bbc
commit a6857ee43e
1 changed files with 7 additions and 0 deletions
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7
src/intel/vulkan/anv_blorp.c
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@ -1852,6 +1852,11 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
* resolve and then use a second PIPE_CONTROL after the resolve to ensure
* that it is completed before any additional drawing occurs.
*/
/* Wa_14015264727, on DG2 we need to flush data cache before fast clear. */
bool data_cache_flush_needed =
intel_device_info_is_dg2(&cmd_buffer->device->info);
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_TILE_CACHE_FLUSH_BIT |
@ -1859,6 +1864,8 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
ANV_PIPE_DEPTH_STALL_BIT : 0) |
(devinfo->verx10 == 125 ?
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0) |
(data_cache_flush_needed ?
ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0) |
ANV_PIPE_PSS_STALL_SYNC_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"before fast clear mcs");