KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

iris|anv: gfx version 12.5 data cache flush is not a workaround 

This was not a workaround, it was simply missing from the documentation.
So remove the workaround language.

Reviewed-by: Nanley Chery <nanley.g.chery@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17797>
This commit is contained in:
Dylan Baker 2022-07-28 13:34:32 -07:00 committed by Marge Bot
parent 180af73101
commit 42b89276e6
2 changed files with 4 additions and 16 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

10
src/gallium/drivers/iris/iris_clear.c
View File

@ -254,11 +254,6 @@ fast_clear_color(struct iris_context *ice,
* and again afterwards to ensure that the resolve is complete before we
* do any more regular drawing.
*/
/* Wa_14015264727, on DG2 we need to flush data cache before fast clear. */
bool data_cache_flush_needed =
intel_device_info_is_dg2(&batch->screen->devinfo);
iris_emit_end_of_pipe_sync(batch,
"fast clear: pre-flush",
PIPE_CONTROL_RENDER_TARGET_FLUSH |
@ -266,9 +261,8 @@ fast_clear_color(struct iris_context *ice,
(devinfo->verx10 == 120 ?
PIPE_CONTROL_DEPTH_STALL : 0) |
(devinfo->verx10 == 125 ?
PIPE_CONTROL_FLUSH_HDC : 0) |
(data_cache_flush_needed ?
PIPE_CONTROL_DATA_CACHE_FLUSH : 0) |
PIPE_CONTROL_FLUSH_HDC |
PIPE_CONTROL_DATA_CACHE_FLUSH : 0) |
PIPE_CONTROL_PSS_STALL_SYNC);
iris_batch_sync_region_start(batch);

10
src/intel/vulkan/anv_blorp.c
View File

@ -1852,20 +1852,14 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
* resolve and then use a second PIPE_CONTROL after the resolve to ensure
* that it is completed before any additional drawing occurs.
*/
/* Wa_14015264727, on DG2 we need to flush data cache before fast clear. */
bool data_cache_flush_needed =
intel_device_info_is_dg2(&cmd_buffer->device->info);
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_TILE_CACHE_FLUSH_BIT |
(devinfo->verx10 == 120 ?
ANV_PIPE_DEPTH_STALL_BIT : 0) |
(devinfo->verx10 == 125 ?
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0) |
(data_cache_flush_needed ?
ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0) |
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT |
ANV_PIPE_DATA_CACHE_FLUSH_BIT : 0) |
ANV_PIPE_PSS_STALL_SYNC_BIT |
ANV_PIPE_END_OF_PIPE_SYNC_BIT,
"before fast clear mcs");