anv,iris: Flush HDC before color fast clears
Needed for XeHP (see Bspec 47704). Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Rohan Garg <rohan.garg@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14024>
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@ -261,6 +261,8 @@ fast_clear_color(struct iris_context *ice,
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PIPE_CONTROL_TILE_CACHE_FLUSH |
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(devinfo->verx10 == 120 ?
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PIPE_CONTROL_DEPTH_STALL : 0) |
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(devinfo->verx10 == 125 ?
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PIPE_CONTROL_FLUSH_HDC : 0) |
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PIPE_CONTROL_PSS_STALL_SYNC);
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iris_batch_sync_region_start(batch);
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@ -1880,6 +1880,8 @@ anv_image_mcs_op(struct anv_cmd_buffer *cmd_buffer,
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ANV_PIPE_TILE_CACHE_FLUSH_BIT |
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(devinfo->verx10 == 120 ?
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ANV_PIPE_DEPTH_STALL_BIT : 0) |
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(devinfo->verx10 == 125 ?
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ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0) |
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ANV_PIPE_PSS_STALL_SYNC_BIT |
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ANV_PIPE_END_OF_PIPE_SYNC_BIT,
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"before fast clear mcs");
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@ -1974,6 +1976,8 @@ anv_image_ccs_op(struct anv_cmd_buffer *cmd_buffer,
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ANV_PIPE_TILE_CACHE_FLUSH_BIT |
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(devinfo->verx10 == 120 ?
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ANV_PIPE_DEPTH_STALL_BIT : 0) |
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(devinfo->verx10 == 125 ?
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ANV_PIPE_HDC_PIPELINE_FLUSH_BIT : 0) |
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ANV_PIPE_PSS_STALL_SYNC_BIT |
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ANV_PIPE_END_OF_PIPE_SYNC_BIT,
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"before fast clear ccs");
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