anv: Avoid corrupting indirect depth clear values
We don't need to initialize the BO since blorp updates the clear color BO content with fast clear value i.e ANV_HZ_FC_VAL for depth surface. With this approach, we can get rid of possibility of corruption since we are no longer sharing the same clear BO for depth formats. Closes: #3614 Signed-off-by: Sagar Ghuge <sagar.ghuge@intel.com> Reviewed-by: Nanley Chery <nanley.g.chery@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9941>
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@ -257,18 +257,9 @@ get_blorp_surf_for_anv_image(const struct anv_device *device,
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anv_image_get_clear_color_addr(device, image, aspect);
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blorp_surf->clear_color_addr = anv_to_blorp_address(clear_color_addr);
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} else if (aspect & VK_IMAGE_ASPECT_DEPTH_BIT) {
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if (device->info.ver >= 10) {
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/* Vulkan always clears to 1.0. On gen < 10, we set that directly
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* in the state packet. For gen >= 10, must provide the clear
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* value in a buffer. We have a single global buffer that stores
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* the 1.0 value.
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*/
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const struct anv_address clear_color_addr = (struct anv_address) {
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.bo = device->hiz_clear_bo,
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};
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blorp_surf->clear_color_addr =
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anv_to_blorp_address(clear_color_addr);
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}
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const struct anv_address clear_color_addr =
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anv_image_get_clear_color_addr(device, image, aspect);
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blorp_surf->clear_color_addr = anv_to_blorp_address(clear_color_addr);
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blorp_surf->clear_color = (union isl_color_value) {
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.f32 = { ANV_HZ_FC_VAL },
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};
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@ -2772,27 +2772,6 @@ vk_priority_to_gen(int priority)
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}
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}
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static VkResult
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anv_device_init_hiz_clear_value_bo(struct anv_device *device)
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{
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VkResult result = anv_device_alloc_bo(device, "hiz-clear-value", 4096,
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ANV_BO_ALLOC_MAPPED,
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0 /* explicit_address */,
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&device->hiz_clear_bo);
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if (result != VK_SUCCESS)
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return result;
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union isl_color_value hiz_clear = { .u32 = { 0, } };
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hiz_clear.f32[0] = ANV_HZ_FC_VAL;
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memcpy(device->hiz_clear_bo->map, hiz_clear.u32, sizeof(hiz_clear.u32));
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if (!device->info.has_llc)
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gen_clflush_range(device->hiz_clear_bo->map, sizeof(hiz_clear.u32));
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return VK_SUCCESS;
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}
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static bool
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get_bo_from_pool(struct intel_batch_decode_bo *ret,
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struct anv_block_pool *pool,
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@ -3255,17 +3234,11 @@ VkResult anv_CreateDevice(
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isl_extent3d(1, 1, 1) /* This shouldn't matter */);
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assert(device->null_surface_state.offset == 0);
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if (device->info.ver >= 10) {
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result = anv_device_init_hiz_clear_value_bo(device);
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if (result != VK_SUCCESS)
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goto fail_trivial_batch_bo;
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}
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anv_scratch_pool_init(device, &device->scratch_pool);
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result = anv_genX(&device->info, init_device_state)(device);
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if (result != VK_SUCCESS)
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goto fail_clear_value_bo;
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goto fail_trivial_batch_bo_and_scratch_pool;
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anv_pipeline_cache_init(&device->default_pipeline_cache, device,
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true /* cache_enabled */, false /* external_sync */);
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@ -3280,11 +3253,8 @@ VkResult anv_CreateDevice(
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return VK_SUCCESS;
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fail_clear_value_bo:
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if (device->info.ver >= 10)
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anv_device_release_bo(device, device->hiz_clear_bo);
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fail_trivial_batch_bo_and_scratch_pool:
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anv_scratch_pool_finish(device, &device->scratch_pool);
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fail_trivial_batch_bo:
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anv_device_release_bo(device, device->trivial_batch_bo);
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fail_workaround_bo:
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anv_device_release_bo(device, device->workaround_bo);
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@ -3362,8 +3332,6 @@ void anv_DestroyDevice(
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anv_device_release_bo(device, device->workaround_bo);
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anv_device_release_bo(device, device->trivial_batch_bo);
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if (device->info.ver >= 10)
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anv_device_release_bo(device, device->hiz_clear_bo);
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if (device->info.has_aux_map) {
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intel_aux_map_finish(device->aux_map_ctx);
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@ -459,7 +459,8 @@ add_aux_state_tracking_buffer(struct anv_device *device,
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{
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assert(image && device);
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assert(image->planes[plane].aux_usage != ISL_AUX_USAGE_NONE &&
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image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
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image->aspects & (VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV |
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VK_IMAGE_ASPECT_DEPTH_BIT));
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const unsigned clear_color_state_size = device->info.ver >= 10 ?
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device->isl_dev.ss.clear_color_state_size :
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@ -578,9 +579,14 @@ add_aux_surface_if_supported(struct anv_device *device,
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image->planes[plane].aux_usage = ISL_AUX_USAGE_HIZ_CCS;
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}
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return add_surface(device, image, &image->planes[plane].aux_surface,
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ANV_IMAGE_MEMORY_BINDING_PLANE_0 + plane,
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ANV_OFFSET_IMPLICIT);
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result = add_surface(device, image, &image->planes[plane].aux_surface,
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ANV_IMAGE_MEMORY_BINDING_PLANE_0 + plane,
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ANV_OFFSET_IMPLICIT);
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if (result != VK_SUCCESS)
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return result;
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if (image->planes[plane].aux_usage == ISL_AUX_USAGE_HIZ_CCS_WT)
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return add_aux_state_tracking_buffer(device, image, plane);
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} else if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT) {
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if (INTEL_DEBUG & DEBUG_NO_RBC)
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@ -903,10 +909,6 @@ check_memory_bindings(const struct anv_device *device,
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}
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/* Check fast clear state */
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assert((plane->fast_clear_memory_range.size > 0) ==
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(plane->aux_usage != ISL_AUX_USAGE_NONE &&
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image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV));
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if (plane->fast_clear_memory_range.size > 0) {
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enum anv_image_memory_binding binding = primary_binding;
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@ -2575,14 +2577,7 @@ anv_image_fill_surface_state(struct anv_device *device,
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struct anv_address clear_address = ANV_NULL_ADDRESS;
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if (device->info.ver >= 10 && isl_aux_usage_has_fast_clears(aux_usage)) {
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if (aspect == VK_IMAGE_ASPECT_DEPTH_BIT) {
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clear_address = (struct anv_address) {
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.bo = device->hiz_clear_bo,
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.offset = 0,
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};
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} else {
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clear_address = anv_image_get_clear_color_addr(device, image, aspect);
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}
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clear_address = anv_image_get_clear_color_addr(device, image, aspect);
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}
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state_inout->clear_address = clear_address;
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@ -1223,7 +1223,6 @@ struct anv_device {
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struct anv_address workaround_address;
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struct anv_bo * trivial_batch_bo;
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struct anv_bo * hiz_clear_bo;
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struct anv_state null_surface_state;
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struct anv_pipeline_cache default_pipeline_cache;
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@ -3844,7 +3843,8 @@ anv_image_get_clear_color_addr(UNUSED const struct anv_device *device,
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const struct anv_image *image,
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VkImageAspectFlagBits aspect)
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{
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assert(image->aspects & VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV);
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assert(image->aspects & (VK_IMAGE_ASPECT_ANY_COLOR_BIT_ANV |
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VK_IMAGE_ASPECT_DEPTH_BIT));
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uint32_t plane = anv_image_aspect_to_plane(image->aspects, aspect);
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const struct anv_image_memory_range *mem_range =
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