Commit Graph

96939 Commits

Author SHA1 Message Date
Bas Nieuwenhuizen 2c5b43c87f ac/nir: Fix nir_texop_lod on GFX for 1D arrays.
Fixes: 1bcb953e16 'radv: handle GFX9 1D textures'
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-23 00:27:44 +02:00
Dave Airlie da9c3cd3ee radv/ac/nir: only emit tess factors to storage if tes reads them
Otherwise we just need to write them to the tf ring.

this seems to improve the tessellation demo on Bonarie
~2190->~2230 fps

Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2017-10-23 07:10:29 +10:00
Bas Nieuwenhuizen 6ce550453f radv: Don't use vgpr indexing for outputs on GFX9.
Due to LLVM bugs. Fixes a bunch of dEQP-VK.glsl.indexing.*
tests.

Fixes: e38685cc62 'Revert "radv: disable support for VEGA for now."'
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-22 02:36:37 +02:00
Bas Nieuwenhuizen ad727b96b6 ac/nir: Account for compact array index in GS input load from LDS.
Mirrors the vram path.

Fixes: d4ecc3c929 'ac/nir: Add loading from LDS for merged GS.'
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-21 22:29:40 +02:00
Bas Nieuwenhuizen 67648c0faa radv: Don't compile shaders when they are cached already.
When the gs_copy_shader is NULL (due to an incomplete cache), but
the main shaders are found, we still do the nir, but we shouldn't
compile the shaders again. For merged shaders we should also account
for the missing shaders.

Fixes: ce03c119ce 'radv: Add code to compile merged shaders.'
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-21 22:29:34 +02:00
Bas Nieuwenhuizen 3bf954b28e radv: Don't check for max GL GS invocations.
We specify 127 instead of 32 as the limit in vulkan.

Fixes: 6bc42855f9 'radv: enable GS on GFX9'
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-21 22:29:09 +02:00
Bas Nieuwenhuizen 050f7e2df2 radv: Don't explicitly reference vertex shader for draw_id.
With merged shaders the vertex shader may not exist. This got in
because the offending patch was written before merged shaders were
upstream, but committed after.

Fixes: 75dfab24a2 'radv: refactor indirect draws with radv_draw_info'
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-10-21 20:00:22 +02:00
Bas Nieuwenhuizen 20fb15bfe4 radv: Don't reset cmd_buffer->state.dirty.
Otherwise for non-indexed draws we set and immediately unset
RADV_CMD_DIRTY_INDEX_BUFFER. As all the set functions should
clear their own bit, this is unnecessary.

Fixes: 341529dbee 'radv: use optimal packet order for draws'
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-10-21 20:00:16 +02:00
Bas Nieuwenhuizen fb55477990 radv: Correctly detect changed shaders for vertex descriptors.
As they were emitted after the new pipeline, the changed pipeline
detection was not working anymore.

Fixes: 341529dbee 'radv: use optimal packet order for draws'
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
2017-10-21 19:59:44 +02:00
Bas Nieuwenhuizen 24fe4e6143 ac/nir: Set larged wrokgroup size for GS on GFX9.
They don't take a single wave anymore and we need the barriers.

Fixes: 6bc42855f9 'radv: enable GS on GFX9'
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-21 12:46:44 +02:00
Bas Nieuwenhuizen 9e82f2b3ea ac/nir: Take the max workgroup size of all provided shaders.
Fixes: ffaf4d608a 'radv: Enable tessellation shaders for  GFX9.'
Reviewed-by: Dave Airlie <airlied@redhat.com>
2017-10-21 12:46:28 +02:00
Alex Smith 0fdd531457 radv: Fix pipeline cache locking issues
Need to lock around the whole process of retrieving cached shaders, and
around GetPipelineCacheData.

This fixes GPU hangs observed when creating multiple pipelines in
parallel, which appeared to be due to invalid shader code being pulled
from the cache.

Signed-off-by: Alex Smith <asmith@feralinteractive.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-21 03:52:43 +02:00
Lionel Landwerlin c71d44c7f8 anv: don't assert on device init on Cannonlake
v2: Warn that support is still in alpha (Jason)

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-21 02:37:33 +01:00
Lionel Landwerlin 0c95adaf9e anv: disable stencil pma fix on Gen > 9
This workaround isn't listed on Gen10.

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-21 02:37:33 +01:00
Lionel Landwerlin 0c92651a3b blorp: enable R32G32B32X32 blorp ccs copies
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-10-21 02:37:33 +01:00
Eric Anholt 48615d1ead meson: Fix vc5 deps on the XML-generated headers.
I typoed and was depending on v3d_xml.h (the gzipped xml)_, not on the
v3d_packet_v33_pack.h that the compiler and QPU packing actually use.
2017-10-20 17:16:00 -07:00
Eric Anholt 07bfdb478b broadcom/vc5: Propagate vc4 aliasing fix to vc5.
See e5fea0d621
2017-10-20 17:09:47 -07:00
Stefan Schake e5fea0d621 broadcom/vc4: Fix aliasing issue
This was causing Android clang version 3.8.256229 to miscompile,
presumably due to strict aliasing.

Fixes: 14dc281c13 ("vc4: Enforce one-uniform-per-instruction after optimization.")
2017-10-20 17:09:35 -07:00
Dylan Baker 035ec7a2bb meson: Add support for EGL glvnd
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Tested-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Lyude Paul <lyude@redhat.com>
2017-10-20 16:46:48 -07:00
Dylan Baker 108d257a16 meson: build libEGL
This is based heavily on Daniel Stone's work for the same, rebased on
master and with a number of TODO's fixed.

This does not implement glvnd (which is coming in a later patch)

Meson builds egl slightly differently than autotools, namely it doesn't
build an intermediate shared library. It doesn't do this because meson
doesn't have problems with the name of the library being dynamically
generated, so the glvnd and non-glvnd code can follow the same path.

v2: - Don't reuse variable (Eric E.)

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Tested-by: Eric Engestrom <eric.engestrom@imgtec.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
2017-10-20 16:46:48 -07:00
Dylan Baker ddf06a05ad meson: move wayland_drm_protocol generation to wayland-drm
These files are needed by both vulkan wayland-wsi and by egl
wayland-wsi, since the XML file is in src/egl/wayland/wayland-drm and we
can include this directory in such a way that it will be loaded before
egl and vulkan this allows us to avoid multiple calls to the same
generator.

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-and-Tested-by: Eric Engestrom <eric@engestrom.ch>
2017-10-20 16:46:48 -07:00
Dylan Baker 8d3b1210cb meson: Don't allow glx to be built without platform_x11
Previously this failed to change with_glx to disabled from auto if
platform_x11 was unset or if no opengl apis were being built.

v2: - swap conditional positions

Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-and-Tested-by: Eric Engestrom <eric@engestrom.ch>
2017-10-20 16:46:48 -07:00
Dylan Baker 8792a9e01b meson: bump libdrm_amdgpu requirement to 2.4.85
fixes: b603725703 ("configure.ac: Bump libdrm_amdgpu version to 2.4.85.")
Signed-off-by: Dylan Baker <dylanx.c.baker@intel.com>
Reviewed-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-20 16:45:39 -07:00
Eric Anholt 5a0d3e1129 nir: Print the components referenced for split or packed shader in/outs.
Having 4 variables all called "gl_in_TexCoord0@n" isn't very informative,
much better to see:

decl_var shader_in INTERP_MODE_NONE float gl_in_TexCoord0 (VARYING_SLOT_VAR0.x, 1, 0)
decl_var shader_in INTERP_MODE_NONE float gl_in_TexCoord0@0 (VARYING_SLOT_VAR0.y, 1, 0)
decl_var shader_in INTERP_MODE_NONE float gl_in_TexCoord0@1 (VARYING_SLOT_VAR0.z, 1, 0)
decl_var shader_in INTERP_MODE_NONE float gl_in_TexCoord0@2 (VARYING_SLOT_VAR0.w, 1, 0)

v2: Handle arrays and structs better (by Timothy)

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-10-20 16:26:46 -07:00
Eric Anholt d9ce4ac990 nir: Add a safety check that we don't remove dead I/O vars after lowering.
The pass only looks at var load/store intrinsics, not input load/store
intrinsics, so assert that we don't see the other type.

v2: Adjust comment indentation.

Reviewed-by: Timothy Arceri <tarceri@itsqueeze.com>
2017-10-20 16:26:07 -07:00
Andres Rodriguez a2c6fbb3ee radv: disable implicit sync for radv allocated bos v3
Implicit sync kicks in when a buffer is used by two different amdgpu
contexts simultaneously. Jobs that use explicit synchronization
mechanisms end up needlessly waiting to be scheduled for long periods
of time in order to achieve serialized execution.

This patch disables implicit synchronization for all radv allocations
except for wsi bos. The only systems that require implicit
synchronization are DRI2/3 and PRIME.

v2: mark wsi bos as RADV_MEM_IMPLICIT_SYNC
v3: Add drm version check (Bas)

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-21 01:15:54 +02:00
Andres Rodriguez eff2bdbd82 radv: factor out radv_alloc_memory
This allows us to pass extra parameters to the memory allocation
operation that are not defined in the vulkan spec. This is useful for
internal usage.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-21 01:15:49 +02:00
Andres Rodriguez 92724338ba radv: Expose VK_EXT_global_priority
Expose the extension string as supported

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-21 01:01:44 +02:00
Andres Rodriguez 9f7edf4d1f radv: don't skip PS/VS partial flush
This patch helps lower high priority compute latency. Found by
bisecting a perf regression on computeparticles with high priority
compute queues enabled.

Reverting this micro-optimization doesn't seem to have any negative
effect on performance on Dota2 or ssao.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-21 01:01:44 +02:00
Andres Rodriguez fd04f3eb86 radv: Implement VK_EXT_global_priority
This extension allows the caller to change a queue's system wide
priority. This is useful for applications with specific
latency constraints.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-21 01:01:44 +02:00
Andres Rodriguez 557de3b9ae radeonsi: hardcode shader WAVE_LIMIT to the maximum value
This is part of a cooperative scheduling approach used by radv. All
drivers in the stack must opt-in to resource arbitration, otherwise GL
based apps will be able to ignore system priorities.

We always hardcode the field to its maximum value, instead of attempting
to calculate an approximate usage. In testing, there were no benefits to
using anything other than the maximum.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-21 01:01:44 +02:00
Andres Rodriguez 986c4b0bd4 radv: hardcode shader WAVE_LIMIT to the maximum value
When WAVE_LIMIT is set, a submission will opt-in for SPI based resource
scheduling. Because this mechanism is cooperative, we must ensure that
all submissions have this field set, otherwise they will bypass resource
arbitration.

We always hardcode the field to its maximum value, instead of attempting
to calculate an approximate usage. In testing, there were no benefits to
using anything other than the maximum.

Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-21 01:01:44 +02:00
Andres Rodriguez b7c2f70656 vulkan: update headers & registry to VK 1.0.63
Signed-off-by: Andres Rodriguez <andresx7@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-10-21 01:01:44 +02:00
Bas Nieuwenhuizen b603725703 configure.ac: Bump libdrm_amdgpu version to 2.4.85.
For VK_EXT_global_priority in radv.

Acked-by: Andres Rodriguez <andresx7@gmail.com>
2017-10-21 01:01:44 +02:00
Eric Anholt 9b5fa214f4 broadcom/vc5: Use SETMSF to handle discards.
A bit of spec text suggested that (like vc4) condition codes should be
used for discards, and the simulator was fine with it, but the 7268
disagrees and you have to use SETMSF instead or the color comes through.
Fixes glsl-fs-discard-01 and many of the interpolation-with-clipping
tests.
2017-10-20 15:59:41 -07:00
Eric Anholt a48a38937c broadcom/vc5: Set the snorm/unorm packing functions to be lowered.
We don't have native instructions for them, so set up the lowering.  Once
we support the bfi instructions that get generated, they should start
actually working.
2017-10-20 15:59:41 -07:00
Eric Anholt 0e6fee7328 broadcom/vc5: Fix pasteo that broke vertex texturing.
We weren't ever filling in the texture state record, so we'd dereference
NULL from the shader.
2017-10-20 15:59:41 -07:00
Eric Anholt 34690536a7 broadcom/vc5: Move default attribute value setup to the CSO and fix them.
I was generating some stub values to bring the driver up, but fill them in
properly now.  We now set 1.0 or 1u as appropriate, and thanks to being in
their own BO it fixes piglit failures on the 7268 (where our 4-byte
alignment was insufficient).

Fixes const-packHalf2x16.shader_test
2017-10-20 15:59:41 -07:00
Eric Anholt fb15168919 broadcom/vc5: Move most of the shader state attribute record to the CSO.
This should reduce our draw-time overhead, and puts the code where it
should go long term.
2017-10-20 15:53:55 -07:00
Eric Anholt f4ff8f74ee broadcom/vc5: Fix build failure frm nir_shader::stage removal.
Fixes: 59fb59ad54 ("nir: Get rid of nir_shader::stage")
2017-10-20 15:53:55 -07:00
Matt Turner 9cd60fce9c i965/fs: Use align1 mode on ternary instructions on Gen10+
Align1 mode offers some nice features over align16, like access to more
data types and the ability to use a 16-bit immediate. This patch does
not start using any new features. It just emits ternary instructions in
align1 mode.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-10-20 15:00:17 -07:00
Matt Turner 8c16c9c677 i965: Add align1 ternary instruction emission support
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-10-20 15:00:17 -07:00
Matt Turner f11fa5ac6c i965: Add align1 ternary instruction disassembler support
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-10-20 15:00:17 -07:00
Matt Turner 6c7fc9b73a i965: Add align1 ternary instruction-word support
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-10-20 15:00:17 -07:00
Matt Turner 3b2c868848 i965: Add align1 ternary instruction support to conversion functions
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-10-20 15:00:17 -07:00
Matt Turner 281e8b8f27 i965: Add align1 ternary instruction field encodings
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-10-20 15:00:17 -07:00
Matt Turner 5f6ee55e68 i965: Add functions to abstract access to 3src register types
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-10-20 15:00:17 -07:00
Matt Turner e15dac319b i965: Rename brw_inst's functions that access the 3src register type
Put hw_ in the name so that it's clear these are the hardware encodings.

Similar to commit 9fb8323328 ("i965: Rename brw_inst's functions that
access the register type")

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-10-20 15:00:16 -07:00
Matt Turner e7f3b82e03 i965: Rename brw_inst 3src functions in preparation for align1
Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-10-20 15:00:16 -07:00
Matt Turner ba50b538af i965: Print subreg in units of type-size on ternary instructions
The instruction word contains SubRegNum[4:2] so it's in units of dwords
(hence the * 4 to get it in terms of bytes). Before this patch, the
subreg would have been wrong for DF arguments.

Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2017-10-20 15:00:16 -07:00