i965/fs: Use align1 mode on ternary instructions on Gen10+
Align1 mode offers some nice features over align16, like access to more data types and the ability to use a 16-bit immediate. This patch does not start using any new features. It just emits ternary instructions in align1 mode. Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
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@ -1729,13 +1729,15 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
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case BRW_OPCODE_MAD:
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assert(devinfo->gen >= 6);
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brw_set_default_access_mode(p, BRW_ALIGN_16);
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if (devinfo->gen < 10)
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brw_set_default_access_mode(p, BRW_ALIGN_16);
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brw_MAD(p, dst, src[0], src[1], src[2]);
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break;
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case BRW_OPCODE_LRP:
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assert(devinfo->gen >= 6);
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brw_set_default_access_mode(p, BRW_ALIGN_16);
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if (devinfo->gen < 10)
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brw_set_default_access_mode(p, BRW_ALIGN_16);
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brw_LRP(p, dst, src[0], src[1], src[2]);
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break;
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@ -1833,7 +1835,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
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case BRW_OPCODE_BFE:
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assert(devinfo->gen >= 7);
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brw_set_default_access_mode(p, BRW_ALIGN_16);
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if (devinfo->gen < 10)
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brw_set_default_access_mode(p, BRW_ALIGN_16);
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brw_BFE(p, dst, src[0], src[1], src[2]);
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break;
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@ -1843,7 +1846,8 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
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break;
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case BRW_OPCODE_BFI2:
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assert(devinfo->gen >= 7);
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brw_set_default_access_mode(p, BRW_ALIGN_16);
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if (devinfo->gen < 10)
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brw_set_default_access_mode(p, BRW_ALIGN_16);
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brw_BFI2(p, dst, src[0], src[1], src[2]);
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break;
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