radeonsi: hardcode shader WAVE_LIMIT to the maximum value
This is part of a cooperative scheduling approach used by radv. All drivers in the stack must opt-in to resource arbitration, otherwise GL based apps will be able to ignore system priorities. We always hardcode the field to its maximum value, instead of attempting to calculate an approximate usage. In testing, there were no benefits to using anything other than the maximum. Signed-off-by: Andres Rodriguez <andresx7@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
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@ -4994,11 +4994,15 @@ static void si_init_config(struct si_context *sctx)
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if (sctx->b.chip_class >= CIK) {
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if (sctx->b.chip_class >= GFX9) {
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si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, S_00B41C_CU_EN(0xffff));
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si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
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S_00B41C_CU_EN(0xffff) | S_00B41C_WAVE_LIMIT(0x3F));
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} else {
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si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS, S_00B51C_CU_EN(0xffff));
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si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS, 0);
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si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES, S_00B31C_CU_EN(0xffff));
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si_pm4_set_reg(pm4, R_00B51C_SPI_SHADER_PGM_RSRC3_LS,
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S_00B51C_CU_EN(0xffff) | S_00B51C_WAVE_LIMIT(0x3F));
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si_pm4_set_reg(pm4, R_00B41C_SPI_SHADER_PGM_RSRC3_HS,
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S_00B41C_WAVE_LIMIT(0x3F));
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si_pm4_set_reg(pm4, R_00B31C_SPI_SHADER_PGM_RSRC3_ES,
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S_00B31C_CU_EN(0xffff) | S_00B31C_WAVE_LIMIT(0x3F));
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/* If this is 0, Bonaire can hang even if GS isn't being used.
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* Other chips are unaffected. These are suboptimal values,
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@ -5008,7 +5012,8 @@ static void si_init_config(struct si_context *sctx)
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S_028A44_ES_VERTS_PER_SUBGRP(64) |
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S_028A44_GS_PRIMS_PER_SUBGRP(4));
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}
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si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS, S_00B21C_CU_EN(0xffff));
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si_pm4_set_reg(pm4, R_00B21C_SPI_SHADER_PGM_RSRC3_GS,
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S_00B21C_CU_EN(0xffff) | S_00B21C_WAVE_LIMIT(0x3F));
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/* Compute LATE_ALLOC_VS.LIMIT. */
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unsigned num_cu_per_sh = sscreen->b.info.num_good_compute_units /
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@ -5040,10 +5045,12 @@ static void si_init_config(struct si_context *sctx)
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/* VS can't execute on one CU if the limit is > 2. */
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si_pm4_set_reg(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
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S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff));
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S_00B118_CU_EN(late_alloc_limit > 2 ? 0xfffe : 0xffff) |
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S_00B118_WAVE_LIMIT(0x3F));
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si_pm4_set_reg(pm4, R_00B11C_SPI_SHADER_LATE_ALLOC_VS,
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S_00B11C_LIMIT(late_alloc_limit));
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si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS, S_00B01C_CU_EN(0xffff));
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si_pm4_set_reg(pm4, R_00B01C_SPI_SHADER_PGM_RSRC3_PS,
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S_00B01C_CU_EN(0xffff) | S_00B01C_WAVE_LIMIT(0x3F));
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}
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if (sctx->b.chip_class >= VI) {
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