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65029 Commits

Author SHA1 Message Date
Chia-I Wu 17401896dd ilo: enable HiZ in more cases on GEN6 
With layer offsetting killed, we no longer need to restrict HiZ to
non-mipmapped and non-arary depth buffers.
 2014-08-19 19:53:37 +08:00
Chia-I Wu 5b4fc5f156 ilo: remove layer offsetting 
Follow i965 to kill layer offsetting for GEN6.
 2014-08-19 19:53:37 +08:00
Chia-I Wu fb3d506431 ilo: migrate to ilo_layout 
Embed an ilo_layout in ilo_texture, and remove now duplicated members.
 2014-08-19 19:53:37 +08:00
Chia-I Wu 925359bc78 ilo: add new resource layout code 
Based on the old code, the new layout code describes the layout with the new,
well-documented, ilo_layout.  It also gains new features such as MCS support
and extended ARYSPC_LOD0 that i965 comes up with (see
6345a94a9b).
 2014-08-19 19:53:37 +08:00
Niels Ole Salscheider 5ae9bdafd4 gallium/radeon: Do not use u_upload_mgr for buffer downloads 
Instead create a staging texture with pipe_buffer_create and
PIPE_USAGE_STAGING.

u_upload_mgr sets the usage of its staging buffer to PIPE_USAGE_STREAM.
But since 150ac07b85 CPU -> GPU streaming buffers
are created in VRAM. Therefore the staging texture (in VRAM) does not offer any
performance improvements for buffer downloads.

Signed-off-by: Niels Ole Salscheider <niels_ole@salscheider-online.de>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
 2014-08-19 12:56:04 +02:00
Marek Olšák 498dc676ea r600g: copy IA_MULTI_VGT_PARAM programming from radeonsi for Cayman 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák f62f88274a radeonsi: bump PRIMGROUP_SIZE for some cases 
Recommended by hw people.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák 4be7ff5567 radeonsi: set PARTIAL_VS_WAVE(0) when appropriate 
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák 94e474f3c3 radeonsi: set IA_MULTI_VGT_PARAM on SI the same as on CIK (v2) 
Nothing's changed for CIK here.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák a333309979 radeonsi: simplify si_num_banks function 
This makes it easier to use.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák db51ab6d6a radeonsi: use r600_draw_rectangle from r600g 
Rectangles are easier than triangles for the rasterizer.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák 7792f9858b radeonsi: save scissor state and sample mask for u_blitter 
Cc: mesa-stable@lists.freedesktop.org
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák 25633c85e1 radeonsi: don't set CB_SHADER_MASK=1 if there are no color outputs 
This hack isn't needed anymore because of the previous u_blitter commit.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák a6fcdbf560 gallium/u_blitter: don't use an empty fragment shader if there's a colorbuffer 
This is custom code used by some drivers.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák 406ab1662c gallium/util: handle PIPE_BUFFER in util_pipe_tex_to_tgsi_tex 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák 8db7dacf29 rbug: only add textures to the list 
rbug-gui cannot display buffers, so it's pointless to add them.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák ddcbe9c526 rbug: fix a crash in sampler_view_destroy caused by incorrect context 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák ba81a3784b rbug: send the actual number of layers to the client 
This sends the correct value for array textures.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák 90d10f467f rbug: implement streamout context functions 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2014-08-19 12:20:18 +02:00
Marek Olšák b7b1ad9c6c rbug: fix crash in set_vertex_buffers 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2014-08-19 12:20:17 +02:00
Marek Olšák 4a3f156dd1 rbug: remove contexts from the list properly 
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
 2014-08-19 12:20:17 +02:00
Emil Velikov f921131a5c ilo: fold drm_intel_get_aperture_sizes() within probe_winsys() 
... and store the value in intel_winsys_info/ilo_dev_info.

Suggested-by: Chia-I Wu <olvaffe@gmail.com>
Signed-off-by: Emil Velikov <emil.l.velikov@gmail.com>

olv: check for errors and report raw values
 2014-08-19 17:45:00 +08:00
Matt Turner a4359bcaa5 i965/cfg: Add a foreach_block_and_inst_safe macro. 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
 2014-08-18 19:08:53 -07:00
Matt Turner 26624b85e7 i965/cfg: Add a foreach_inst_in_block_safe macro. 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
 2014-08-18 19:05:59 -07:00
Matt Turner c51b0861e4 i965/cfg: Add a foreach_block_safe macro. 
Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
 2014-08-18 19:05:59 -07:00
Matt Turner a3d0ccb037 i965: Pass a cfg pointer to generate_{code,assembly}. 
The loop over all instructions is now two-fold, over all of the blocks
and all of the instructions in each block.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
 2014-08-18 19:05:59 -07:00
Matt Turner 596990d91e i965: Add and use foreach_block macro. 
Use this as an opportunity to rename 'block_num' to 'num'. block->num is
clear, and block->block_num has always been redundant.
 2014-08-18 18:56:30 -07:00
Matt Turner d688667c7f i965/cfg: Embed link in bblock_t for main block list. 
The next patch adds a foreach_block (block, cfg) macro, which works
better if it provides a direct bblock_t pointer, rather than a
bblock_link pointer that you have to use to find the actual block.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
 2014-08-18 18:56:30 -07:00
Matt Turner 19c6617adf i965/fs: Optimize gl_FrontFacing calculation on Gen4/5. 
Doesn't use fewer instructions, but it does avoid writing the flag
register and if we want to switch the representation of true for Gen4/5
in the future, we can just delete the AND instruction.
 2014-08-18 18:35:56 -07:00
Matt Turner d1c43ed487 i965/fs: Optimize gl_FrontFacing calculation on Gen6+. 
total instructions in shared programs: 4288650 -> 4282838 (-0.14%)
instructions in affected programs:     595018 -> 589206 (-0.98%)

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
 2014-08-18 18:35:54 -07:00
Matt Turner 2e51dc838b i965: Use ~0 to represent true on Gen >= 6. 
total instructions in shared programs: 4292303 -> 4288650 (-0.09%)
instructions in affected programs:     299670 -> 296017 (-1.22%)

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
 2014-08-18 18:35:53 -07:00
Matt Turner cc60a487d1 i965/fs: Optimize emit_bool_to_cond_code for logical exprs. 
AND, OR, and XOR can generate the conditional code directly.

total instructions in shared programs: 4293335 -> 4292303 (-0.02%)
instructions in affected programs:     121408 -> 120376 (-0.85%)

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
 2014-08-18 18:35:53 -07:00
Matt Turner 2a6b6621d8 i965: Use UniformBooleanTrue value for boolean literal true. 
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
 2014-08-18 18:35:49 -07:00
Matt Turner 9e2e7c7dc0 glsl: Use UniformBooleanTrue value for uniform initializers. 
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
 2014-08-18 18:35:48 -07:00
Matt Turner 6df0fd8fe9 mesa: Upload boolean uniforms using UniformBooleanTrue. 
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
 2014-08-18 18:35:47 -07:00
Matt Turner e0f955abd3 i965: Remove dead call to _mesa_associate_uniform_storage(). 
Dead since the call to _mesa_generate_parameters_list_for_uniforms
was removed in commit 12751ef2. So this was why all of that code that
was supposed to fix up the value of a uniform bool to wasn't happening.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
 2014-08-18 18:35:41 -07:00
Matt Turner e87106d153 mapi: Inline shared-glapi/tests/Makefile. 
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
 2014-08-18 18:27:20 -07:00
Matt Turner 7172f02d7c mapi: Inline glapi/tests/Makefile. 
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
 2014-08-18 18:27:16 -07:00
Matt Turner 9dbb0f49b6 mapi: Inline glapi/Makefile. 
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
 2014-08-18 18:25:52 -07:00
Matt Turner dff5a219d0 mapi: Inline es2api/Makefile. 
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
 2014-08-18 18:25:29 -07:00
Matt Turner 18ef5136b6 mapi: Inline es1api/Makefile. 
Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
 2014-08-18 18:25:02 -07:00
Matt Turner c3ce1a942f mapi: Inline shared-glapi/Makefile. 2014-08-18 18:24:09 -07:00
Matt Turner 4ccd2a9f9b build: Let install-lib-links.mk handle .la files in subdirectories. 
The next patches are going to combine some of the mapi subdirectories'
Makefiles into a single Makefile, giving better build parallelism.

lib_LTLIBRARIES will be set to something like

   lib_LTLIBRARIES = shared-glapi/libglapi.la es2api/libGLESv2.la

and the current code in install-lib-links.mk simply prepends .libs/ and
replaces the .la in order to create the filenames that it needs to ln/cp
into the LIBDIR. This doesn't work when the .la file is actually in a
subdirectory.

This patch fixes this and puts .libs/ in the right place.

Reviewed-by: Kristian Høgsberg <krh@bitplanet.net>
Reviewed-by: Emil Velikov <emil.l.velikov@gmail.com>
 2014-08-18 18:22:40 -07:00
Matt Turner 45eb065668 i965: Enable instruction compaction on Gen8+. 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2014-08-18 18:18:50 -07:00
Matt Turner 31eed95b22 i965: Add support for compacting 3-src instructions on Gen8. 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2014-08-18 18:18:50 -07:00
Matt Turner fb1db6753f i965: Add support for compacting 1- and 2-src instructions on Gen8. 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2014-08-18 18:18:50 -07:00
Matt Turner 3904d404a3 i965/gen8: Add 3-src instruction compaction tables. 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2014-08-18 18:18:50 -07:00
Matt Turner 190ce6b093 i965/gen8: Add instruction compaction tables. 
Acked-by: Kenneth Graunke <kenneth@whitecape.org>
 2014-08-18 18:18:50 -07:00
Matt Turner 2faa1a414c i965: Update JIP/UIP compaction code to operate on bytes. 
JIP/UIP were previously in units of compacted instructions. On Gen8
they're in units of bytes.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2014-08-18 18:18:50 -07:00
Matt Turner 23ab55cb6c i965: Reverse condition ordering to let us support other gens. 
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
 2014-08-18 18:18:50 -07:00