2017-11-24 07:15:14 +00:00
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/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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2018-08-19 08:31:46 +01:00
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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2017-11-24 07:15:14 +00:00
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*
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2018-08-19 08:31:46 +01:00
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* The above copyright notice and this permission notice shall be included
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* in all copies or substantial portions of the Software.
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2017-11-24 07:15:14 +00:00
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*
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2018-08-19 08:31:46 +01:00
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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2017-11-24 07:15:14 +00:00
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*/
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2018-07-31 07:49:34 +01:00
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/**
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* @file iris_screen.c
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*
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* Screen related driver hooks and capability lists.
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*
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* A program may use multiple rendering contexts (iris_context), but
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* they all share a common screen (iris_screen). Global driver state
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* can be stored in the screen; it may be accessed by multiple threads.
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*/
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2017-11-24 07:15:14 +00:00
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#include <stdio.h>
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#include <errno.h>
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#include <sys/ioctl.h>
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#include "pipe/p_defines.h"
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#include "pipe/p_state.h"
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#include "pipe/p_context.h"
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#include "pipe/p_screen.h"
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2018-11-22 10:55:27 +00:00
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#include "util/debug.h"
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2017-11-24 07:15:14 +00:00
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#include "util/u_inlines.h"
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2019-06-27 23:05:31 +01:00
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#include "util/format/u_format.h"
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2018-11-28 23:10:07 +00:00
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#include "util/u_transfer_helper.h"
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2017-11-24 07:15:14 +00:00
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#include "util/u_upload_mgr.h"
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#include "util/ralloc.h"
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2019-04-19 06:29:27 +01:00
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#include "util/xmlconfig.h"
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2017-11-24 07:15:14 +00:00
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#include "drm-uapi/i915_drm.h"
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#include "iris_context.h"
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2018-09-29 09:47:01 +01:00
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#include "iris_defines.h"
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2018-11-09 15:02:12 +00:00
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#include "iris_fence.h"
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2018-01-12 06:18:54 +00:00
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#include "iris_pipe.h"
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2017-11-24 07:15:14 +00:00
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#include "iris_resource.h"
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#include "iris_screen.h"
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2020-08-15 06:26:05 +01:00
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#include "compiler/glsl_types.h"
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2017-11-24 07:15:14 +00:00
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#include "intel/compiler/brw_compiler.h"
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2021-03-03 21:20:06 +00:00
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#include "intel/common/intel_gem.h"
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#include "intel/common/intel_l3_config.h"
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#include "intel/common/intel_uuid.h"
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2019-04-22 19:43:12 +01:00
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#include "iris_monitor.h"
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2017-11-24 07:15:14 +00:00
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2020-11-11 06:59:46 +00:00
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#define genX_call(devinfo, func, ...) \
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2021-03-29 21:43:47 +01:00
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switch ((devinfo)->verx10) { \
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2021-02-27 23:38:53 +00:00
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case 125: \
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2021-03-29 23:40:04 +01:00
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gfx125_##func(__VA_ARGS__); \
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2020-11-11 06:59:46 +00:00
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break; \
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2021-02-27 23:38:53 +00:00
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case 120: \
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2021-03-29 23:40:04 +01:00
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gfx12_##func(__VA_ARGS__); \
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2021-02-27 23:38:53 +00:00
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break; \
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case 110: \
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2021-03-29 23:40:04 +01:00
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gfx11_##func(__VA_ARGS__); \
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2020-11-11 06:59:46 +00:00
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break; \
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2021-02-27 23:38:53 +00:00
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case 90: \
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2021-03-29 23:40:04 +01:00
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gfx9_##func(__VA_ARGS__); \
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2020-11-11 06:59:46 +00:00
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break; \
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2021-02-27 23:38:53 +00:00
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case 80: \
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2021-03-29 23:40:04 +01:00
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gfx8_##func(__VA_ARGS__); \
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2020-11-11 06:59:46 +00:00
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break; \
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default: \
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unreachable("Unknown hardware generation"); \
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}
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2017-11-24 07:15:14 +00:00
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static void
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iris_flush_frontbuffer(struct pipe_screen *_screen,
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2020-12-10 18:50:54 +00:00
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struct pipe_context *_pipe,
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2017-11-24 07:15:14 +00:00
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struct pipe_resource *resource,
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unsigned level, unsigned layer,
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void *context_private, struct pipe_box *box)
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{
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}
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static const char *
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iris_get_vendor(struct pipe_screen *pscreen)
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{
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2019-04-16 08:27:33 +01:00
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return "Intel";
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2017-11-24 07:15:14 +00:00
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}
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static const char *
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iris_get_device_vendor(struct pipe_screen *pscreen)
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{
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return "Intel";
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}
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2020-03-26 16:04:19 +00:00
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static void
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iris_get_device_uuid(struct pipe_screen *pscreen, char *uuid)
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{
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struct iris_screen *screen = (struct iris_screen *)pscreen;
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const struct isl_device *isldev = &screen->isl_dev;
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2021-03-03 21:49:18 +00:00
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intel_uuid_compute_device_id((uint8_t *)uuid, isldev, PIPE_UUID_SIZE);
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2020-03-26 16:04:19 +00:00
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}
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static void
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iris_get_driver_uuid(struct pipe_screen *pscreen, char *uuid)
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{
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struct iris_screen *screen = (struct iris_screen *)pscreen;
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2021-04-05 21:19:39 +01:00
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const struct intel_device_info *devinfo = &screen->devinfo;
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2020-03-26 16:04:19 +00:00
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2021-03-03 21:49:18 +00:00
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intel_uuid_compute_driver_id((uint8_t *)uuid, devinfo, PIPE_UUID_SIZE);
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2020-03-26 16:04:19 +00:00
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}
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2020-08-20 23:10:59 +01:00
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static bool
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iris_enable_clover()
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{
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static int enable = -1;
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if (enable < 0)
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enable = env_var_as_boolean("IRIS_ENABLE_CLOVER", false);
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return enable;
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}
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static void
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iris_warn_clover()
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{
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static bool warned = false;
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if (warned)
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return;
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warned = true;
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fprintf(stderr, "WARNING: OpenCL support via iris+clover is incomplete.\n"
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"For a complete and conformant OpenCL implementation, use\n"
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"https://github.com/intel/compute-runtime instead\n");
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}
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2017-11-24 07:15:14 +00:00
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static const char *
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iris_get_name(struct pipe_screen *pscreen)
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{
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struct iris_screen *screen = (struct iris_screen *)pscreen;
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2019-04-16 08:27:33 +01:00
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static char buf[128];
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2021-04-05 23:59:35 +01:00
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const char *name = intel_get_device_name(screen->pci_id);
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2017-11-24 07:15:14 +00:00
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2019-12-17 10:57:55 +00:00
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if (!name)
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name = "Intel Unknown";
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2019-04-16 08:27:33 +01:00
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2019-12-17 10:57:55 +00:00
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snprintf(buf, sizeof(buf), "Mesa %s", name);
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2019-04-24 20:53:30 +01:00
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return buf;
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2017-11-24 07:15:14 +00:00
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}
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static int
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iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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{
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struct iris_screen *screen = (struct iris_screen *)pscreen;
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2021-04-05 21:19:39 +01:00
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const struct intel_device_info *devinfo = &screen->devinfo;
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2017-11-24 07:15:14 +00:00
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switch (param) {
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case PIPE_CAP_NPOT_TEXTURES:
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case PIPE_CAP_ANISOTROPIC_FILTER:
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case PIPE_CAP_POINT_SPRITE:
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case PIPE_CAP_OCCLUSION_QUERY:
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case PIPE_CAP_QUERY_TIME_ELAPSED:
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case PIPE_CAP_TEXTURE_SWIZZLE:
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2018-06-24 01:30:18 +01:00
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_BLEND_EQUATION_SEPARATE:
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2019-07-05 15:36:41 +01:00
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case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD:
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case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES:
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case PIPE_CAP_VERTEX_SHADER_SATURATE:
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_PRIMITIVE_RESTART:
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2020-06-18 14:18:54 +01:00
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case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX:
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_INDEP_BLEND_ENABLE:
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case PIPE_CAP_INDEP_BLEND_FUNC:
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case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
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case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
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case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
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case PIPE_CAP_DEPTH_CLIP_DISABLE:
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case PIPE_CAP_TGSI_INSTANCEID:
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case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
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case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
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case PIPE_CAP_SEAMLESS_CUBE_MAP:
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case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
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case PIPE_CAP_CONDITIONAL_RENDER:
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case PIPE_CAP_TEXTURE_BARRIER:
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case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
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case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
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case PIPE_CAP_COMPUTE:
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case PIPE_CAP_START_INSTANCE:
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case PIPE_CAP_QUERY_TIMESTAMP:
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case PIPE_CAP_TEXTURE_MULTISAMPLE:
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case PIPE_CAP_CUBE_MAP_ARRAY:
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case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
|
2019-01-11 21:39:04 +00:00
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case PIPE_CAP_QUERY_PIPELINE_STATISTICS_SINGLE:
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
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case PIPE_CAP_TEXTURE_QUERY_LOD:
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case PIPE_CAP_SAMPLE_SHADING:
|
2018-10-05 23:25:53 +01:00
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case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_DRAW_INDIRECT:
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2019-05-09 22:44:39 +01:00
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case PIPE_CAP_MULTI_DRAW_INDIRECT:
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case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
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case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
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2018-08-02 06:27:16 +01:00
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case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
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2019-06-10 22:03:03 +01:00
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case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_ACCELERATED:
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case PIPE_CAP_UMA:
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case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
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case PIPE_CAP_CLIP_HALFZ:
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2018-02-10 07:38:08 +00:00
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case PIPE_CAP_TGSI_TEXCOORD:
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2018-04-26 07:47:06 +01:00
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case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
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case PIPE_CAP_DOUBLES:
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case PIPE_CAP_INT64:
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case PIPE_CAP_INT64_DIVMOD:
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case PIPE_CAP_SAMPLER_VIEW_TARGET:
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case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
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2019-05-08 19:33:50 +01:00
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case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
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2018-04-26 07:47:06 +01:00
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case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
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case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
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case PIPE_CAP_CULL_DISTANCE:
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2018-06-06 10:16:52 +01:00
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case PIPE_CAP_PACKED_UNIFORMS:
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2018-06-18 19:30:23 +01:00
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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2018-07-24 22:49:13 +01:00
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case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
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case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
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case PIPE_CAP_POLYGON_OFFSET_CLAMP:
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2018-08-02 06:27:16 +01:00
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case PIPE_CAP_QUERY_SO_OVERFLOW:
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2018-09-18 00:37:26 +01:00
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case PIPE_CAP_QUERY_BUFFER_OBJECT:
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2018-08-02 06:27:16 +01:00
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case PIPE_CAP_TGSI_TEX_TXF_LZ:
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2018-10-15 17:51:54 +01:00
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case PIPE_CAP_TGSI_TXQS:
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2018-08-02 06:27:16 +01:00
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case PIPE_CAP_TGSI_CLOCK:
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case PIPE_CAP_TGSI_BALLOT:
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2018-08-11 20:48:24 +01:00
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case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
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2018-08-15 09:34:10 +01:00
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case PIPE_CAP_CLEAR_TEXTURE:
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2020-03-24 15:58:29 +00:00
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case PIPE_CAP_CLEAR_SCISSORED:
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2018-09-29 10:04:48 +01:00
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case PIPE_CAP_TGSI_VOTE:
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2018-09-07 03:42:58 +01:00
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case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
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case PIPE_CAP_TEXTURE_GATHER_SM5:
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2018-09-15 23:27:59 +01:00
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case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
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2018-09-19 18:17:23 +01:00
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case PIPE_CAP_GLSL_TESS_LEVELS_AS_INPUTS:
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2018-11-20 21:42:31 +00:00
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case PIPE_CAP_LOAD_CONSTBUF:
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2019-01-23 10:58:59 +00:00
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case PIPE_CAP_NIR_COMPACT_ARRAYS:
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2019-02-26 13:37:23 +00:00
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case PIPE_CAP_DRAW_PARAMETERS:
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2019-07-18 15:59:44 +01:00
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case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
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2019-02-13 22:28:20 +00:00
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case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
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2019-03-28 08:48:38 +00:00
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case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
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2019-03-12 21:51:22 +00:00
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case PIPE_CAP_INVALIDATE_BUFFER:
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2019-05-01 22:34:00 +01:00
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case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
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2019-06-10 04:58:08 +01:00
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case PIPE_CAP_CS_DERIVED_SYSTEM_VALUES_SUPPORTED:
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2019-07-25 22:07:36 +01:00
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case PIPE_CAP_TEXTURE_SHADOW_LOD:
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2019-07-31 23:47:34 +01:00
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case PIPE_CAP_SHADER_SAMPLES_IDENTICAL:
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2019-08-06 00:56:42 +01:00
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case PIPE_CAP_GL_SPIRV:
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case PIPE_CAP_GL_SPIRV_VARIABLE_POINTERS:
|
2019-09-20 17:20:17 +01:00
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|
case PIPE_CAP_DEMOTE_TO_HELPER_INVOCATION:
|
2019-12-19 18:56:03 +00:00
|
|
|
case PIPE_CAP_NATIVE_FENCE_FD:
|
2020-10-26 18:43:35 +00:00
|
|
|
case PIPE_CAP_MEMOBJ:
|
2020-03-10 07:21:09 +00:00
|
|
|
case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
|
2020-03-26 16:23:08 +00:00
|
|
|
case PIPE_CAP_FENCE_SIGNAL:
|
2017-11-24 07:15:14 +00:00
|
|
|
return true;
|
2019-05-15 04:23:36 +01:00
|
|
|
case PIPE_CAP_FBFETCH:
|
2019-07-16 19:29:47 +01:00
|
|
|
return BRW_MAX_DRAW_BUFFERS;
|
2019-05-15 04:31:46 +01:00
|
|
|
case PIPE_CAP_FBFETCH_COHERENT:
|
2019-04-18 18:21:56 +01:00
|
|
|
case PIPE_CAP_CONSERVATIVE_RASTER_INNER_COVERAGE:
|
2018-11-08 00:38:48 +00:00
|
|
|
case PIPE_CAP_POST_DEPTH_COVERAGE:
|
|
|
|
case PIPE_CAP_SHADER_STENCIL_EXPORT:
|
2019-04-29 21:25:12 +01:00
|
|
|
case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE:
|
2019-05-11 02:34:25 +01:00
|
|
|
case PIPE_CAP_FRAGMENT_SHADER_INTERLOCK:
|
2019-06-12 04:07:32 +01:00
|
|
|
case PIPE_CAP_ATOMIC_FLOAT_MINMAX:
|
2021-03-29 22:41:58 +01:00
|
|
|
return devinfo->ver >= 9;
|
2020-04-13 23:35:50 +01:00
|
|
|
case PIPE_CAP_DEPTH_BOUNDS_TEST:
|
2021-03-29 22:41:58 +01:00
|
|
|
return devinfo->ver >= 12;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
|
|
|
|
return 1;
|
|
|
|
case PIPE_CAP_MAX_RENDER_TARGETS:
|
|
|
|
return BRW_MAX_DRAW_BUFFERS;
|
2019-04-29 23:38:24 +01:00
|
|
|
case PIPE_CAP_MAX_TEXTURE_2D_SIZE:
|
|
|
|
return 16384;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
|
2019-02-14 00:41:46 +00:00
|
|
|
return IRIS_MAX_MIPLEVELS; /* 16384x16384 */
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
|
|
|
|
return 12; /* 2048x2048 */
|
|
|
|
case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
|
|
|
|
return 4;
|
|
|
|
case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
|
|
|
|
return 2048;
|
|
|
|
case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
|
|
|
|
return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
|
|
|
|
case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
|
|
|
|
return BRW_MAX_SOL_BINDINGS;
|
|
|
|
case PIPE_CAP_GLSL_FEATURE_LEVEL:
|
2018-06-20 05:46:56 +01:00
|
|
|
case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
|
2019-06-28 05:55:20 +01:00
|
|
|
return 460;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
|
|
|
|
/* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
|
|
|
|
return 32;
|
2018-12-21 11:04:18 +00:00
|
|
|
case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
|
|
|
|
return IRIS_MAP_BUFFER_ALIGNMENT;
|
2018-07-25 01:03:48 +01:00
|
|
|
case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
|
2021-07-02 20:39:49 +01:00
|
|
|
return 4;
|
2018-09-01 05:22:31 +01:00
|
|
|
case PIPE_CAP_MAX_SHADER_BUFFER_SIZE:
|
|
|
|
return 1 << 27;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
|
2018-09-07 03:42:58 +01:00
|
|
|
return 16; // XXX: u_screen says 256 is the minimum value...
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
|
2019-07-03 23:12:17 +01:00
|
|
|
return true;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
|
2018-10-22 22:28:54 +01:00
|
|
|
return IRIS_MAX_TEXTURE_BUFFER_SIZE;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_MAX_VIEWPORTS:
|
|
|
|
return 16;
|
|
|
|
case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
|
|
|
|
return 256;
|
|
|
|
case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
|
2018-07-26 09:11:11 +01:00
|
|
|
return 1024;
|
2018-09-01 05:22:31 +01:00
|
|
|
case PIPE_CAP_MAX_GS_INVOCATIONS:
|
|
|
|
return 32;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
|
2018-07-26 07:33:16 +01:00
|
|
|
return 4;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
|
|
|
|
return -32;
|
|
|
|
case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
|
|
|
|
return 31;
|
|
|
|
case PIPE_CAP_MAX_VERTEX_STREAMS:
|
|
|
|
return 4;
|
|
|
|
case PIPE_CAP_VENDOR_ID:
|
|
|
|
return 0x8086;
|
|
|
|
case PIPE_CAP_DEVICE_ID:
|
|
|
|
return screen->pci_id;
|
2019-05-08 20:37:32 +01:00
|
|
|
case PIPE_CAP_VIDEO_MEMORY: {
|
|
|
|
/* Once a batch uses more than 75% of the maximum mappable size, we
|
|
|
|
* assume that there's some fragmentation, and we start doing extra
|
|
|
|
* flushing, etc. That's the big cliff apps will care about.
|
|
|
|
*/
|
|
|
|
const unsigned gpu_mappable_megabytes =
|
2020-05-14 19:44:29 +01:00
|
|
|
(devinfo->aperture_bytes * 3 / 4) / (1024 * 1024);
|
2019-05-08 20:37:32 +01:00
|
|
|
|
|
|
|
const long system_memory_pages = sysconf(_SC_PHYS_PAGES);
|
|
|
|
const long system_page_size = sysconf(_SC_PAGE_SIZE);
|
|
|
|
|
|
|
|
if (system_memory_pages <= 0 || system_page_size <= 0)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
const uint64_t system_memory_bytes =
|
|
|
|
(uint64_t) system_memory_pages * (uint64_t) system_page_size;
|
|
|
|
|
|
|
|
const unsigned system_memory_megabytes =
|
|
|
|
(unsigned) (system_memory_bytes / (1024 * 1024));
|
|
|
|
|
|
|
|
return MIN2(system_memory_megabytes, gpu_mappable_megabytes);
|
|
|
|
}
|
2018-07-19 05:08:32 +01:00
|
|
|
case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
|
2019-02-10 22:23:45 +00:00
|
|
|
case PIPE_CAP_MAX_VARYINGS:
|
2018-07-19 05:08:32 +01:00
|
|
|
return 32;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
|
2018-07-31 14:47:02 +01:00
|
|
|
/* AMD_pinned_memory assumes the flexibility of using client memory
|
|
|
|
* for any buffer (incl. vertex buffers) which rules out the prospect
|
|
|
|
* of using snooped buffers, as using snooped buffers without
|
|
|
|
* cogniscience is likely to be detrimental to performance and require
|
|
|
|
* extensive checking in the driver for correctness, e.g. to prevent
|
|
|
|
* illegal snoop <-> snoop transfers.
|
|
|
|
*/
|
|
|
|
return devinfo->has_llc;
|
2019-10-14 09:05:46 +01:00
|
|
|
case PIPE_CAP_THROTTLE:
|
2019-09-05 09:52:17 +01:00
|
|
|
return screen->driconf.disable_throttling ? 0 : 1;
|
2018-09-07 03:42:58 +01:00
|
|
|
|
2019-02-22 23:31:56 +00:00
|
|
|
case PIPE_CAP_CONTEXT_PRIORITY_MASK:
|
|
|
|
return PIPE_CONTEXT_PRIORITY_LOW |
|
|
|
|
PIPE_CONTEXT_PRIORITY_MEDIUM |
|
|
|
|
PIPE_CONTEXT_PRIORITY_HIGH;
|
|
|
|
|
2019-12-05 12:49:12 +00:00
|
|
|
case PIPE_CAP_FRONTEND_NOOP:
|
|
|
|
return true;
|
|
|
|
|
2018-09-07 03:42:58 +01:00
|
|
|
// XXX: don't hardcode 00:00:02.0 PCI here
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_PCI_GROUP:
|
2018-09-07 03:42:58 +01:00
|
|
|
return 0;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_PCI_BUS:
|
2018-09-07 03:42:58 +01:00
|
|
|
return 0;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_PCI_DEVICE:
|
2018-09-07 03:42:58 +01:00
|
|
|
return 2;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_CAP_PCI_FUNCTION:
|
2018-09-07 03:42:58 +01:00
|
|
|
return 0;
|
|
|
|
|
2019-11-14 22:20:48 +00:00
|
|
|
case PIPE_CAP_OPENCL_INTEGER_FUNCTIONS:
|
|
|
|
case PIPE_CAP_INTEGER_MULTIPLY_32X16:
|
|
|
|
return true;
|
|
|
|
|
2021-03-25 16:29:11 +00:00
|
|
|
case PIPE_CAP_ALLOW_DYNAMIC_VAO_FASTPATH:
|
|
|
|
/* Internal details of VF cache make this optimization harmful on GFX
|
|
|
|
* version 8 and 9, because generated VERTEX_BUFFER_STATEs are cached
|
|
|
|
* separately.
|
|
|
|
*/
|
2021-03-29 22:41:58 +01:00
|
|
|
return devinfo->ver >= 11;
|
2021-03-25 16:29:11 +00:00
|
|
|
|
2018-09-07 03:42:58 +01:00
|
|
|
default:
|
|
|
|
return u_pipe_screen_get_param_defaults(pscreen, param);
|
2017-11-24 07:15:14 +00:00
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static float
|
|
|
|
iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
|
|
|
|
{
|
|
|
|
switch (param) {
|
|
|
|
case PIPE_CAPF_MAX_LINE_WIDTH:
|
|
|
|
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
|
|
|
|
return 7.375f;
|
|
|
|
|
|
|
|
case PIPE_CAPF_MAX_POINT_WIDTH:
|
|
|
|
case PIPE_CAPF_MAX_POINT_WIDTH_AA:
|
|
|
|
return 255.0f;
|
|
|
|
|
|
|
|
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
|
|
|
|
return 16.0f;
|
|
|
|
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
|
|
|
|
return 15.0f;
|
2018-05-03 05:52:26 +01:00
|
|
|
case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
|
|
|
|
case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
|
|
|
|
case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
|
|
|
|
return 0.0f;
|
2017-11-24 07:15:14 +00:00
|
|
|
default:
|
|
|
|
unreachable("unknown param");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
iris_get_shader_param(struct pipe_screen *pscreen,
|
2018-07-20 09:18:57 +01:00
|
|
|
enum pipe_shader_type p_stage,
|
2017-11-24 07:15:14 +00:00
|
|
|
enum pipe_shader_cap param)
|
|
|
|
{
|
2018-07-20 09:18:57 +01:00
|
|
|
gl_shader_stage stage = stage_from_pipe(p_stage);
|
2017-11-24 07:15:14 +00:00
|
|
|
|
|
|
|
/* this is probably not totally correct.. but it's a start: */
|
|
|
|
switch (param) {
|
|
|
|
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
|
2018-07-20 09:18:57 +01:00
|
|
|
return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
|
2018-07-20 09:18:57 +01:00
|
|
|
return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
|
2017-11-24 07:15:14 +00:00
|
|
|
|
|
|
|
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
|
|
|
|
return UINT_MAX;
|
|
|
|
|
|
|
|
case PIPE_SHADER_CAP_MAX_INPUTS:
|
2018-07-20 09:18:57 +01:00
|
|
|
return stage == MESA_SHADER_VERTEX ? 16 : 32;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_SHADER_CAP_MAX_OUTPUTS:
|
|
|
|
return 32;
|
|
|
|
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
|
|
|
|
return 16 * 1024 * sizeof(float);
|
|
|
|
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
|
|
|
|
return 16;
|
|
|
|
case PIPE_SHADER_CAP_MAX_TEMPS:
|
|
|
|
return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
|
|
|
|
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
|
|
|
|
return 0;
|
|
|
|
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
|
|
|
|
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
|
|
|
|
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
|
|
|
|
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
|
2018-11-21 02:16:02 +00:00
|
|
|
/* Lie about these to avoid st/mesa's GLSL IR lowering of indirects,
|
|
|
|
* which we don't want. Our compiler backend will check brw_compiler's
|
|
|
|
* options and call nir_lower_indirect_derefs appropriately anyway.
|
|
|
|
*/
|
|
|
|
return true;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_SHADER_CAP_SUBROUTINES:
|
|
|
|
return 0;
|
|
|
|
case PIPE_SHADER_CAP_INTEGERS:
|
|
|
|
return 1;
|
|
|
|
case PIPE_SHADER_CAP_INT64_ATOMICS:
|
|
|
|
case PIPE_SHADER_CAP_FP16:
|
2020-05-10 22:05:00 +01:00
|
|
|
case PIPE_SHADER_CAP_FP16_DERIVATIVES:
|
2021-02-12 14:32:25 +00:00
|
|
|
case PIPE_SHADER_CAP_FP16_CONST_BUFFERS:
|
2020-05-10 22:05:00 +01:00
|
|
|
case PIPE_SHADER_CAP_INT16:
|
2020-08-05 18:21:46 +01:00
|
|
|
case PIPE_SHADER_CAP_GLSL_16BIT_CONSTS:
|
2017-11-24 07:15:14 +00:00
|
|
|
return 0;
|
|
|
|
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
|
|
|
|
return IRIS_MAX_TEXTURE_SAMPLERS;
|
2018-07-25 01:44:09 +01:00
|
|
|
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
|
|
|
|
return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
|
|
|
|
return 0;
|
|
|
|
case PIPE_SHADER_CAP_PREFERRED_IR:
|
|
|
|
return PIPE_SHADER_IR_NIR;
|
2020-08-20 23:10:59 +01:00
|
|
|
case PIPE_SHADER_CAP_SUPPORTED_IRS: {
|
|
|
|
int irs = 1 << PIPE_SHADER_IR_NIR;
|
|
|
|
if (iris_enable_clover())
|
|
|
|
irs |= 1 << PIPE_SHADER_IR_NIR_SERIALIZED;
|
|
|
|
return irs;
|
|
|
|
}
|
2019-05-05 10:39:23 +01:00
|
|
|
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
|
|
|
|
return 1;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
|
2019-06-26 03:34:45 +01:00
|
|
|
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
|
2017-11-24 07:15:14 +00:00
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
unreachable("unknown shader param");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
iris_get_compute_param(struct pipe_screen *pscreen,
|
|
|
|
enum pipe_shader_ir ir_type,
|
|
|
|
enum pipe_compute_cap param,
|
|
|
|
void *ret)
|
|
|
|
{
|
2018-07-27 07:13:51 +01:00
|
|
|
struct iris_screen *screen = (struct iris_screen *)pscreen;
|
2021-04-05 21:19:39 +01:00
|
|
|
const struct intel_device_info *devinfo = &screen->devinfo;
|
2018-07-27 07:13:51 +01:00
|
|
|
|
2020-05-21 07:32:18 +01:00
|
|
|
/* Limit max_threads to 64 for the GPGPU_WALKER command. */
|
|
|
|
const unsigned max_threads = MIN2(64, devinfo->max_cs_threads);
|
2018-07-27 07:13:51 +01:00
|
|
|
const uint32_t max_invocations = 32 * max_threads;
|
|
|
|
|
|
|
|
#define RET(x) do { \
|
|
|
|
if (ret) \
|
|
|
|
memcpy(ret, x, sizeof(x)); \
|
|
|
|
return sizeof(x); \
|
|
|
|
} while (0)
|
|
|
|
|
|
|
|
switch (param) {
|
2020-08-20 23:10:59 +01:00
|
|
|
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
|
|
|
|
/* This gets queried on clover device init and is never queried by the
|
|
|
|
* OpenGL state tracker.
|
|
|
|
*/
|
|
|
|
iris_warn_clover();
|
|
|
|
RET((uint32_t []){ 64 });
|
|
|
|
|
2018-07-27 07:13:51 +01:00
|
|
|
case PIPE_COMPUTE_CAP_IR_TARGET:
|
|
|
|
if (ret)
|
|
|
|
strcpy(ret, "gen");
|
|
|
|
return 4;
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_GRID_DIMENSION:
|
|
|
|
RET((uint64_t []) { 3 });
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_GRID_SIZE:
|
|
|
|
RET(((uint64_t []) { 65535, 65535, 65535 }));
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
|
|
|
|
/* MaxComputeWorkGroupSize[0..2] */
|
|
|
|
RET(((uint64_t []) {max_invocations, max_invocations, max_invocations}));
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
|
|
|
|
/* MaxComputeWorkGroupInvocations */
|
2020-05-21 07:32:18 +01:00
|
|
|
case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK:
|
|
|
|
/* MaxComputeVariableGroupInvocations */
|
2018-07-27 07:13:51 +01:00
|
|
|
RET((uint64_t []) { max_invocations });
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE:
|
|
|
|
/* MaxComputeSharedMemorySize */
|
|
|
|
RET((uint64_t []) { 64 * 1024 });
|
|
|
|
|
2020-08-20 23:10:59 +01:00
|
|
|
case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED:
|
|
|
|
RET((uint32_t []) { 0 });
|
|
|
|
|
2018-07-27 07:13:51 +01:00
|
|
|
case PIPE_COMPUTE_CAP_SUBGROUP_SIZE:
|
|
|
|
RET((uint32_t []) { BRW_SUBGROUP_SIZE });
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE:
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE:
|
2020-08-20 23:10:59 +01:00
|
|
|
RET((uint64_t []) { 1 << 30 }); /* TODO */
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY:
|
|
|
|
RET((uint32_t []) { 400 }); /* TODO */
|
|
|
|
|
|
|
|
case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS: {
|
|
|
|
unsigned total_num_subslices = 0;
|
|
|
|
for (unsigned i = 0; i < devinfo->num_slices; i++)
|
|
|
|
total_num_subslices += devinfo->num_subslices[i];
|
|
|
|
RET((uint32_t []) { total_num_subslices });
|
|
|
|
}
|
|
|
|
|
2018-07-27 07:13:51 +01:00
|
|
|
case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE:
|
2020-08-20 23:10:59 +01:00
|
|
|
/* MaxComputeSharedMemorySize */
|
|
|
|
RET((uint64_t []) { 64 * 1024 });
|
|
|
|
|
2018-07-27 07:13:51 +01:00
|
|
|
case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE:
|
2020-08-20 23:10:59 +01:00
|
|
|
/* We could probably allow more; this is the OpenCL minimum */
|
|
|
|
RET((uint64_t []) { 1024 });
|
2018-07-27 07:13:51 +01:00
|
|
|
|
|
|
|
default:
|
|
|
|
unreachable("unknown compute param");
|
|
|
|
}
|
2017-11-24 07:15:14 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t
|
|
|
|
iris_get_timestamp(struct pipe_screen *pscreen)
|
|
|
|
{
|
2018-09-28 14:42:51 +01:00
|
|
|
struct iris_screen *screen = (struct iris_screen *) pscreen;
|
|
|
|
const unsigned TIMESTAMP = 0x2358;
|
|
|
|
uint64_t result;
|
|
|
|
|
2018-09-28 15:45:04 +01:00
|
|
|
iris_reg_read(screen->bufmgr, TIMESTAMP | 1, &result);
|
2018-09-28 14:42:51 +01:00
|
|
|
|
2021-04-05 21:19:39 +01:00
|
|
|
result = intel_device_info_timebase_scale(&screen->devinfo, result);
|
2018-09-29 09:47:01 +01:00
|
|
|
result &= (1ull << TIMESTAMP_BITS) - 1;
|
2018-09-28 14:42:51 +01:00
|
|
|
|
|
|
|
return result;
|
2017-11-24 07:15:14 +00:00
|
|
|
}
|
|
|
|
|
2020-03-06 13:58:37 +00:00
|
|
|
void
|
|
|
|
iris_screen_destroy(struct iris_screen *screen)
|
2017-11-24 07:15:14 +00:00
|
|
|
{
|
2020-10-27 22:56:06 +00:00
|
|
|
iris_destroy_screen_measure(screen);
|
2020-08-15 06:26:05 +01:00
|
|
|
glsl_type_singleton_decref();
|
2018-04-19 20:52:51 +01:00
|
|
|
iris_bo_unreference(screen->workaround_bo);
|
2020-03-06 13:58:37 +00:00
|
|
|
u_transfer_helper_destroy(screen->base.transfer_helper);
|
2020-03-06 11:34:23 +00:00
|
|
|
iris_bufmgr_unref(screen->bufmgr);
|
2018-12-20 23:54:06 +00:00
|
|
|
disk_cache_destroy(screen->disk_cache);
|
2020-05-02 14:46:47 +01:00
|
|
|
close(screen->winsys_fd);
|
2017-11-24 07:15:14 +00:00
|
|
|
ralloc_free(screen);
|
|
|
|
}
|
|
|
|
|
2020-03-06 13:58:37 +00:00
|
|
|
static void
|
|
|
|
iris_screen_unref(struct pipe_screen *pscreen)
|
|
|
|
{
|
|
|
|
iris_pscreen_unref(pscreen);
|
|
|
|
}
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
static void
|
|
|
|
iris_query_memory_info(struct pipe_screen *pscreen,
|
|
|
|
struct pipe_memory_info *info)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static const void *
|
|
|
|
iris_get_compiler_options(struct pipe_screen *pscreen,
|
|
|
|
enum pipe_shader_ir ir,
|
|
|
|
enum pipe_shader_type pstage)
|
|
|
|
{
|
|
|
|
struct iris_screen *screen = (struct iris_screen *) pscreen;
|
|
|
|
gl_shader_stage stage = stage_from_pipe(pstage);
|
|
|
|
assert(ir == PIPE_SHADER_IR_NIR);
|
|
|
|
|
|
|
|
return screen->compiler->glsl_compiler_options[stage].NirOptions;
|
|
|
|
}
|
|
|
|
|
2019-05-21 20:06:02 +01:00
|
|
|
static struct disk_cache *
|
|
|
|
iris_get_disk_shader_cache(struct pipe_screen *pscreen)
|
|
|
|
{
|
|
|
|
struct iris_screen *screen = (struct iris_screen *) pscreen;
|
|
|
|
return screen->disk_cache;
|
|
|
|
}
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
static int
|
2020-04-20 15:09:42 +01:00
|
|
|
iris_getparam(int fd, int param, int *value)
|
2017-11-24 07:15:14 +00:00
|
|
|
{
|
|
|
|
struct drm_i915_getparam gp = { .param = param, .value = value };
|
|
|
|
|
2020-04-20 15:09:42 +01:00
|
|
|
if (ioctl(fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
|
2017-11-24 07:15:14 +00:00
|
|
|
return -errno;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
2020-04-20 15:09:42 +01:00
|
|
|
iris_getparam_integer(int fd, int param)
|
2017-11-24 07:15:14 +00:00
|
|
|
{
|
|
|
|
int value = -1;
|
|
|
|
|
2020-04-20 15:09:42 +01:00
|
|
|
if (iris_getparam(fd, param, &value) == 0)
|
2017-11-24 07:15:14 +00:00
|
|
|
return value;
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2021-03-03 21:49:18 +00:00
|
|
|
static const struct intel_l3_config *
|
2021-04-05 21:19:39 +01:00
|
|
|
iris_get_default_l3_config(const struct intel_device_info *devinfo,
|
2020-01-17 17:37:31 +00:00
|
|
|
bool compute)
|
|
|
|
{
|
|
|
|
bool wants_dc_cache = true;
|
|
|
|
bool has_slm = compute;
|
2021-03-03 21:49:18 +00:00
|
|
|
const struct intel_l3_weights w =
|
|
|
|
intel_get_default_l3_weights(devinfo, wants_dc_cache, has_slm);
|
|
|
|
return intel_get_l3_config(devinfo, w);
|
2020-01-17 17:37:31 +00:00
|
|
|
}
|
|
|
|
|
2018-01-19 23:41:46 +00:00
|
|
|
static void
|
|
|
|
iris_shader_debug_log(void *data, const char *fmt, ...)
|
|
|
|
{
|
2018-01-20 10:01:07 +00:00
|
|
|
struct pipe_debug_callback *dbg = data;
|
|
|
|
unsigned id = 0;
|
2018-01-19 23:41:46 +00:00
|
|
|
va_list args;
|
|
|
|
|
|
|
|
if (!dbg->debug_message)
|
|
|
|
return;
|
|
|
|
|
|
|
|
va_start(args, fmt);
|
2018-01-20 10:01:07 +00:00
|
|
|
dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
|
2018-01-19 23:41:46 +00:00
|
|
|
va_end(args);
|
|
|
|
}
|
|
|
|
|
2018-07-05 10:53:54 +01:00
|
|
|
static void
|
|
|
|
iris_shader_perf_log(void *data, const char *fmt, ...)
|
|
|
|
{
|
|
|
|
struct pipe_debug_callback *dbg = data;
|
|
|
|
unsigned id = 0;
|
|
|
|
va_list args;
|
2019-04-16 06:34:15 +01:00
|
|
|
va_start(args, fmt);
|
2018-07-05 10:53:54 +01:00
|
|
|
|
2020-09-14 17:49:43 +01:00
|
|
|
if (INTEL_DEBUG & DEBUG_PERF) {
|
2019-04-16 06:34:15 +01:00
|
|
|
va_list args_copy;
|
|
|
|
va_copy(args_copy, args);
|
|
|
|
vfprintf(stderr, fmt, args_copy);
|
|
|
|
va_end(args_copy);
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dbg->debug_message) {
|
|
|
|
dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
|
|
|
|
}
|
2018-07-05 10:53:54 +01:00
|
|
|
|
|
|
|
va_end(args);
|
|
|
|
}
|
|
|
|
|
2020-04-29 21:53:50 +01:00
|
|
|
static void
|
|
|
|
iris_detect_kernel_features(struct iris_screen *screen)
|
|
|
|
{
|
|
|
|
/* Kernel 5.2+ */
|
2021-03-03 21:49:18 +00:00
|
|
|
if (intel_gem_supports_syncobj_wait(screen->fd))
|
2020-04-29 21:53:50 +01:00
|
|
|
screen->kernel_features |= KERNEL_HAS_WAIT_FOR_SUBMIT;
|
|
|
|
}
|
|
|
|
|
2019-12-24 00:41:10 +00:00
|
|
|
static bool
|
|
|
|
iris_init_identifier_bo(struct iris_screen *screen)
|
|
|
|
{
|
|
|
|
void *bo_map;
|
|
|
|
|
|
|
|
bo_map = iris_bo_map(NULL, screen->workaround_bo, MAP_READ | MAP_WRITE);
|
|
|
|
if (!bo_map)
|
|
|
|
return false;
|
|
|
|
|
|
|
|
screen->workaround_bo->kflags |= EXEC_OBJECT_CAPTURE;
|
|
|
|
screen->workaround_address = (struct iris_address) {
|
|
|
|
.bo = screen->workaround_bo,
|
|
|
|
.offset = ALIGN(
|
|
|
|
intel_debug_write_identifiers(bo_map, 4096, "Iris") + 8, 8),
|
|
|
|
};
|
|
|
|
|
|
|
|
iris_bo_unmap(screen->workaround_bo);
|
|
|
|
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
struct pipe_screen *
|
2019-04-19 06:13:41 +01:00
|
|
|
iris_screen_create(int fd, const struct pipe_screen_config *config)
|
2017-11-24 07:15:14 +00:00
|
|
|
{
|
2021-02-25 06:11:12 +00:00
|
|
|
/* Here are the i915 features we need for Iris (in chronological order) :
|
2020-04-20 15:09:42 +01:00
|
|
|
* - I915_PARAM_HAS_EXEC_NO_RELOC (3.10)
|
|
|
|
* - I915_PARAM_HAS_EXEC_HANDLE_LUT (3.10)
|
|
|
|
* - I915_PARAM_HAS_EXEC_BATCH_FIRST (4.13)
|
|
|
|
* - I915_PARAM_HAS_EXEC_FENCE_ARRAY (4.14)
|
|
|
|
* - I915_PARAM_HAS_CONTEXT_ISOLATION (4.16)
|
|
|
|
*
|
|
|
|
* Checking the last feature availability will include all previous ones.
|
|
|
|
*/
|
2020-07-10 08:46:53 +01:00
|
|
|
if (iris_getparam_integer(fd, I915_PARAM_HAS_CONTEXT_ISOLATION) <= 0) {
|
2020-04-20 15:09:42 +01:00
|
|
|
debug_error("Kernel is too old for Iris. Consider upgrading to kernel v4.16.\n");
|
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
|
|
|
|
if (!screen)
|
|
|
|
return NULL;
|
|
|
|
|
2021-04-05 23:59:35 +01:00
|
|
|
if (!intel_get_device_info_from_fd(fd, &screen->devinfo))
|
2017-11-24 07:15:14 +00:00
|
|
|
return NULL;
|
2019-07-24 23:21:36 +01:00
|
|
|
screen->pci_id = screen->devinfo.chipset_id;
|
|
|
|
screen->no_hw = screen->devinfo.no_hw;
|
2017-11-24 07:15:14 +00:00
|
|
|
|
2020-03-06 13:58:37 +00:00
|
|
|
p_atomic_set(&screen->refcount, 1);
|
|
|
|
|
2021-03-29 22:41:58 +01:00
|
|
|
if (screen->devinfo.ver < 8 || screen->devinfo.is_cherryview)
|
2019-01-14 08:25:23 +00:00
|
|
|
return NULL;
|
|
|
|
|
2019-08-28 12:46:16 +01:00
|
|
|
bool bo_reuse = false;
|
|
|
|
int bo_reuse_mode = driQueryOptioni(config->options, "bo_reuse");
|
|
|
|
switch (bo_reuse_mode) {
|
|
|
|
case DRI_CONF_BO_REUSE_DISABLED:
|
|
|
|
break;
|
|
|
|
case DRI_CONF_BO_REUSE_ALL:
|
|
|
|
bo_reuse = true;
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
|
2020-03-06 11:34:23 +00:00
|
|
|
screen->bufmgr = iris_bufmgr_get_for_fd(&screen->devinfo, fd, bo_reuse);
|
2017-11-24 07:15:14 +00:00
|
|
|
if (!screen->bufmgr)
|
|
|
|
return NULL;
|
|
|
|
|
2020-03-06 11:34:23 +00:00
|
|
|
screen->fd = iris_bufmgr_get_fd(screen->bufmgr);
|
2020-05-02 14:46:47 +01:00
|
|
|
screen->winsys_fd = fd;
|
2020-03-06 11:34:23 +00:00
|
|
|
|
|
|
|
if (getenv("INTEL_NO_HW") != NULL)
|
|
|
|
screen->no_hw = true;
|
|
|
|
|
2018-04-19 20:52:51 +01:00
|
|
|
screen->workaround_bo =
|
2021-06-03 00:16:53 +01:00
|
|
|
iris_bo_alloc(screen->bufmgr, "workaround", 4096, 1,
|
|
|
|
IRIS_MEMZONE_OTHER, 0);
|
2018-04-19 20:52:51 +01:00
|
|
|
if (!screen->workaround_bo)
|
|
|
|
return NULL;
|
|
|
|
|
2019-12-24 00:41:10 +00:00
|
|
|
if (!iris_init_identifier_bo(screen))
|
|
|
|
return NULL;
|
2020-02-21 16:06:18 +00:00
|
|
|
|
2018-01-20 09:12:12 +00:00
|
|
|
brw_process_intel_debug_variable();
|
|
|
|
|
2019-04-19 06:29:27 +01:00
|
|
|
screen->driconf.dual_color_blend_by_location =
|
|
|
|
driQueryOptionb(config->options, "dual_color_blend_by_location");
|
2019-09-05 09:52:17 +01:00
|
|
|
screen->driconf.disable_throttling =
|
|
|
|
driQueryOptionb(config->options, "disable_throttling");
|
2019-09-08 05:18:51 +01:00
|
|
|
screen->driconf.always_flush_cache =
|
|
|
|
driQueryOptionb(config->options, "always_flush_cache");
|
2019-04-19 06:29:27 +01:00
|
|
|
|
2018-11-22 10:55:27 +00:00
|
|
|
screen->precompile = env_var_as_boolean("shader_precompile", true);
|
|
|
|
|
2019-02-12 06:36:45 +00:00
|
|
|
isl_device_init(&screen->isl_dev, &screen->devinfo, false);
|
2017-11-24 07:15:14 +00:00
|
|
|
|
|
|
|
screen->compiler = brw_compiler_create(screen, &screen->devinfo);
|
2018-01-19 23:41:46 +00:00
|
|
|
screen->compiler->shader_debug_log = iris_shader_debug_log;
|
2018-07-05 10:53:54 +01:00
|
|
|
screen->compiler->shader_perf_log = iris_shader_perf_log;
|
2018-11-09 20:09:50 +00:00
|
|
|
screen->compiler->supports_pull_constants = false;
|
2019-05-28 23:33:58 +01:00
|
|
|
screen->compiler->supports_shader_constants = true;
|
2019-11-18 21:40:09 +00:00
|
|
|
screen->compiler->compact_params = false;
|
2021-03-29 22:41:58 +01:00
|
|
|
screen->compiler->indirect_ubos_use_sampler = screen->devinfo.ver < 12;
|
2017-11-24 07:15:14 +00:00
|
|
|
|
2020-01-17 17:37:31 +00:00
|
|
|
screen->l3_config_3d = iris_get_default_l3_config(&screen->devinfo, false);
|
|
|
|
screen->l3_config_cs = iris_get_default_l3_config(&screen->devinfo, true);
|
|
|
|
|
2018-12-20 23:54:06 +00:00
|
|
|
iris_disk_cache_init(screen);
|
|
|
|
|
2018-07-06 19:29:51 +01:00
|
|
|
slab_create_parent(&screen->transfer_pool,
|
|
|
|
sizeof(struct iris_transfer), 64);
|
|
|
|
|
2021-04-05 21:19:39 +01:00
|
|
|
screen->subslice_total = intel_device_info_subslice_total(&screen->devinfo);
|
2018-07-27 05:59:20 +01:00
|
|
|
assert(screen->subslice_total >= 1);
|
|
|
|
|
2020-04-29 21:53:50 +01:00
|
|
|
iris_detect_kernel_features(screen);
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
struct pipe_screen *pscreen = &screen->base;
|
|
|
|
|
2018-11-07 11:50:02 +00:00
|
|
|
iris_init_screen_fence_functions(pscreen);
|
2017-11-24 07:15:14 +00:00
|
|
|
iris_init_screen_resource_functions(pscreen);
|
2020-10-27 22:56:06 +00:00
|
|
|
iris_init_screen_measure(screen);
|
2017-11-24 07:15:14 +00:00
|
|
|
|
2020-03-06 13:58:37 +00:00
|
|
|
pscreen->destroy = iris_screen_unref;
|
2017-11-24 07:15:14 +00:00
|
|
|
pscreen->get_name = iris_get_name;
|
|
|
|
pscreen->get_vendor = iris_get_vendor;
|
|
|
|
pscreen->get_device_vendor = iris_get_device_vendor;
|
|
|
|
pscreen->get_param = iris_get_param;
|
|
|
|
pscreen->get_shader_param = iris_get_shader_param;
|
|
|
|
pscreen->get_compute_param = iris_get_compute_param;
|
|
|
|
pscreen->get_paramf = iris_get_paramf;
|
|
|
|
pscreen->get_compiler_options = iris_get_compiler_options;
|
2020-03-26 16:04:19 +00:00
|
|
|
pscreen->get_device_uuid = iris_get_device_uuid;
|
|
|
|
pscreen->get_driver_uuid = iris_get_driver_uuid;
|
2019-05-21 20:06:02 +01:00
|
|
|
pscreen->get_disk_shader_cache = iris_get_disk_shader_cache;
|
2017-11-24 07:15:14 +00:00
|
|
|
pscreen->is_format_supported = iris_is_format_supported;
|
|
|
|
pscreen->context_create = iris_create_context;
|
|
|
|
pscreen->flush_frontbuffer = iris_flush_frontbuffer;
|
|
|
|
pscreen->get_timestamp = iris_get_timestamp;
|
|
|
|
pscreen->query_memory_info = iris_query_memory_info;
|
2019-04-22 19:43:12 +01:00
|
|
|
pscreen->get_driver_query_group_info = iris_get_monitor_group_info;
|
|
|
|
pscreen->get_driver_query_info = iris_get_monitor_info;
|
2017-11-24 07:15:14 +00:00
|
|
|
|
2020-05-15 11:16:51 +01:00
|
|
|
genX_call(&screen->devinfo, init_screen_state, screen);
|
2020-11-11 06:59:46 +00:00
|
|
|
|
2020-08-15 06:26:05 +01:00
|
|
|
glsl_type_singleton_init_or_ref();
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
return pscreen;
|
|
|
|
}
|