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intel: Use a system value for gl_FragCoord 

It's kind-of an anomaly that the Intel drivers are still treating
gl_FragCoord as an input.  It also makes zero sense because we have to
special-case it in the back-end.

Because ANV is the only user of nir_lower_wpos_center, we go ahead and
just update it to look for nir_intrinsic_load_frag_coord as part of this
patch.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jason Ekstrand 2019-07-18 09:59:44 -05:00
parent 44268b1c72
commit 4bb6e6817e
11 changed files with 19 additions and 52 deletions
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16
src/compiler/nir/nir_lower_wpos_center.c
View File

@ -80,19 +80,9 @@ lower_wpos_center_block(nir_builder *b, nir_block *block,
nir_foreach_instr(instr, block) {
if (instr->type == nir_instr_type_intrinsic) {
nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
if (intr->intrinsic == nir_intrinsic_load_deref) {
nir_deref_instr *deref = nir_src_as_deref(intr->src[0]);
if (deref->mode != nir_var_shader_in)
continue;
nir_variable *var = nir_deref_instr_get_variable(deref);
if (var->data.location == VARYING_SLOT_POS) {
/* gl_FragCoord should not have array/struct derefs: */
assert(deref->deref_type == nir_deref_type_var);
update_fragcoord(b, intr, for_sample_shading);
progress = true;
}
if (intr->intrinsic == nir_intrinsic_load_frag_coord) {
update_fragcoord(b, intr, for_sample_shading);
progress = true;
}
}
}

1
src/gallium/drivers/iris/iris_screen.c
View File

@ -190,6 +190,7 @@ iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
case PIPE_CAP_LOAD_CONSTBUF:
case PIPE_CAP_NIR_COMPACT_ARRAYS:
case PIPE_CAP_DRAW_PARAMETERS:
case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
case PIPE_CAP_COMPUTE_SHADER_DERIVATIVES:
case PIPE_CAP_INVALIDATE_BUFFER:

9
src/intel/blorp/blorp_blit.c
View File

@ -60,9 +60,6 @@ struct brw_blorp_blit_vars {
nir_variable *v_dst_offset;
nir_variable *v_src_inv_size;
/* gl_FragCoord */
nir_variable *frag_coord;
/* gl_FragColor */
nir_variable *color_out;
};
@ -84,10 +81,6 @@ brw_blorp_blit_vars_init(nir_builder *b, struct brw_blorp_blit_vars *v,
#undef LOAD_INPUT
v->frag_coord = nir_variable_create(b->shader, nir_var_shader_in,
glsl_vec4_type(), "gl_FragCoord");
v->frag_coord->data.location = VARYING_SLOT_POS;
v->color_out = nir_variable_create(b->shader, nir_var_shader_out,
glsl_vec4_type(), "gl_FragColor");
v->color_out->data.location = FRAG_RESULT_COLOR;
@ -98,7 +91,7 @@ blorp_blit_get_frag_coords(nir_builder *b,
const struct brw_blorp_blit_prog_key *key,
struct brw_blorp_blit_vars *v)
{
nir_ssa_def *coord = nir_f2i32(b, nir_load_var(b, v->frag_coord));
nir_ssa_def *coord = nir_f2i32(b, nir_load_frag_coord(b));
/* Account for destination surface intratile offset
*

9
src/intel/blorp/blorp_clear.c
View File

@ -70,12 +70,7 @@ blorp_params_get_clear_kernel(struct blorp_batch *batch,
nir_ssa_def *color = nir_load_var(&b, v_color);
if (clear_rgb_as_red) {
nir_variable *frag_coord =
nir_variable_create(b.shader, nir_var_shader_in,
glsl_vec4_type(), "gl_FragCoord");
frag_coord->data.location = VARYING_SLOT_POS;
nir_ssa_def *pos = nir_f2i32(&b, nir_load_var(&b, frag_coord));
nir_ssa_def *pos = nir_f2i32(&b, nir_load_frag_coord(&b));
nir_ssa_def *comp = nir_umod(&b, nir_channel(&b, pos, 0),
nir_imm_int(&b, 3));
nir_ssa_def *color_component =
@ -976,7 +971,7 @@ blorp_params_get_mcs_partial_resolve_kernel(struct blorp_batch *batch,
/* Do an MCS fetch and check if it is equal to the magic clear value */
nir_ssa_def *mcs =
blorp_nir_txf_ms_mcs(&b, nir_f2i32(&b, blorp_nir_frag_coord(&b)),
blorp_nir_txf_ms_mcs(&b, nir_f2i32(&b, nir_load_frag_coord(&b)),
nir_load_layer_id(&b));
nir_ssa_def *is_clear =
blorp_nir_mcs_is_clear_color(&b, mcs, blorp_key.num_samples);

12
src/intel/blorp/blorp_nir_builder.h
View File

@ -36,18 +36,6 @@ blorp_nir_init_shader(nir_builder *b,
b->shader->info.fs.origin_upper_left = true;
}
static inline nir_ssa_def *
blorp_nir_frag_coord(nir_builder *b)
{
nir_variable *frag_coord =
nir_variable_create(b->shader, nir_var_shader_in,
glsl_vec4_type(), "gl_FragCoord");
frag_coord->data.location = VARYING_SLOT_POS;
return nir_load_var(b, frag_coord);
}
static inline nir_ssa_def *
blorp_nir_txf_ms_mcs(nir_builder *b, nir_ssa_def *xy_pos, nir_ssa_def *layer)
{

8
src/intel/compiler/brw_fs.cpp
View File

@ -6822,7 +6822,7 @@ fs_visitor::setup_fs_payload_gen6()
assert(devinfo->gen >= 6);
prog_data->uses_src_depth = prog_data->uses_src_w =
(nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
(nir->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD)) != 0;
prog_data->uses_sample_mask =
(nir->info.system_values_read & SYSTEM_BIT_SAMPLE_MASK_IN) != 0;
@ -7601,6 +7601,7 @@ fs_visitor::run_fs(bool allow_spilling, bool do_rep_send)
emit_shader_time_begin();
if (nir->info.inputs_read > 0 ||
(nir->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD)) ||
(nir->info.outputs_read > 0 && !wm_key->coherent_fb_fetch)) {
if (devinfo->gen < 6)
emit_interpolation_setup_gen4();
@ -7707,10 +7708,7 @@ is_used_in_not_interp_frag_coord(nir_ssa_def *def)
return true;
nir_intrinsic_instr *intrin = nir_instr_as_intrinsic(src->parent_instr);
if (intrin->intrinsic != nir_intrinsic_load_interpolated_input)
return true;
if (nir_intrinsic_base(intrin) != VARYING_SLOT_POS)
if (intrin->intrinsic != nir_intrinsic_load_frag_coord)
return true;
}

9
src/intel/compiler/brw_fs_nir.cpp
View File

@ -3829,12 +3829,11 @@ fs_visitor::nir_emit_fs_intrinsic(const fs_builder &bld,
break;
}
case nir_intrinsic_load_interpolated_input: {
if (nir_intrinsic_base(instr) == VARYING_SLOT_POS) {
emit_fragcoord_interpolation(dest);
break;
}
case nir_intrinsic_load_frag_coord:
emit_fragcoord_interpolation(dest);
break;
case nir_intrinsic_load_interpolated_input: {
assert(instr->src[0].ssa &&
instr->src[0].ssa->parent_instr->type == nir_instr_type_intrinsic);
nir_intrinsic_instr *bary_intrinsic =

2
src/intel/compiler/brw_wm_iz.cpp
View File

@ -145,7 +145,7 @@ void fs_visitor::setup_fs_payload_gen4()
payload.subspan_coord_reg[0] = reg++;
prog_data->uses_src_depth =
(nir->info.inputs_read & (1 << VARYING_SLOT_POS)) != 0;
(nir->info.system_values_read & (1ull << SYSTEM_VALUE_FRAG_COORD)) != 0;
if (wm_iz_table[lookup].sd_present || prog_data->uses_src_depth ||
kill_stats_promoted_workaround) {
payload.source_depth_reg[0] = reg;

3
src/intel/vulkan/anv_pipeline.c
View File

@ -167,6 +167,7 @@ anv_shader_compile_to_nir(struct anv_device *device,
};
struct spirv_to_nir_options spirv_options = {
.lower_workgroup_access_to_offsets = true,
.frag_coord_is_sysval = true,
.caps = {
.demote_to_helper_invocation = true,
.derivative_group = true,
@ -652,7 +653,7 @@ anv_pipeline_lower_nir(struct anv_pipeline *pipeline,
if (nir->info.stage == MESA_SHADER_FRAGMENT) {
NIR_PASS_V(nir, nir_lower_wpos_center, pipeline->sample_shading_enable);
NIR_PASS_V(nir, nir_lower_input_attachments, false);
NIR_PASS_V(nir, nir_lower_input_attachments, true);
}
NIR_PASS_V(nir, anv_nir_lower_ycbcr_textures, layout);

1
src/mesa/drivers/dri/i965/brw_context.c
View File

@ -621,6 +621,7 @@ brw_initialize_context_constants(struct brw_context *brw)
if (devinfo->gen >= 5 || devinfo->is_g4x)
ctx->Const.MaxClipPlanes = 8;
ctx->Const.GLSLFragCoordIsSysVal = true;
ctx->Const.GLSLTessLevelsAsInputs = true;
ctx->Const.PrimitiveRestartForPatches = true;

1
src/mesa/drivers/dri/i965/brw_program.c
View File

@ -262,6 +262,7 @@ brwProgramStringNotify(struct gl_context *ctx,
if (newFP == curFP)
brw->ctx.NewDriverState |= BRW_NEW_FRAGMENT_PROGRAM;
_mesa_program_fragment_position_to_sysval(&newFP->program);
newFP->id = get_new_program_id(brw->screen);
prog->nir = brw_create_nir(brw, NULL, prog, MESA_SHADER_FRAGMENT, true);