2017-11-24 07:15:14 +00:00
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/*
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* Copyright © 2017 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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#include <stdio.h>
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#include <errno.h>
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#include <sys/ioctl.h>
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#include "pipe/p_defines.h"
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#include "pipe/p_state.h"
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#include "pipe/p_context.h"
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#include "pipe/p_screen.h"
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#include "util/u_inlines.h"
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#include "util/u_format.h"
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#include "util/u_upload_mgr.h"
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#include "util/ralloc.h"
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#include "drm-uapi/i915_drm.h"
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#include "iris_context.h"
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2018-01-12 06:18:54 +00:00
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#include "iris_pipe.h"
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2017-11-24 07:15:14 +00:00
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#include "iris_resource.h"
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#include "iris_screen.h"
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#include "intel/compiler/brw_compiler.h"
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static void
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iris_flush_frontbuffer(struct pipe_screen *_screen,
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struct pipe_resource *resource,
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unsigned level, unsigned layer,
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void *context_private, struct pipe_box *box)
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{
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}
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static const char *
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iris_get_vendor(struct pipe_screen *pscreen)
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{
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return "Mesa Project";
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}
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static const char *
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iris_get_device_vendor(struct pipe_screen *pscreen)
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{
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return "Intel";
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}
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static const char *
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iris_get_name(struct pipe_screen *pscreen)
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{
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struct iris_screen *screen = (struct iris_screen *)pscreen;
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const char *chipset;
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switch (screen->pci_id) {
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#undef CHIPSET
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#define CHIPSET(id, symbol, str) case id: chipset = str; break;
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#include "pci_ids/i965_pci_ids.h"
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default:
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chipset = "Unknown Intel Chipset";
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break;
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}
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return &chipset[9];
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}
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static int
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iris_get_param(struct pipe_screen *pscreen, enum pipe_cap param)
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{
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struct iris_screen *screen = (struct iris_screen *)pscreen;
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switch (param) {
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case PIPE_CAP_NPOT_TEXTURES:
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case PIPE_CAP_ANISOTROPIC_FILTER:
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case PIPE_CAP_POINT_SPRITE:
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case PIPE_CAP_OCCLUSION_QUERY:
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case PIPE_CAP_QUERY_TIME_ELAPSED:
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case PIPE_CAP_TEXTURE_SWIZZLE:
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2018-06-24 01:30:18 +01:00
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE:
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_BLEND_EQUATION_SEPARATE:
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case PIPE_CAP_SM3:
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case PIPE_CAP_PRIMITIVE_RESTART:
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case PIPE_CAP_INDEP_BLEND_ENABLE:
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case PIPE_CAP_INDEP_BLEND_FUNC:
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case PIPE_CAP_RGB_OVERRIDE_DST_ALPHA_BLEND:
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case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT:
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case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER:
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case PIPE_CAP_DEPTH_CLIP_DISABLE:
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case PIPE_CAP_SHADER_STENCIL_EXPORT:
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case PIPE_CAP_TGSI_INSTANCEID:
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case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR:
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case PIPE_CAP_MIXED_COLORBUFFER_FORMATS:
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case PIPE_CAP_SEAMLESS_CUBE_MAP:
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case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE:
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case PIPE_CAP_CONDITIONAL_RENDER:
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case PIPE_CAP_TEXTURE_BARRIER:
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case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME:
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case PIPE_CAP_VERTEX_COLOR_UNCLAMPED:
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case PIPE_CAP_COMPUTE:
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case PIPE_CAP_START_INSTANCE:
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case PIPE_CAP_QUERY_TIMESTAMP:
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case PIPE_CAP_TEXTURE_MULTISAMPLE:
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case PIPE_CAP_CUBE_MAP_ARRAY:
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case PIPE_CAP_TEXTURE_BUFFER_OBJECTS:
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case PIPE_CAP_QUERY_PIPELINE_STATISTICS:
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case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT:
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case PIPE_CAP_TEXTURE_QUERY_LOD:
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case PIPE_CAP_SAMPLE_SHADING:
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case PIPE_CAP_TEXTURE_GATHER_OFFSETS:
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case PIPE_CAP_DRAW_INDIRECT:
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case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES:
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case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT:
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case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE:
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case PIPE_CAP_ACCELERATED:
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case PIPE_CAP_UMA:
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case PIPE_CAP_CONDITIONAL_RENDER_INVERTED:
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case PIPE_CAP_CLIP_HALFZ:
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2018-02-10 07:38:08 +00:00
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case PIPE_CAP_TGSI_TEXCOORD:
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2018-04-26 07:47:06 +01:00
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case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS:
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case PIPE_CAP_DOUBLES:
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case PIPE_CAP_INT64:
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case PIPE_CAP_INT64_DIVMOD:
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case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY:
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case PIPE_CAP_SAMPLER_VIEW_TARGET:
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case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR:
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case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS:
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case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT:
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case PIPE_CAP_CULL_DISTANCE:
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2018-06-06 10:16:52 +01:00
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case PIPE_CAP_PACKED_UNIFORMS:
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2018-06-08 09:28:16 +01:00
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case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION:
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2018-06-18 19:30:23 +01:00
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case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET:
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2018-07-24 22:49:13 +01:00
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case PIPE_CAP_TEXTURE_FLOAT_LINEAR:
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case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR:
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case PIPE_CAP_POLYGON_OFFSET_CLAMP:
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2017-11-24 07:15:14 +00:00
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return true;
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case PIPE_CAP_FRAGMENT_COLOR_CLAMPED:
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case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS:
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case PIPE_CAP_VERTEX_COLOR_CLAMPED:
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case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION:
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case PIPE_CAP_USER_VERTEX_BUFFERS:
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case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY:
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case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY:
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case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY:
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case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK:
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case PIPE_CAP_FAKE_SW_MSAA:
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case PIPE_CAP_VERTEXID_NOBASE:
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2018-05-03 05:52:26 +01:00
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case PIPE_CAP_FENCE_SIGNAL:
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case PIPE_CAP_CONSTBUF0_FLAGS:
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case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES:
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case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES:
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case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES:
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case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES:
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case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS:
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case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE:
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2018-06-20 05:46:56 +01:00
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case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS:
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2018-06-24 07:52:43 +01:00
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case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT:
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case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER:
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2018-06-26 08:17:36 +01:00
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case PIPE_CAP_GENERATE_MIPMAP:
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2018-07-16 23:36:34 +01:00
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case PIPE_CAP_FORCE_PERSAMPLE_INTERP:
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2017-11-24 07:15:14 +00:00
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return false;
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2018-06-24 01:30:18 +01:00
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case PIPE_CAP_TEXTURE_MIRROR_CLAMP:
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/* Intel GPUs don't support PIPE_TEX_WRAP_MIRROR_CLAMP or
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* PIPE_TEX_WRAP_MIRROR_CLAMP_TO_BORDER.
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*/
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return false;
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS:
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return 1;
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case PIPE_CAP_MAX_RENDER_TARGETS:
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return BRW_MAX_DRAW_BUFFERS;
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case PIPE_CAP_MAX_TEXTURE_2D_LEVELS:
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case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS:
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return 15; /* 16384x16384 */
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case PIPE_CAP_MAX_TEXTURE_3D_LEVELS:
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return 12; /* 2048x2048 */
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case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS:
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return 4;
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case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS:
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return 2048;
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case PIPE_CAP_MIN_TEXEL_OFFSET:
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return -8;
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case PIPE_CAP_MAX_TEXEL_OFFSET:
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return 7;
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case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS:
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return BRW_MAX_SOL_BINDINGS / IRIS_MAX_SOL_BUFFERS;
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case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS:
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return BRW_MAX_SOL_BINDINGS;
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case PIPE_CAP_GLSL_FEATURE_LEVEL:
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return 460;
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2018-06-20 05:46:56 +01:00
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case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY:
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return 140;
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT:
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/* 3DSTATE_CONSTANT_XS requires the start of UBOs to be 32B aligned */
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return 32;
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2018-07-25 01:03:48 +01:00
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case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT:
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/* Choose a cacheline (64 bytes) so that we can safely have the CPU and
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* GPU writing the same SSBO on non-coherent systems (Atom CPUs). With
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* UBOs, the GPU never writes, so there's no problem. For an SSBO, the
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* GPU and the CPU can be updating disjoint regions of the buffer
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* simultaneously and that will break if the regions overlap the same
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* cacheline.
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*/
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return 64;
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT:
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return 64; // XXX: ?
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case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT:
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2018-07-25 01:02:25 +01:00
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return 16;
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER:
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return true; // XXX: ?????
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case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE:
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return 1 << 27; /* 128MB */
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case PIPE_CAP_MAX_VIEWPORTS:
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return 16;
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case PIPE_CAP_ENDIANNESS:
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return PIPE_ENDIAN_LITTLE;
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case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES:
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return 256;
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case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS:
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return 128;
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case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS:
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2018-07-26 07:33:16 +01:00
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return 4;
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_TEXTURE_GATHER_SM5:
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2018-07-26 07:33:16 +01:00
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return 1;
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET:
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return -32;
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case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET:
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return 31;
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case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION:
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case PIPE_CAP_MAX_VERTEX_STREAMS:
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return 4;
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case PIPE_CAP_VENDOR_ID:
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return 0x8086;
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case PIPE_CAP_DEVICE_ID:
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return screen->pci_id;
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case PIPE_CAP_VIDEO_MEMORY:
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return 0xffffffff; // XXX: bogus
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case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE:
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return 2048;
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2018-07-19 05:08:32 +01:00
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case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS:
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return 32;
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2017-11-24 07:15:14 +00:00
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case PIPE_CAP_MULTISAMPLE_Z_RESOLVE:
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case PIPE_CAP_RESOURCE_FROM_USER_MEMORY:
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case PIPE_CAP_DEVICE_RESET_STATUS_QUERY:
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case PIPE_CAP_DEPTH_BOUNDS_TEST:
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case PIPE_CAP_TGSI_TXQS:
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case PIPE_CAP_SHAREABLE_SHADERS:
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case PIPE_CAP_CLEAR_TEXTURE:
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case PIPE_CAP_DRAW_PARAMETERS:
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case PIPE_CAP_TGSI_PACK_HALF_FLOAT:
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case PIPE_CAP_MULTI_DRAW_INDIRECT:
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case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS:
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case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL:
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case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL:
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case PIPE_CAP_INVALIDATE_BUFFER:
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case PIPE_CAP_STRING_MARKER:
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case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS:
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case PIPE_CAP_QUERY_BUFFER_OBJECT:
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case PIPE_CAP_QUERY_MEMORY_INFO:
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case PIPE_CAP_PCI_GROUP:
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case PIPE_CAP_PCI_BUS:
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case PIPE_CAP_PCI_DEVICE:
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case PIPE_CAP_PCI_FUNCTION:
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case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES:
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case PIPE_CAP_TGSI_VOTE:
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case PIPE_CAP_MAX_WINDOW_RECTANGLES:
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case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED:
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case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS:
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case PIPE_CAP_MIXED_COLOR_DEPTH_BITS:
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case PIPE_CAP_TGSI_ARRAY_COMPONENTS:
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case PIPE_CAP_TGSI_CAN_READ_OUTPUTS:
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case PIPE_CAP_NATIVE_FENCE_FD:
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case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY:
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case PIPE_CAP_TGSI_FS_FBFETCH:
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case PIPE_CAP_TGSI_MUL_ZERO_WINS:
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case PIPE_CAP_TGSI_TEX_TXF_LZ:
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case PIPE_CAP_TGSI_CLOCK:
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case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE:
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case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE:
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|
|
case PIPE_CAP_TGSI_BALLOT:
|
|
|
|
case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT:
|
|
|
|
case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX:
|
|
|
|
case PIPE_CAP_POST_DEPTH_COVERAGE:
|
|
|
|
case PIPE_CAP_BINDLESS_TEXTURE:
|
|
|
|
case PIPE_CAP_NIR_SAMPLERS_AS_DEREF:
|
|
|
|
case PIPE_CAP_QUERY_SO_OVERFLOW:
|
|
|
|
case PIPE_CAP_MEMOBJ:
|
|
|
|
case PIPE_CAP_LOAD_CONSTBUF:
|
|
|
|
case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS:
|
|
|
|
case PIPE_CAP_TILE_RASTER_ORDER:
|
|
|
|
case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES:
|
|
|
|
case PIPE_CAP_CONTEXT_PRIORITY_MASK:
|
|
|
|
// XXX: TODO: fill these out
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static float
|
|
|
|
iris_get_paramf(struct pipe_screen *pscreen, enum pipe_capf param)
|
|
|
|
{
|
|
|
|
switch (param) {
|
|
|
|
case PIPE_CAPF_MAX_LINE_WIDTH:
|
|
|
|
case PIPE_CAPF_MAX_LINE_WIDTH_AA:
|
|
|
|
return 7.375f;
|
|
|
|
|
|
|
|
case PIPE_CAPF_MAX_POINT_WIDTH:
|
|
|
|
case PIPE_CAPF_MAX_POINT_WIDTH_AA:
|
|
|
|
return 255.0f;
|
|
|
|
|
|
|
|
case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY:
|
|
|
|
return 16.0f;
|
|
|
|
case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS:
|
|
|
|
return 15.0f;
|
2018-05-03 05:52:26 +01:00
|
|
|
case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE:
|
|
|
|
case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE:
|
|
|
|
case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY:
|
|
|
|
return 0.0f;
|
2017-11-24 07:15:14 +00:00
|
|
|
default:
|
|
|
|
unreachable("unknown param");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
iris_get_shader_param(struct pipe_screen *pscreen,
|
2018-07-20 09:18:57 +01:00
|
|
|
enum pipe_shader_type p_stage,
|
2017-11-24 07:15:14 +00:00
|
|
|
enum pipe_shader_cap param)
|
|
|
|
{
|
|
|
|
struct iris_screen *screen = (struct iris_screen *)pscreen;
|
|
|
|
struct brw_compiler *compiler = screen->compiler;
|
2018-07-20 09:18:57 +01:00
|
|
|
gl_shader_stage stage = stage_from_pipe(p_stage);
|
2017-11-24 07:15:14 +00:00
|
|
|
|
|
|
|
/* this is probably not totally correct.. but it's a start: */
|
|
|
|
switch (param) {
|
|
|
|
case PIPE_SHADER_CAP_MAX_INSTRUCTIONS:
|
2018-07-20 09:18:57 +01:00
|
|
|
return stage == MESA_SHADER_FRAGMENT ? 1024 : 16384;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS:
|
2018-07-20 09:18:57 +01:00
|
|
|
return stage == MESA_SHADER_FRAGMENT ? 1024 : 0;
|
2017-11-24 07:15:14 +00:00
|
|
|
|
|
|
|
case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH:
|
|
|
|
return UINT_MAX;
|
|
|
|
|
|
|
|
case PIPE_SHADER_CAP_MAX_INPUTS:
|
2018-07-20 09:18:57 +01:00
|
|
|
return stage == MESA_SHADER_VERTEX ? 16 : 32;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_SHADER_CAP_MAX_OUTPUTS:
|
|
|
|
return 32;
|
|
|
|
case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE:
|
|
|
|
return 16 * 1024 * sizeof(float);
|
|
|
|
case PIPE_SHADER_CAP_MAX_CONST_BUFFERS:
|
|
|
|
return 16;
|
|
|
|
case PIPE_SHADER_CAP_MAX_TEMPS:
|
|
|
|
return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
|
|
|
|
case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED:
|
|
|
|
return 0;
|
|
|
|
case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR:
|
2018-07-20 09:18:57 +01:00
|
|
|
return !compiler->glsl_compiler_options[stage].EmitNoIndirectInput;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR:
|
2018-07-20 09:18:57 +01:00
|
|
|
return !compiler->glsl_compiler_options[stage].EmitNoIndirectOutput;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR:
|
2018-07-20 09:18:57 +01:00
|
|
|
return !compiler->glsl_compiler_options[stage].EmitNoIndirectTemp;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR:
|
|
|
|
return 1;
|
|
|
|
case PIPE_SHADER_CAP_SUBROUTINES:
|
|
|
|
return 0;
|
|
|
|
case PIPE_SHADER_CAP_INTEGERS:
|
|
|
|
case PIPE_SHADER_CAP_SCALAR_ISA:
|
|
|
|
return 1;
|
|
|
|
case PIPE_SHADER_CAP_INT64_ATOMICS:
|
|
|
|
case PIPE_SHADER_CAP_FP16:
|
|
|
|
return 0;
|
|
|
|
case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_SHADER_IMAGES:
|
|
|
|
return IRIS_MAX_TEXTURE_SAMPLERS;
|
2018-07-25 01:44:09 +01:00
|
|
|
case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS:
|
|
|
|
return IRIS_MAX_ABOS + IRIS_MAX_SSBOS;
|
2017-11-24 07:15:14 +00:00
|
|
|
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS:
|
|
|
|
case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS:
|
|
|
|
return 0;
|
|
|
|
case PIPE_SHADER_CAP_PREFERRED_IR:
|
|
|
|
return PIPE_SHADER_IR_NIR;
|
|
|
|
case PIPE_SHADER_CAP_SUPPORTED_IRS:
|
|
|
|
return 0;
|
|
|
|
case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT:
|
|
|
|
return 32;
|
|
|
|
case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE:
|
|
|
|
case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED:
|
|
|
|
return 0;
|
|
|
|
default:
|
|
|
|
unreachable("unknown shader param");
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
iris_get_compute_param(struct pipe_screen *pscreen,
|
|
|
|
enum pipe_shader_ir ir_type,
|
|
|
|
enum pipe_compute_cap param,
|
|
|
|
void *ret)
|
|
|
|
{
|
|
|
|
/* TODO: compute shaders */
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint64_t
|
|
|
|
iris_get_timestamp(struct pipe_screen *pscreen)
|
|
|
|
{
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
iris_destroy_screen(struct pipe_screen *pscreen)
|
|
|
|
{
|
|
|
|
struct iris_screen *screen = (struct iris_screen *) pscreen;
|
2018-04-19 20:52:51 +01:00
|
|
|
iris_bo_unreference(screen->workaround_bo);
|
2017-11-24 07:15:14 +00:00
|
|
|
ralloc_free(screen);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
iris_fence_reference(struct pipe_screen *screen,
|
|
|
|
struct pipe_fence_handle **ptr,
|
|
|
|
struct pipe_fence_handle *fence)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static boolean
|
|
|
|
iris_fence_finish(struct pipe_screen *screen,
|
|
|
|
struct pipe_context *ctx,
|
|
|
|
struct pipe_fence_handle *fence,
|
|
|
|
uint64_t timeout)
|
|
|
|
{
|
|
|
|
return true;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void
|
|
|
|
iris_query_memory_info(struct pipe_screen *pscreen,
|
|
|
|
struct pipe_memory_info *info)
|
|
|
|
{
|
|
|
|
}
|
|
|
|
|
|
|
|
static const void *
|
|
|
|
iris_get_compiler_options(struct pipe_screen *pscreen,
|
|
|
|
enum pipe_shader_ir ir,
|
|
|
|
enum pipe_shader_type pstage)
|
|
|
|
{
|
|
|
|
struct iris_screen *screen = (struct iris_screen *) pscreen;
|
|
|
|
gl_shader_stage stage = stage_from_pipe(pstage);
|
|
|
|
assert(ir == PIPE_SHADER_IR_NIR);
|
|
|
|
|
|
|
|
return screen->compiler->glsl_compiler_options[stage].NirOptions;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
iris_getparam(struct iris_screen *screen, int param, int *value)
|
|
|
|
{
|
|
|
|
struct drm_i915_getparam gp = { .param = param, .value = value };
|
|
|
|
|
|
|
|
if (ioctl(screen->fd, DRM_IOCTL_I915_GETPARAM, &gp) == -1)
|
|
|
|
return -errno;
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static bool
|
|
|
|
iris_getparam_boolean(struct iris_screen *screen, int param)
|
|
|
|
{
|
|
|
|
int value = 0;
|
|
|
|
return (iris_getparam(screen, param, &value) == 0) && value;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int
|
|
|
|
iris_getparam_integer(struct iris_screen *screen, int param)
|
|
|
|
{
|
|
|
|
int value = -1;
|
|
|
|
|
|
|
|
if (iris_getparam(screen, param, &value) == 0)
|
|
|
|
return value;
|
|
|
|
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
|
2018-01-19 23:41:46 +00:00
|
|
|
static void
|
|
|
|
iris_shader_debug_log(void *data, const char *fmt, ...)
|
|
|
|
{
|
2018-01-20 10:01:07 +00:00
|
|
|
struct pipe_debug_callback *dbg = data;
|
|
|
|
unsigned id = 0;
|
2018-01-19 23:41:46 +00:00
|
|
|
va_list args;
|
|
|
|
|
|
|
|
if (!dbg->debug_message)
|
|
|
|
return;
|
|
|
|
|
|
|
|
va_start(args, fmt);
|
2018-01-20 10:01:07 +00:00
|
|
|
dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_SHADER_INFO, fmt, args);
|
2018-01-19 23:41:46 +00:00
|
|
|
va_end(args);
|
|
|
|
}
|
|
|
|
|
2018-07-05 10:53:54 +01:00
|
|
|
static void
|
|
|
|
iris_shader_perf_log(void *data, const char *fmt, ...)
|
|
|
|
{
|
|
|
|
struct pipe_debug_callback *dbg = data;
|
|
|
|
unsigned id = 0;
|
|
|
|
va_list args;
|
|
|
|
|
|
|
|
if (!dbg->debug_message)
|
|
|
|
return;
|
|
|
|
|
|
|
|
va_start(args, fmt);
|
|
|
|
dbg->debug_message(dbg->data, &id, PIPE_DEBUG_TYPE_PERF_INFO, fmt, args);
|
|
|
|
va_end(args);
|
|
|
|
}
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
struct pipe_screen *
|
|
|
|
iris_screen_create(int fd)
|
|
|
|
{
|
|
|
|
struct iris_screen *screen = rzalloc(NULL, struct iris_screen);
|
|
|
|
if (!screen)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
screen->fd = fd;
|
|
|
|
screen->pci_id = iris_getparam_integer(screen, I915_PARAM_CHIPSET_ID);
|
|
|
|
|
|
|
|
if (!gen_get_device_info(screen->pci_id, &screen->devinfo))
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
screen->bufmgr = iris_bufmgr_init(&screen->devinfo, fd);
|
|
|
|
if (!screen->bufmgr)
|
|
|
|
return NULL;
|
|
|
|
|
2018-04-19 20:52:51 +01:00
|
|
|
screen->workaround_bo =
|
|
|
|
iris_bo_alloc(screen->bufmgr, "workaround", 4096, IRIS_MEMZONE_OTHER);
|
|
|
|
if (!screen->workaround_bo)
|
|
|
|
return NULL;
|
|
|
|
|
2018-01-20 09:12:12 +00:00
|
|
|
brw_process_intel_debug_variable();
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
bool hw_has_swizzling = false; // XXX: detect?
|
|
|
|
isl_device_init(&screen->isl_dev, &screen->devinfo, hw_has_swizzling);
|
|
|
|
|
|
|
|
screen->compiler = brw_compiler_create(screen, &screen->devinfo);
|
2018-01-19 23:41:46 +00:00
|
|
|
screen->compiler->shader_debug_log = iris_shader_debug_log;
|
2018-07-05 10:53:54 +01:00
|
|
|
screen->compiler->shader_perf_log = iris_shader_perf_log;
|
2017-11-24 07:15:14 +00:00
|
|
|
|
2018-07-06 19:29:51 +01:00
|
|
|
slab_create_parent(&screen->transfer_pool,
|
|
|
|
sizeof(struct iris_transfer), 64);
|
|
|
|
|
2017-11-24 07:15:14 +00:00
|
|
|
struct pipe_screen *pscreen = &screen->base;
|
|
|
|
|
|
|
|
iris_init_screen_resource_functions(pscreen);
|
|
|
|
|
|
|
|
pscreen->destroy = iris_destroy_screen;
|
|
|
|
pscreen->get_name = iris_get_name;
|
|
|
|
pscreen->get_vendor = iris_get_vendor;
|
|
|
|
pscreen->get_device_vendor = iris_get_device_vendor;
|
|
|
|
pscreen->get_param = iris_get_param;
|
|
|
|
pscreen->get_shader_param = iris_get_shader_param;
|
|
|
|
pscreen->get_compute_param = iris_get_compute_param;
|
|
|
|
pscreen->get_paramf = iris_get_paramf;
|
|
|
|
pscreen->get_compiler_options = iris_get_compiler_options;
|
|
|
|
pscreen->is_format_supported = iris_is_format_supported;
|
|
|
|
pscreen->context_create = iris_create_context;
|
|
|
|
pscreen->flush_frontbuffer = iris_flush_frontbuffer;
|
|
|
|
pscreen->get_timestamp = iris_get_timestamp;
|
|
|
|
pscreen->fence_reference = iris_fence_reference;
|
|
|
|
pscreen->fence_finish = iris_fence_finish;
|
|
|
|
pscreen->query_memory_info = iris_query_memory_info;
|
|
|
|
|
|
|
|
return pscreen;
|
|
|
|
}
|