2016-04-10 03:26:50 +01:00
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/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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2018-04-01 21:49:48 +01:00
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* All Rights Reserved.
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2016-04-10 03:26:50 +01:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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2018-04-01 23:42:33 +01:00
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#include "si_build_pm4.h"
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2019-12-30 19:23:16 +00:00
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#include "util/u_upload_mgr.h"
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2016-08-26 16:26:43 +01:00
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#include "util/u_viewport.h"
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2016-04-10 03:26:50 +01:00
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2017-09-26 16:56:15 +01:00
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#define SI_MAX_SCISSOR 16384
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2016-04-10 11:53:12 +01:00
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2021-11-06 18:08:39 +00:00
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static void si_get_small_prim_cull_info(struct si_context *sctx, struct si_small_prim_cull_info *out)
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2019-12-24 03:16:42 +00:00
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{
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2020-03-27 18:32:38 +00:00
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/* This is needed by the small primitive culling, because it's done
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* in screen space.
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*/
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struct si_small_prim_cull_info info;
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2020-12-10 00:18:37 +00:00
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unsigned num_samples = si_get_num_coverage_samples(sctx);
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2020-03-27 18:32:38 +00:00
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assert(num_samples >= 1);
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info.scale[0] = sctx->viewports.states[0].scale[0];
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info.scale[1] = sctx->viewports.states[0].scale[1];
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info.translate[0] = sctx->viewports.states[0].translate[0];
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info.translate[1] = sctx->viewports.states[0].translate[1];
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/* The viewport shouldn't flip the X axis for the small prim culling to work. */
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assert(-info.scale[0] + info.translate[0] <= info.scale[0] + info.translate[0]);
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2021-11-06 18:07:25 +00:00
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/* Compute the line width used by the rasterizer. */
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float line_width = sctx->queued.named.rasterizer->line_width;
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if (num_samples == 1)
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line_width = roundf(line_width);
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line_width = MAX2(line_width, 1);
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info.clip_half_line_width[0] = line_width * 0.5 / fabs(info.scale[0]);
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info.clip_half_line_width[1] = line_width * 0.5 / fabs(info.scale[1]);
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2020-03-27 18:32:38 +00:00
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/* If the Y axis is inverted (OpenGL default framebuffer), reverse it.
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* This is because the viewport transformation inverts the clip space
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* bounding box, so min becomes max, which breaks small primitive
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* culling.
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*/
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2021-01-10 07:00:58 +00:00
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if (sctx->viewport0_y_inverted) {
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2020-03-27 18:32:38 +00:00
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info.scale[1] = -info.scale[1];
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info.translate[1] = -info.translate[1];
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}
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2021-11-06 03:31:07 +00:00
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/* This is what the hardware does. */
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if (!sctx->queued.named.rasterizer->half_pixel_center) {
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info.translate[0] += 0.5;
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info.translate[1] += 0.5;
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}
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2021-11-06 01:56:24 +00:00
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memcpy(info.scale_no_aa, info.scale, sizeof(info.scale));
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memcpy(info.translate_no_aa, info.translate, sizeof(info.translate));
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2020-03-27 18:32:38 +00:00
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/* Scale the framebuffer up, so that samples become pixels and small
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* primitive culling is the same for all sample counts.
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* This only works with the standard DX sample positions, because
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* the samples are evenly spaced on both X and Y axes.
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*/
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for (unsigned i = 0; i < 2; i++) {
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info.scale[i] *= num_samples;
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info.translate[i] *= num_samples;
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}
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2020-12-10 00:18:37 +00:00
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/* Better subpixel precision increases the efficiency of small
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* primitive culling. (more precision means a tighter bounding box
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* around primitives and more accurate elimination)
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*/
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unsigned quant_mode = sctx->viewports.as_scissor[0].quant_mode;
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if (quant_mode == SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH)
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2021-11-06 01:56:24 +00:00
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info.small_prim_precision_no_aa = 1.0 / 4096.0;
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2020-12-10 00:18:37 +00:00
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else if (quant_mode == SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH)
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2021-11-06 01:56:24 +00:00
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info.small_prim_precision_no_aa = 1.0 / 1024.0;
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2020-12-10 00:18:37 +00:00
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else
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2021-11-06 01:56:24 +00:00
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info.small_prim_precision_no_aa = 1.0 / 256.0;
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info.small_prim_precision = num_samples * info.small_prim_precision_no_aa;
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2020-12-10 00:18:37 +00:00
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2020-03-27 18:32:38 +00:00
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*out = info;
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2019-12-24 03:16:42 +00:00
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}
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2020-12-10 00:18:37 +00:00
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static void si_emit_cull_state(struct si_context *sctx)
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{
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assert(sctx->screen->use_ngg_culling);
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2021-11-06 18:08:53 +00:00
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const unsigned upload_size = offsetof(struct si_small_prim_cull_info, small_prim_precision);
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2020-12-10 00:18:37 +00:00
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struct si_small_prim_cull_info info;
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si_get_small_prim_cull_info(sctx, &info);
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if (!sctx->small_prim_cull_info_buf ||
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memcmp(&info, &sctx->last_small_prim_cull_info, sizeof(info))) {
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unsigned offset = 0;
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2021-11-06 18:08:53 +00:00
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u_upload_data(sctx->b.const_uploader, 0, upload_size,
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si_optimal_tcc_alignment(sctx, upload_size), &info, &offset,
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2020-12-10 00:18:37 +00:00
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(struct pipe_resource **)&sctx->small_prim_cull_info_buf);
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sctx->small_prim_cull_info_address = sctx->small_prim_cull_info_buf->gpu_address + offset;
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sctx->last_small_prim_cull_info = info;
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}
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/* This will end up in SGPR6 as (value << 8), shifted by the hw. */
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radeon_add_to_buffer_list(sctx, &sctx->gfx_cs, sctx->small_prim_cull_info_buf,
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2021-10-22 04:17:03 +01:00
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RADEON_USAGE_READ | RADEON_PRIO_CONST_BUFFER);
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2021-01-09 20:14:22 +00:00
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radeon_begin(&sctx->gfx_cs);
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2021-11-06 18:08:53 +00:00
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radeon_set_sh_reg(R_00B230_SPI_SHADER_USER_DATA_GS_0 + GFX9_SGPR_SMALL_PRIM_CULL_INFO * 4,
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sctx->small_prim_cull_info_address);
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2021-01-09 20:14:22 +00:00
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radeon_end();
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2020-12-10 00:18:37 +00:00
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/* Set VS_STATE.SMALL_PRIM_PRECISION for NGG culling.
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*
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* small_prim_precision is 1 / 2^n. We only need n between 5 (1/32) and 12 (1/4096).
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* Such a floating point value can be packed into 4 bits as follows:
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* If we pass the first 4 bits of the exponent to the shader and set the next 3 bits
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* to 1, we'll get the number exactly because all other bits are always 0. See:
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* 1
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* value = (0x70 | value.exponent[0:3]) << 23 = ------------------------------
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* 2 ^ (15 - value.exponent[0:3])
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*
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* So pass only the first 4 bits of the float exponent to the shader.
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*/
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2022-06-09 14:41:52 +01:00
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SET_FIELD(sctx->current_gs_state, GS_STATE_SMALL_PRIM_PRECISION,
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(fui(info.small_prim_precision) >> 23) & 0xf);
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2020-12-10 00:18:37 +00:00
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}
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2020-03-27 18:32:38 +00:00
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static void si_set_scissor_states(struct pipe_context *pctx, unsigned start_slot,
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unsigned num_scissors, const struct pipe_scissor_state *state)
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2016-04-10 03:26:50 +01:00
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{
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2020-03-27 18:32:38 +00:00
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struct si_context *ctx = (struct si_context *)pctx;
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int i;
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2016-04-10 03:26:50 +01:00
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2020-03-27 18:32:38 +00:00
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for (i = 0; i < num_scissors; i++)
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ctx->scissors[start_slot + i] = state[i];
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2016-04-10 03:26:50 +01:00
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2020-03-27 18:32:38 +00:00
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if (!ctx->queued.named.rasterizer->scissor_enable)
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return;
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2016-04-10 03:26:50 +01:00
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2020-03-27 18:32:38 +00:00
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si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
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2016-04-10 03:26:50 +01:00
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}
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2016-04-13 16:27:02 +01:00
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/* Since the guard band disables clipping, we have to clip per-pixel
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* using a scissor.
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*/
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2017-09-26 16:56:15 +01:00
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static void si_get_scissor_from_viewport(struct si_context *ctx,
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2020-03-27 18:32:38 +00:00
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const struct pipe_viewport_state *vp,
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struct si_signed_scissor *scissor)
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2016-04-10 03:26:50 +01:00
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{
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2020-03-27 18:32:38 +00:00
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float tmp, minx, miny, maxx, maxy;
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/* Convert (-1, -1) and (1, 1) from clip space into window space. */
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minx = -vp->scale[0] + vp->translate[0];
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miny = -vp->scale[1] + vp->translate[1];
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maxx = vp->scale[0] + vp->translate[0];
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maxy = vp->scale[1] + vp->translate[1];
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/* Handle inverted viewports. */
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if (minx > maxx) {
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tmp = minx;
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minx = maxx;
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maxx = tmp;
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}
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if (miny > maxy) {
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tmp = miny;
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miny = maxy;
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maxy = tmp;
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}
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/* Convert to integer and round up the max bounds. */
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scissor->minx = minx;
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scissor->miny = miny;
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scissor->maxx = ceilf(maxx);
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scissor->maxy = ceilf(maxy);
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2016-04-10 03:26:50 +01:00
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}
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2020-03-27 18:32:38 +00:00
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static void si_clamp_scissor(struct si_context *ctx, struct pipe_scissor_state *out,
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struct si_signed_scissor *scissor)
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2016-04-10 03:26:50 +01:00
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{
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2020-03-27 18:32:38 +00:00
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out->minx = CLAMP(scissor->minx, 0, SI_MAX_SCISSOR);
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out->miny = CLAMP(scissor->miny, 0, SI_MAX_SCISSOR);
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out->maxx = CLAMP(scissor->maxx, 0, SI_MAX_SCISSOR);
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out->maxy = CLAMP(scissor->maxy, 0, SI_MAX_SCISSOR);
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2016-04-10 03:26:50 +01:00
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}
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2020-03-27 18:32:38 +00:00
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static void si_clip_scissor(struct pipe_scissor_state *out, struct pipe_scissor_state *clip)
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2016-04-10 03:26:50 +01:00
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{
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2020-03-27 18:32:38 +00:00
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out->minx = MAX2(out->minx, clip->minx);
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out->miny = MAX2(out->miny, clip->miny);
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out->maxx = MIN2(out->maxx, clip->maxx);
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out->maxy = MIN2(out->maxy, clip->maxy);
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2016-04-10 03:26:50 +01:00
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}
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2020-03-27 18:32:38 +00:00
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static void si_scissor_make_union(struct si_signed_scissor *out, struct si_signed_scissor *in)
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2016-04-10 03:26:50 +01:00
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{
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2020-03-27 18:32:38 +00:00
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out->minx = MIN2(out->minx, in->minx);
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out->miny = MIN2(out->miny, in->miny);
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out->maxx = MAX2(out->maxx, in->maxx);
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out->maxy = MAX2(out->maxy, in->maxy);
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out->quant_mode = MIN2(out->quant_mode, in->quant_mode);
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2016-04-10 03:26:50 +01:00
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}
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2020-03-27 18:32:38 +00:00
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static void si_emit_one_scissor(struct si_context *ctx, struct radeon_cmdbuf *cs,
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struct si_signed_scissor *vp_scissor,
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struct pipe_scissor_state *scissor)
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2016-04-10 03:26:50 +01:00
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{
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2020-03-27 18:32:38 +00:00
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struct pipe_scissor_state final;
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if (ctx->vs_disables_clipping_viewport) {
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final.minx = final.miny = 0;
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final.maxx = final.maxy = SI_MAX_SCISSOR;
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} else {
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si_clamp_scissor(ctx, &final, vp_scissor);
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}
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if (scissor)
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si_clip_scissor(&final, scissor);
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2021-01-09 20:14:22 +00:00
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radeon_begin(cs);
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2020-03-27 18:32:38 +00:00
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/* Workaround for a hw bug on GFX6 that occurs when PA_SU_HARDWARE_-
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* SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
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*/
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2022-05-12 07:50:17 +01:00
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if (ctx->gfx_level == GFX6 && (final.maxx == 0 || final.maxy == 0)) {
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2021-09-23 12:17:58 +01:00
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radeon_emit(S_028250_TL_X(1) | S_028250_TL_Y(1) | S_028250_WINDOW_OFFSET_DISABLE(1));
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radeon_emit(S_028254_BR_X(1) | S_028254_BR_Y(1));
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2021-01-09 20:14:22 +00:00
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radeon_end();
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2020-03-27 18:32:38 +00:00
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return;
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}
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2021-09-23 12:17:58 +01:00
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radeon_emit(S_028250_TL_X(final.minx) | S_028250_TL_Y(final.miny) |
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S_028250_WINDOW_OFFSET_DISABLE(1));
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radeon_emit(S_028254_BR_X(final.maxx) | S_028254_BR_Y(final.maxy));
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2021-01-09 20:14:22 +00:00
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radeon_end();
|
2016-04-10 03:26:50 +01:00
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}
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2019-01-10 19:32:42 +00:00
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#define MAX_PA_SU_HARDWARE_SCREEN_OFFSET 8176
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2018-05-31 03:38:05 +01:00
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static void si_emit_guardband(struct si_context *ctx)
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2016-04-10 03:26:50 +01:00
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{
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2020-03-27 18:32:38 +00:00
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const struct si_state_rasterizer *rs = ctx->queued.named.rasterizer;
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struct si_signed_scissor vp_as_scissor;
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struct pipe_viewport_state vp;
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float left, top, right, bottom, max_range, guardband_x, guardband_y;
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float discard_x, discard_y;
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if (ctx->vs_writes_viewport_index) {
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|
|
|
/* Shaders can draw to any viewport. Make a union of all
|
|
|
|
* viewports. */
|
|
|
|
vp_as_scissor = ctx->viewports.as_scissor[0];
|
|
|
|
for (unsigned i = 1; i < SI_MAX_VIEWPORTS; i++) {
|
|
|
|
si_scissor_make_union(&vp_as_scissor, &ctx->viewports.as_scissor[i]);
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
vp_as_scissor = ctx->viewports.as_scissor[0];
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Blits don't set the viewport state. The vertex shader determines
|
|
|
|
* the viewport size by scaling the coordinates, so we don't know
|
|
|
|
* how large the viewport is. Assume the worst case.
|
|
|
|
*/
|
|
|
|
if (ctx->vs_disables_clipping_viewport)
|
|
|
|
vp_as_scissor.quant_mode = SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH;
|
|
|
|
|
|
|
|
/* Determine the optimal hardware screen offset to center the viewport
|
|
|
|
* within the viewport range in order to maximize the guardband size.
|
|
|
|
*/
|
|
|
|
int hw_screen_offset_x = (vp_as_scissor.maxx + vp_as_scissor.minx) / 2;
|
|
|
|
int hw_screen_offset_y = (vp_as_scissor.maxy + vp_as_scissor.miny) / 2;
|
|
|
|
|
|
|
|
/* GFX6-GFX7 need to align the offset to an ubertile consisting of all SEs. */
|
|
|
|
const unsigned hw_screen_offset_alignment =
|
2022-05-12 07:50:17 +01:00
|
|
|
ctx->gfx_level >= GFX11 ? 32 :
|
|
|
|
ctx->gfx_level >= GFX8 ? 16 : MAX2(ctx->screen->se_tile_repeat, 16);
|
2020-03-27 18:32:38 +00:00
|
|
|
|
|
|
|
/* Indexed by quantization modes */
|
|
|
|
static int max_viewport_size[] = {65535, 16383, 4095};
|
|
|
|
|
|
|
|
/* Ensure that the whole viewport stays representable in
|
|
|
|
* absolute coordinates.
|
|
|
|
* See comment in si_set_viewport_states.
|
|
|
|
*/
|
|
|
|
assert(vp_as_scissor.maxx <= max_viewport_size[vp_as_scissor.quant_mode] &&
|
|
|
|
vp_as_scissor.maxy <= max_viewport_size[vp_as_scissor.quant_mode]);
|
|
|
|
|
|
|
|
hw_screen_offset_x = CLAMP(hw_screen_offset_x, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET);
|
|
|
|
hw_screen_offset_y = CLAMP(hw_screen_offset_y, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET);
|
|
|
|
|
|
|
|
/* Align the screen offset by dropping the low bits. */
|
|
|
|
hw_screen_offset_x &= ~(hw_screen_offset_alignment - 1);
|
|
|
|
hw_screen_offset_y &= ~(hw_screen_offset_alignment - 1);
|
|
|
|
|
|
|
|
/* Apply the offset to center the viewport and maximize the guardband. */
|
|
|
|
vp_as_scissor.minx -= hw_screen_offset_x;
|
|
|
|
vp_as_scissor.maxx -= hw_screen_offset_x;
|
|
|
|
vp_as_scissor.miny -= hw_screen_offset_y;
|
|
|
|
vp_as_scissor.maxy -= hw_screen_offset_y;
|
|
|
|
|
|
|
|
/* Reconstruct the viewport transformation from the scissor. */
|
|
|
|
vp.translate[0] = (vp_as_scissor.minx + vp_as_scissor.maxx) / 2.0;
|
|
|
|
vp.translate[1] = (vp_as_scissor.miny + vp_as_scissor.maxy) / 2.0;
|
|
|
|
vp.scale[0] = vp_as_scissor.maxx - vp.translate[0];
|
|
|
|
vp.scale[1] = vp_as_scissor.maxy - vp.translate[1];
|
|
|
|
|
|
|
|
/* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
|
|
|
|
if (vp_as_scissor.minx == vp_as_scissor.maxx)
|
|
|
|
vp.scale[0] = 0.5;
|
|
|
|
if (vp_as_scissor.miny == vp_as_scissor.maxy)
|
|
|
|
vp.scale[1] = 0.5;
|
|
|
|
|
|
|
|
/* Find the biggest guard band that is inside the supported viewport
|
|
|
|
* range. The guard band is specified as a horizontal and vertical
|
|
|
|
* distance from (0,0) in clip space.
|
|
|
|
*
|
|
|
|
* This is done by applying the inverse viewport transformation
|
|
|
|
* on the viewport limits to get those limits in clip space.
|
|
|
|
*
|
2020-09-11 10:52:18 +01:00
|
|
|
* The viewport range is [-max_viewport_size/2 - 1, max_viewport_size/2].
|
|
|
|
* (-1 to the min coord because max_viewport_size is odd and ViewportBounds
|
|
|
|
* Min/Max are -32768, 32767).
|
2020-03-27 18:32:38 +00:00
|
|
|
*/
|
|
|
|
assert(vp_as_scissor.quant_mode < ARRAY_SIZE(max_viewport_size));
|
|
|
|
max_range = max_viewport_size[vp_as_scissor.quant_mode] / 2;
|
2020-09-11 10:52:18 +01:00
|
|
|
left = (-max_range - 1 - vp.translate[0]) / vp.scale[0];
|
2020-03-27 18:32:38 +00:00
|
|
|
right = (max_range - vp.translate[0]) / vp.scale[0];
|
2020-09-11 10:52:18 +01:00
|
|
|
top = (-max_range - 1 - vp.translate[1]) / vp.scale[1];
|
2020-03-27 18:32:38 +00:00
|
|
|
bottom = (max_range - vp.translate[1]) / vp.scale[1];
|
|
|
|
|
|
|
|
assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
|
|
|
|
|
|
|
|
guardband_x = MIN2(-left, right);
|
|
|
|
guardband_y = MIN2(-top, bottom);
|
|
|
|
|
|
|
|
discard_x = 1.0;
|
|
|
|
discard_y = 1.0;
|
|
|
|
|
|
|
|
if (unlikely(util_prim_is_points_or_lines(ctx->current_rast_prim))) {
|
|
|
|
/* When rendering wide points or lines, we need to be more
|
|
|
|
* conservative about when to discard them entirely. */
|
|
|
|
float pixels;
|
|
|
|
|
|
|
|
if (ctx->current_rast_prim == PIPE_PRIM_POINTS)
|
|
|
|
pixels = rs->max_point_size;
|
|
|
|
else
|
|
|
|
pixels = rs->line_width;
|
|
|
|
|
|
|
|
/* Add half the point size / line width */
|
|
|
|
discard_x += pixels / (2.0 * vp.scale[0]);
|
|
|
|
discard_y += pixels / (2.0 * vp.scale[1]);
|
|
|
|
|
|
|
|
/* Discard primitives that would lie entirely outside the clip
|
|
|
|
* region. */
|
|
|
|
discard_x = MIN2(discard_x, guardband_x);
|
|
|
|
discard_y = MIN2(discard_y, guardband_y);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* If any of the GB registers is updated, all of them must be updated.
|
|
|
|
* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
|
|
|
|
* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
|
|
|
|
*/
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_begin(&ctx->gfx_cs);
|
2020-03-27 18:32:38 +00:00
|
|
|
radeon_opt_set_context_reg4(ctx, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ,
|
|
|
|
SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ, fui(guardband_y), fui(discard_y),
|
|
|
|
fui(guardband_x), fui(discard_x));
|
|
|
|
radeon_opt_set_context_reg(ctx, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET,
|
|
|
|
SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
|
|
|
|
S_028234_HW_SCREEN_OFFSET_X(hw_screen_offset_x >> 4) |
|
|
|
|
S_028234_HW_SCREEN_OFFSET_Y(hw_screen_offset_y >> 4));
|
|
|
|
radeon_opt_set_context_reg(
|
|
|
|
ctx, R_028BE4_PA_SU_VTX_CNTL, SI_TRACKED_PA_SU_VTX_CNTL,
|
2022-03-04 10:23:20 +00:00
|
|
|
S_028BE4_PIX_CENTER(rs->half_pixel_center) | S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
|
2020-03-27 18:32:38 +00:00
|
|
|
S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH + vp_as_scissor.quant_mode));
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_end_update_context_roll(ctx);
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|
|
|
|
|
2018-04-09 02:20:53 +01:00
|
|
|
static void si_emit_scissors(struct si_context *ctx)
|
2016-04-10 03:26:50 +01:00
|
|
|
{
|
2020-11-29 09:09:02 +00:00
|
|
|
struct radeon_cmdbuf *cs = &ctx->gfx_cs;
|
2020-03-27 18:32:38 +00:00
|
|
|
struct pipe_scissor_state *states = ctx->scissors;
|
|
|
|
bool scissor_enabled = ctx->queued.named.rasterizer->scissor_enable;
|
|
|
|
|
|
|
|
/* The simple case: Only 1 viewport is active. */
|
|
|
|
if (!ctx->vs_writes_viewport_index) {
|
|
|
|
struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0];
|
|
|
|
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_begin(cs);
|
2021-09-23 12:17:58 +01:00
|
|
|
radeon_set_context_reg_seq(R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_end();
|
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
si_emit_one_scissor(ctx, cs, vp, scissor_enabled ? &states[0] : NULL);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* All registers in the array need to be updated if any of them is changed.
|
|
|
|
* This is a hardware requirement.
|
|
|
|
*/
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_begin(cs);
|
2021-09-23 12:17:58 +01:00
|
|
|
radeon_set_context_reg_seq(R_028250_PA_SC_VPORT_SCISSOR_0_TL, SI_MAX_VIEWPORTS * 2);
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_end();
|
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++) {
|
|
|
|
si_emit_one_scissor(ctx, cs, &ctx->viewports.as_scissor[i],
|
|
|
|
scissor_enabled ? &states[i] : NULL);
|
|
|
|
}
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
static void si_set_viewport_states(struct pipe_context *pctx, unsigned start_slot,
|
|
|
|
unsigned num_viewports, const struct pipe_viewport_state *state)
|
2016-04-10 03:26:50 +01:00
|
|
|
{
|
2020-03-27 18:32:38 +00:00
|
|
|
struct si_context *ctx = (struct si_context *)pctx;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < num_viewports; i++) {
|
|
|
|
unsigned index = start_slot + i;
|
|
|
|
struct si_signed_scissor *scissor = &ctx->viewports.as_scissor[index];
|
|
|
|
|
|
|
|
ctx->viewports.states[index] = state[i];
|
|
|
|
|
|
|
|
si_get_scissor_from_viewport(ctx, &state[i], scissor);
|
|
|
|
|
2020-09-11 10:52:04 +01:00
|
|
|
int max_corner = MAX2(
|
|
|
|
MAX2(abs(scissor->maxx), abs(scissor->maxy)),
|
|
|
|
MAX2(abs(scissor->minx), abs(scissor->miny)));
|
2020-03-27 18:32:38 +00:00
|
|
|
|
|
|
|
/* Determine the best quantization mode (subpixel precision),
|
|
|
|
* but also leave enough space for the guardband.
|
|
|
|
*
|
|
|
|
* Note that primitive binning requires QUANT_MODE == 16_8 on Vega10
|
|
|
|
* and Raven1 for line and rectangle primitive types to work correctly.
|
|
|
|
* Always use 16_8 if primitive binning is possible to occur.
|
|
|
|
*/
|
|
|
|
if ((ctx->family == CHIP_VEGA10 || ctx->family == CHIP_RAVEN) && ctx->screen->dpbb_allowed)
|
2021-10-15 16:28:19 +01:00
|
|
|
max_corner = 16384; /* Use QUANT_MODE == 16_8. */
|
2020-03-27 18:32:38 +00:00
|
|
|
|
|
|
|
/* Another constraint is that all coordinates in the viewport
|
|
|
|
* are representable in fixed point with respect to the
|
|
|
|
* surface origin.
|
|
|
|
*
|
|
|
|
* It means that PA_SU_HARDWARE_SCREEN_OFFSET can't be given
|
|
|
|
* an offset that would make the upper corner of the viewport
|
|
|
|
* greater than the maximum representable number post
|
|
|
|
* quantization, ie 2^quant_bits.
|
|
|
|
*
|
|
|
|
* This does not matter for 14.10 and 16.8 formats since the
|
|
|
|
* offset is already limited at 8k, but it means we can't use
|
|
|
|
* 12.12 if we are drawing to some pixels outside the lower
|
|
|
|
* 4k x 4k of the render target.
|
|
|
|
*/
|
|
|
|
|
2021-10-15 16:28:19 +01:00
|
|
|
if (max_corner <= 1024) /* 4K scanline area for guardband */
|
2020-03-27 18:32:38 +00:00
|
|
|
scissor->quant_mode = SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH;
|
2021-10-15 16:28:19 +01:00
|
|
|
else if (max_corner <= 4096) /* 16K scanline area for guardband */
|
2020-03-27 18:32:38 +00:00
|
|
|
scissor->quant_mode = SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH;
|
|
|
|
else /* 64K scanline area for guardband */
|
|
|
|
scissor->quant_mode = SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (start_slot == 0) {
|
2021-01-10 07:00:58 +00:00
|
|
|
ctx->viewport0_y_inverted =
|
2020-03-27 18:32:38 +00:00
|
|
|
-state->scale[1] + state->translate[1] > state->scale[1] + state->translate[1];
|
2020-12-10 00:18:37 +00:00
|
|
|
|
|
|
|
/* NGG cull state uses the viewport and quant mode. */
|
|
|
|
if (ctx->screen->use_ngg_culling)
|
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.ngg_cull_state);
|
2020-03-27 18:32:38 +00:00
|
|
|
}
|
|
|
|
|
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
|
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
|
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
static void si_emit_one_viewport(struct si_context *ctx, struct pipe_viewport_state *state)
|
2016-08-26 10:53:47 +01:00
|
|
|
{
|
2020-11-29 09:09:02 +00:00
|
|
|
struct radeon_cmdbuf *cs = &ctx->gfx_cs;
|
2020-03-27 18:32:38 +00:00
|
|
|
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_begin(cs);
|
2021-09-23 12:17:58 +01:00
|
|
|
radeon_emit(fui(state->scale[0]));
|
|
|
|
radeon_emit(fui(state->translate[0]));
|
|
|
|
radeon_emit(fui(state->scale[1]));
|
|
|
|
radeon_emit(fui(state->translate[1]));
|
|
|
|
radeon_emit(fui(state->scale[2]));
|
|
|
|
radeon_emit(fui(state->translate[2]));
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_end();
|
2016-08-26 10:53:47 +01:00
|
|
|
}
|
|
|
|
|
2017-09-26 16:56:15 +01:00
|
|
|
static void si_emit_viewports(struct si_context *ctx)
|
2016-04-10 03:26:50 +01:00
|
|
|
{
|
2020-11-29 09:09:02 +00:00
|
|
|
struct radeon_cmdbuf *cs = &ctx->gfx_cs;
|
2020-03-27 18:32:38 +00:00
|
|
|
struct pipe_viewport_state *states = ctx->viewports.states;
|
|
|
|
|
|
|
|
/* The simple case: Only 1 viewport is active. */
|
|
|
|
if (!ctx->vs_writes_viewport_index) {
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_begin(cs);
|
2021-09-23 12:17:58 +01:00
|
|
|
radeon_set_context_reg_seq(R_02843C_PA_CL_VPORT_XSCALE, 6);
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_end();
|
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
si_emit_one_viewport(ctx, &states[0]);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* All registers in the array need to be updated if any of them is changed.
|
|
|
|
* This is a hardware requirement.
|
|
|
|
*/
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_begin(cs);
|
2021-09-23 12:17:58 +01:00
|
|
|
radeon_set_context_reg_seq(R_02843C_PA_CL_VPORT_XSCALE + 0, SI_MAX_VIEWPORTS * 6);
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_end();
|
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++)
|
|
|
|
si_emit_one_viewport(ctx, &states[i]);
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
static inline void si_viewport_zmin_zmax(const struct pipe_viewport_state *vp, bool halfz,
|
|
|
|
bool window_space_position, float *zmin, float *zmax)
|
2017-10-05 23:19:22 +01:00
|
|
|
{
|
2020-03-27 18:32:38 +00:00
|
|
|
if (window_space_position) {
|
|
|
|
*zmin = 0;
|
|
|
|
*zmax = 1;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
util_viewport_zmin_zmax(vp, halfz, zmin, zmax);
|
2017-10-05 23:19:22 +01:00
|
|
|
}
|
|
|
|
|
2017-09-26 16:56:15 +01:00
|
|
|
static void si_emit_depth_ranges(struct si_context *ctx)
|
2016-04-10 03:26:50 +01:00
|
|
|
{
|
2020-11-29 09:09:02 +00:00
|
|
|
struct radeon_cmdbuf *cs = &ctx->gfx_cs;
|
2020-03-27 18:32:38 +00:00
|
|
|
struct pipe_viewport_state *states = ctx->viewports.states;
|
|
|
|
bool clip_halfz = ctx->queued.named.rasterizer->clip_halfz;
|
|
|
|
bool window_space = ctx->vs_disables_clipping_viewport;
|
|
|
|
float zmin, zmax;
|
|
|
|
|
|
|
|
/* The simple case: Only 1 viewport is active. */
|
|
|
|
if (!ctx->vs_writes_viewport_index) {
|
|
|
|
si_viewport_zmin_zmax(&states[0], clip_halfz, window_space, &zmin, &zmax);
|
|
|
|
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_begin(cs);
|
2021-09-23 12:17:58 +01:00
|
|
|
radeon_set_context_reg_seq(R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
|
2021-09-23 12:17:58 +01:00
|
|
|
radeon_emit(fui(zmin));
|
|
|
|
radeon_emit(fui(zmax));
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_end();
|
2020-03-27 18:32:38 +00:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* All registers in the array need to be updated if any of them is changed.
|
|
|
|
* This is a hardware requirement.
|
|
|
|
*/
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_begin(cs);
|
2021-09-23 12:17:58 +01:00
|
|
|
radeon_set_context_reg_seq(R_0282D0_PA_SC_VPORT_ZMIN_0, SI_MAX_VIEWPORTS * 2);
|
2020-03-27 18:32:38 +00:00
|
|
|
for (unsigned i = 0; i < SI_MAX_VIEWPORTS; i++) {
|
|
|
|
si_viewport_zmin_zmax(&states[i], clip_halfz, window_space, &zmin, &zmax);
|
2021-09-23 12:17:58 +01:00
|
|
|
radeon_emit(fui(zmin));
|
|
|
|
radeon_emit(fui(zmax));
|
2020-03-27 18:32:38 +00:00
|
|
|
}
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_end();
|
2016-08-26 16:26:43 +01:00
|
|
|
}
|
|
|
|
|
2018-04-09 02:20:53 +01:00
|
|
|
static void si_emit_viewport_states(struct si_context *ctx)
|
2016-08-26 16:26:43 +01:00
|
|
|
{
|
2020-03-27 18:32:38 +00:00
|
|
|
si_emit_viewports(ctx);
|
|
|
|
si_emit_depth_ranges(ctx);
|
2016-08-26 16:26:43 +01:00
|
|
|
}
|
|
|
|
|
2016-04-10 03:26:50 +01:00
|
|
|
/**
|
2017-10-05 23:14:17 +01:00
|
|
|
* This reacts to 2 state changes:
|
|
|
|
* - VS.writes_viewport_index
|
|
|
|
* - VS output position in window space (enable/disable)
|
|
|
|
*
|
2016-04-10 03:26:50 +01:00
|
|
|
* Normally, we only emit 1 viewport and 1 scissor if no shader is using
|
|
|
|
* the VIEWPORT_INDEX output, and emitting the other viewports and scissors
|
|
|
|
* is delayed. When a shader with VIEWPORT_INDEX appears, this should be
|
|
|
|
* called to emit the rest.
|
|
|
|
*/
|
2017-10-05 23:14:17 +01:00
|
|
|
void si_update_vs_viewport_state(struct si_context *ctx)
|
2016-04-10 03:26:50 +01:00
|
|
|
{
|
2022-01-04 19:41:46 +00:00
|
|
|
struct si_shader_ctx_state *vs = si_get_vs(ctx);
|
|
|
|
struct si_shader_info *info = vs->cso ? &vs->cso->info : NULL;
|
2020-03-27 18:32:38 +00:00
|
|
|
bool vs_window_space;
|
|
|
|
|
|
|
|
if (!info)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* When the VS disables clipping and viewport transformation. */
|
2022-01-04 19:41:46 +00:00
|
|
|
vs_window_space = vs->cso->stage == MESA_SHADER_VERTEX && info->base.vs.window_space_position;
|
2020-03-27 18:32:38 +00:00
|
|
|
|
|
|
|
if (ctx->vs_disables_clipping_viewport != vs_window_space) {
|
|
|
|
ctx->vs_disables_clipping_viewport = vs_window_space;
|
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
|
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Viewport index handling. */
|
|
|
|
if (ctx->vs_writes_viewport_index == info->writes_viewport_index)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* This changes how the guardband is computed. */
|
|
|
|
ctx->vs_writes_viewport_index = info->writes_viewport_index;
|
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
|
|
|
|
|
|
|
|
/* Emit scissors and viewports that were enabled by having
|
|
|
|
* the ViewportIndex output.
|
|
|
|
*/
|
|
|
|
if (info->writes_viewport_index) {
|
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
|
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
|
|
|
|
}
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|
|
|
|
|
2018-08-06 09:20:30 +01:00
|
|
|
static void si_emit_window_rectangles(struct si_context *sctx)
|
|
|
|
{
|
2020-03-27 18:32:38 +00:00
|
|
|
/* There are four clipping rectangles. Their corner coordinates are inclusive.
|
|
|
|
* Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
|
|
|
|
* on whether the pixel is inside cliprects 0-3, respectively. For example,
|
|
|
|
* if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
|
|
|
|
* the number 3 (binary 0011).
|
|
|
|
*
|
|
|
|
* If CLIPRECT_RULE & (1 << number), the pixel is rasterized.
|
|
|
|
*/
|
2020-11-29 09:09:02 +00:00
|
|
|
struct radeon_cmdbuf *cs = &sctx->gfx_cs;
|
2020-03-27 18:32:38 +00:00
|
|
|
static const unsigned outside[4] = {
|
|
|
|
/* outside rectangle 0 */
|
|
|
|
V_02820C_OUT | V_02820C_IN_1 | V_02820C_IN_2 | V_02820C_IN_21 | V_02820C_IN_3 |
|
|
|
|
V_02820C_IN_31 | V_02820C_IN_32 | V_02820C_IN_321,
|
|
|
|
/* outside rectangles 0, 1 */
|
|
|
|
V_02820C_OUT | V_02820C_IN_2 | V_02820C_IN_3 | V_02820C_IN_32,
|
|
|
|
/* outside rectangles 0, 1, 2 */
|
|
|
|
V_02820C_OUT | V_02820C_IN_3,
|
|
|
|
/* outside rectangles 0, 1, 2, 3 */
|
|
|
|
V_02820C_OUT,
|
|
|
|
};
|
|
|
|
const unsigned disabled = 0xffff; /* all inside and outside cases */
|
|
|
|
unsigned num_rectangles = sctx->num_window_rectangles;
|
|
|
|
struct pipe_scissor_state *rects = sctx->window_rectangles;
|
|
|
|
unsigned rule;
|
|
|
|
|
|
|
|
assert(num_rectangles <= 4);
|
|
|
|
|
|
|
|
if (num_rectangles == 0)
|
|
|
|
rule = disabled;
|
|
|
|
else if (sctx->window_rectangles_include)
|
|
|
|
rule = ~outside[num_rectangles - 1];
|
|
|
|
else
|
|
|
|
rule = outside[num_rectangles - 1];
|
|
|
|
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_begin(cs);
|
2020-03-27 18:32:38 +00:00
|
|
|
radeon_opt_set_context_reg(sctx, R_02820C_PA_SC_CLIPRECT_RULE, SI_TRACKED_PA_SC_CLIPRECT_RULE,
|
|
|
|
rule);
|
2021-01-09 20:14:22 +00:00
|
|
|
if (num_rectangles == 0) {
|
|
|
|
radeon_end();
|
2020-03-27 18:32:38 +00:00
|
|
|
return;
|
2021-01-09 20:14:22 +00:00
|
|
|
}
|
2020-03-27 18:32:38 +00:00
|
|
|
|
2021-09-23 12:17:58 +01:00
|
|
|
radeon_set_context_reg_seq(R_028210_PA_SC_CLIPRECT_0_TL, num_rectangles * 2);
|
2020-03-27 18:32:38 +00:00
|
|
|
for (unsigned i = 0; i < num_rectangles; i++) {
|
2021-09-23 12:17:58 +01:00
|
|
|
radeon_emit(S_028210_TL_X(rects[i].minx) | S_028210_TL_Y(rects[i].miny));
|
|
|
|
radeon_emit(S_028214_BR_X(rects[i].maxx) | S_028214_BR_Y(rects[i].maxy));
|
2020-03-27 18:32:38 +00:00
|
|
|
}
|
2021-01-09 20:14:22 +00:00
|
|
|
radeon_end();
|
2018-08-06 09:20:30 +01:00
|
|
|
}
|
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
static void si_set_window_rectangles(struct pipe_context *ctx, bool include,
|
|
|
|
unsigned num_rectangles,
|
|
|
|
const struct pipe_scissor_state *rects)
|
2018-08-06 09:20:30 +01:00
|
|
|
{
|
2020-03-27 18:32:38 +00:00
|
|
|
struct si_context *sctx = (struct si_context *)ctx;
|
2018-08-06 09:20:30 +01:00
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
sctx->num_window_rectangles = num_rectangles;
|
|
|
|
sctx->window_rectangles_include = include;
|
|
|
|
if (num_rectangles) {
|
|
|
|
memcpy(sctx->window_rectangles, rects, sizeof(*rects) * num_rectangles);
|
|
|
|
}
|
2018-08-06 09:20:30 +01:00
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
si_mark_atom_dirty(sctx, &sctx->atoms.s.window_rectangles);
|
2018-08-06 09:20:30 +01:00
|
|
|
}
|
|
|
|
|
2017-09-26 16:56:15 +01:00
|
|
|
void si_init_viewport_functions(struct si_context *ctx)
|
2016-04-10 03:26:50 +01:00
|
|
|
{
|
2020-03-27 18:32:38 +00:00
|
|
|
ctx->atoms.s.guardband.emit = si_emit_guardband;
|
|
|
|
ctx->atoms.s.scissors.emit = si_emit_scissors;
|
|
|
|
ctx->atoms.s.viewports.emit = si_emit_viewport_states;
|
|
|
|
ctx->atoms.s.window_rectangles.emit = si_emit_window_rectangles;
|
2020-12-10 00:18:37 +00:00
|
|
|
ctx->atoms.s.ngg_cull_state.emit = si_emit_cull_state;
|
2016-04-10 03:26:50 +01:00
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
ctx->b.set_scissor_states = si_set_scissor_states;
|
|
|
|
ctx->b.set_viewport_states = si_set_viewport_states;
|
|
|
|
ctx->b.set_window_rectangles = si_set_window_rectangles;
|
2018-09-29 02:43:49 +01:00
|
|
|
|
2020-03-27 18:32:38 +00:00
|
|
|
for (unsigned i = 0; i < 16; i++)
|
|
|
|
ctx->viewports.as_scissor[i].quant_mode = SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH;
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|