2016-04-10 03:26:50 +01:00
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/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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2018-04-01 21:49:48 +01:00
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* All Rights Reserved.
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2016-04-10 03:26:50 +01:00
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* on the rights to use, copy, modify, merge, publish, distribute, sub
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* license, and/or sell copies of the Software, and to permit persons to whom
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* the Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
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* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
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* OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
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* USE OR OTHER DEALINGS IN THE SOFTWARE.
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*/
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2018-04-01 23:42:33 +01:00
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#include "si_build_pm4.h"
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2016-08-26 16:26:43 +01:00
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#include "util/u_viewport.h"
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2016-04-10 03:26:50 +01:00
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#include "tgsi/tgsi_scan.h"
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2017-09-26 16:56:15 +01:00
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#define SI_MAX_SCISSOR 16384
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2016-04-10 11:53:12 +01:00
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2017-09-26 16:56:15 +01:00
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static void si_set_scissor_states(struct pipe_context *pctx,
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unsigned start_slot,
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unsigned num_scissors,
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const struct pipe_scissor_state *state)
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2016-04-10 03:26:50 +01:00
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{
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2017-09-26 16:56:15 +01:00
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struct si_context *ctx = (struct si_context *)pctx;
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2016-04-10 03:26:50 +01:00
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int i;
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for (i = 0; i < num_scissors; i++)
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2017-09-26 16:56:15 +01:00
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ctx->scissors.states[start_slot + i] = state[i];
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2016-04-10 03:26:50 +01:00
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2017-09-26 17:10:58 +01:00
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if (!ctx->queued.named.rasterizer ||
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!ctx->queued.named.rasterizer->scissor_enable)
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2016-04-10 03:26:50 +01:00
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return;
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2017-09-26 16:56:15 +01:00
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ctx->scissors.dirty_mask |= ((1 << num_scissors) - 1) << start_slot;
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2018-04-09 01:54:02 +01:00
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si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
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2016-04-10 03:26:50 +01:00
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}
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2016-04-13 16:27:02 +01:00
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/* Since the guard band disables clipping, we have to clip per-pixel
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* using a scissor.
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*/
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2017-09-26 16:56:15 +01:00
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static void si_get_scissor_from_viewport(struct si_context *ctx,
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const struct pipe_viewport_state *vp,
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struct si_signed_scissor *scissor)
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2016-04-10 03:26:50 +01:00
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{
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2016-04-15 23:29:05 +01:00
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float tmp, minx, miny, maxx, maxy;
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2016-04-10 03:26:50 +01:00
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/* Convert (-1, -1) and (1, 1) from clip space into window space. */
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2016-04-15 23:29:05 +01:00
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minx = -vp->scale[0] + vp->translate[0];
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miny = -vp->scale[1] + vp->translate[1];
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maxx = vp->scale[0] + vp->translate[0];
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maxy = vp->scale[1] + vp->translate[1];
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2016-04-10 03:26:50 +01:00
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/* Handle inverted viewports. */
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2016-04-15 23:29:05 +01:00
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if (minx > maxx) {
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tmp = minx;
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minx = maxx;
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maxx = tmp;
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2016-04-10 03:26:50 +01:00
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}
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2016-04-15 23:29:05 +01:00
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if (miny > maxy) {
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tmp = miny;
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miny = maxy;
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maxy = tmp;
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2016-04-10 03:26:50 +01:00
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}
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2016-04-15 23:29:05 +01:00
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/* Convert to integer and round up the max bounds. */
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scissor->minx = minx;
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scissor->miny = miny;
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scissor->maxx = ceilf(maxx);
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scissor->maxy = ceilf(maxy);
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2016-04-10 03:26:50 +01:00
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}
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2017-09-26 16:56:15 +01:00
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static void si_clamp_scissor(struct si_context *ctx,
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struct pipe_scissor_state *out,
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struct si_signed_scissor *scissor)
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2016-04-10 03:26:50 +01:00
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{
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2017-09-26 16:56:15 +01:00
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out->minx = CLAMP(scissor->minx, 0, SI_MAX_SCISSOR);
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out->miny = CLAMP(scissor->miny, 0, SI_MAX_SCISSOR);
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out->maxx = CLAMP(scissor->maxx, 0, SI_MAX_SCISSOR);
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out->maxy = CLAMP(scissor->maxy, 0, SI_MAX_SCISSOR);
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2016-04-10 03:26:50 +01:00
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}
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2017-09-26 16:56:15 +01:00
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static void si_clip_scissor(struct pipe_scissor_state *out,
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struct pipe_scissor_state *clip)
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2016-04-10 03:26:50 +01:00
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{
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out->minx = MAX2(out->minx, clip->minx);
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out->miny = MAX2(out->miny, clip->miny);
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out->maxx = MIN2(out->maxx, clip->maxx);
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out->maxy = MIN2(out->maxy, clip->maxy);
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}
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2017-09-26 16:56:15 +01:00
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static void si_scissor_make_union(struct si_signed_scissor *out,
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struct si_signed_scissor *in)
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2016-04-10 03:26:50 +01:00
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{
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out->minx = MIN2(out->minx, in->minx);
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out->miny = MIN2(out->miny, in->miny);
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out->maxx = MAX2(out->maxx, in->maxx);
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out->maxy = MAX2(out->maxy, in->maxy);
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}
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2017-09-26 16:56:15 +01:00
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static void si_emit_one_scissor(struct si_context *ctx,
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2018-06-19 02:07:10 +01:00
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struct radeon_cmdbuf *cs,
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2017-09-26 16:56:15 +01:00
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struct si_signed_scissor *vp_scissor,
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struct pipe_scissor_state *scissor)
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2016-04-10 03:26:50 +01:00
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{
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struct pipe_scissor_state final;
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2017-09-26 16:56:15 +01:00
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if (ctx->vs_disables_clipping_viewport) {
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2016-04-13 16:28:30 +01:00
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final.minx = final.miny = 0;
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2017-09-26 16:56:15 +01:00
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final.maxx = final.maxy = SI_MAX_SCISSOR;
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2016-04-13 16:28:30 +01:00
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} else {
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2017-09-26 16:56:15 +01:00
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si_clamp_scissor(ctx, &final, vp_scissor);
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2016-04-13 16:28:30 +01:00
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}
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2016-04-10 03:26:50 +01:00
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if (scissor)
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2017-09-26 16:56:15 +01:00
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si_clip_scissor(&final, scissor);
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2016-04-10 03:26:50 +01:00
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2018-09-28 23:49:29 +01:00
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/* Workaround for a hw bug on SI that occurs when PA_SU_HARDWARE_-
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* SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
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*/
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if (ctx->chip_class == SI && (final.maxx == 0 || final.maxy == 0)) {
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radeon_emit(cs, S_028250_TL_X(1) |
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S_028250_TL_Y(1) |
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S_028250_WINDOW_OFFSET_DISABLE(1));
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radeon_emit(cs, S_028254_BR_X(1) |
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S_028254_BR_Y(1));
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return;
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}
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2016-04-10 03:26:50 +01:00
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radeon_emit(cs, S_028250_TL_X(final.minx) |
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S_028250_TL_Y(final.miny) |
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S_028250_WINDOW_OFFSET_DISABLE(1));
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radeon_emit(cs, S_028254_BR_X(final.maxx) |
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S_028254_BR_Y(final.maxy));
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}
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/* the range is [-MAX, MAX] */
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2018-04-02 00:58:22 +01:00
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#define SI_MAX_VIEWPORT_RANGE 32768
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2016-04-10 03:26:50 +01:00
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2018-05-31 03:38:05 +01:00
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static void si_emit_guardband(struct si_context *ctx)
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2016-04-10 03:26:50 +01:00
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{
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2018-09-29 01:57:07 +01:00
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const struct si_state_rasterizer *rs = ctx->queued.named.rasterizer;
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2018-09-28 23:49:29 +01:00
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struct si_signed_scissor vp_as_scissor;
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2016-04-10 03:26:50 +01:00
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struct pipe_viewport_state vp;
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float left, top, right, bottom, max_range, guardband_x, guardband_y;
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2017-09-17 10:26:53 +01:00
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float discard_x, discard_y;
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2016-04-10 03:26:50 +01:00
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2018-05-31 03:38:05 +01:00
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if (ctx->vs_writes_viewport_index) {
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/* Shaders can draw to any viewport. Make a union of all
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* viewports. */
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2018-09-28 23:49:29 +01:00
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vp_as_scissor = ctx->viewports.as_scissor[0];
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2018-05-31 03:38:05 +01:00
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for (unsigned i = 1; i < SI_MAX_VIEWPORTS; i++) {
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2018-09-28 23:49:29 +01:00
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si_scissor_make_union(&vp_as_scissor,
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2018-05-31 03:38:05 +01:00
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&ctx->viewports.as_scissor[i]);
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}
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} else {
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2018-09-28 23:49:29 +01:00
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vp_as_scissor = ctx->viewports.as_scissor[0];
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2018-05-31 03:38:05 +01:00
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}
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2018-09-28 23:49:29 +01:00
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/* Determine the optimal hardware screen offset to center the viewport
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* within the viewport range in order to maximize the guardband size.
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*/
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int hw_screen_offset_x = (vp_as_scissor.maxx - vp_as_scissor.minx) / 2;
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int hw_screen_offset_y = (vp_as_scissor.maxy - vp_as_scissor.miny) / 2;
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const unsigned hw_screen_offset_max = 8176;
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/* SI-CI need to align the offset to an ubertile consisting of all SEs. */
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const unsigned hw_screen_offset_alignment =
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ctx->chip_class >= VI ? 16 : MAX2(ctx->screen->se_tile_repeat, 16);
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hw_screen_offset_x = MIN2(hw_screen_offset_x, hw_screen_offset_max);
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hw_screen_offset_y = MIN2(hw_screen_offset_y, hw_screen_offset_max);
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/* Align the screen offset by dropping the low 4 bits. */
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hw_screen_offset_x &= ~(hw_screen_offset_alignment - 1);
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hw_screen_offset_y &= ~(hw_screen_offset_alignment - 1);
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/* Apply the offset to center the viewport and maximize the guardband. */
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vp_as_scissor.minx -= hw_screen_offset_x;
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vp_as_scissor.maxx -= hw_screen_offset_x;
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vp_as_scissor.miny -= hw_screen_offset_y;
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vp_as_scissor.maxy -= hw_screen_offset_y;
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2016-04-10 03:26:50 +01:00
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/* Reconstruct the viewport transformation from the scissor. */
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2018-09-28 23:49:29 +01:00
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vp.translate[0] = (vp_as_scissor.minx + vp_as_scissor.maxx) / 2.0;
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vp.translate[1] = (vp_as_scissor.miny + vp_as_scissor.maxy) / 2.0;
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vp.scale[0] = vp_as_scissor.maxx - vp.translate[0];
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vp.scale[1] = vp_as_scissor.maxy - vp.translate[1];
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2016-04-10 03:26:50 +01:00
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/* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
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2018-09-28 23:49:29 +01:00
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if (vp_as_scissor.minx == vp_as_scissor.maxx)
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2016-04-10 03:26:50 +01:00
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vp.scale[0] = 0.5;
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2018-09-28 23:49:29 +01:00
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if (vp_as_scissor.miny == vp_as_scissor.maxy)
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2016-04-10 03:26:50 +01:00
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vp.scale[1] = 0.5;
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/* Find the biggest guard band that is inside the supported viewport
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* range. The guard band is specified as a horizontal and vertical
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* distance from (0,0) in clip space.
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*
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* This is done by applying the inverse viewport transformation
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* on the viewport limits to get those limits in clip space.
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*
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* Use a limit one pixel smaller to allow for some precision error.
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*/
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2018-04-02 00:58:22 +01:00
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max_range = SI_MAX_VIEWPORT_RANGE - 1;
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2016-04-10 03:26:50 +01:00
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left = (-max_range - vp.translate[0]) / vp.scale[0];
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right = ( max_range - vp.translate[0]) / vp.scale[0];
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top = (-max_range - vp.translate[1]) / vp.scale[1];
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bottom = ( max_range - vp.translate[1]) / vp.scale[1];
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assert(left <= -1 && top <= -1 && right >= 1 && bottom >= 1);
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guardband_x = MIN2(-left, right);
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guardband_y = MIN2(-top, bottom);
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2017-09-17 10:26:53 +01:00
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discard_x = 1.0;
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discard_y = 1.0;
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2018-05-31 04:21:28 +01:00
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if (unlikely(util_prim_is_points_or_lines(ctx->current_rast_prim))) {
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2017-09-17 10:26:53 +01:00
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/* When rendering wide points or lines, we need to be more
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2017-09-26 19:36:10 +01:00
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* conservative about when to discard them entirely. */
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float pixels;
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if (ctx->current_rast_prim == PIPE_PRIM_POINTS)
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pixels = rs->max_point_size;
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else
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pixels = rs->line_width;
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/* Add half the point size / line width */
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discard_x += pixels / (2.0 * vp.scale[0]);
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discard_y += pixels / (2.0 * vp.scale[1]);
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/* Discard primitives that would lie entirely outside the clip
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* region. */
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discard_x = MIN2(discard_x, guardband_x);
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discard_y = MIN2(discard_y, guardband_y);
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2017-09-17 10:26:53 +01:00
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}
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2018-07-17 15:22:03 +01:00
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/* If any of the GB registers is updated, all of them must be updated.
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* R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
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* R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
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*/
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radeon_opt_set_context_reg4(ctx, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ,
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SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ,
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fui(guardband_y), fui(discard_y),
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fui(guardband_x), fui(discard_x));
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2018-09-28 23:49:29 +01:00
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radeon_opt_set_context_reg(ctx, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET,
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SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET,
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S_028234_HW_SCREEN_OFFSET_X(hw_screen_offset_x >> 4) |
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S_028234_HW_SCREEN_OFFSET_Y(hw_screen_offset_y >> 4));
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2018-09-29 01:57:07 +01:00
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radeon_opt_set_context_reg(ctx, R_028BE4_PA_SU_VTX_CNTL,
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|
|
SI_TRACKED_PA_SU_VTX_CNTL,
|
|
|
|
S_028BE4_PIX_CENTER(rs->half_pixel_center) |
|
|
|
|
S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|
|
|
|
|
2018-04-09 02:20:53 +01:00
|
|
|
static void si_emit_scissors(struct si_context *ctx)
|
2016-04-10 03:26:50 +01:00
|
|
|
{
|
2018-06-19 02:07:10 +01:00
|
|
|
struct radeon_cmdbuf *cs = ctx->gfx_cs;
|
2017-09-26 16:56:15 +01:00
|
|
|
struct pipe_scissor_state *states = ctx->scissors.states;
|
|
|
|
unsigned mask = ctx->scissors.dirty_mask;
|
2018-05-31 04:21:28 +01:00
|
|
|
bool scissor_enabled = ctx->queued.named.rasterizer->scissor_enable;
|
2017-09-26 17:10:58 +01:00
|
|
|
|
2016-04-10 03:26:50 +01:00
|
|
|
/* The simple case: Only 1 viewport is active. */
|
2017-09-26 16:56:15 +01:00
|
|
|
if (!ctx->vs_writes_viewport_index) {
|
|
|
|
struct si_signed_scissor *vp = &ctx->viewports.as_scissor[0];
|
2016-04-10 03:26:50 +01:00
|
|
|
|
|
|
|
if (!(mask & 1))
|
|
|
|
return;
|
|
|
|
|
|
|
|
radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL, 2);
|
2017-09-26 16:56:15 +01:00
|
|
|
si_emit_one_scissor(ctx, cs, vp, scissor_enabled ? &states[0] : NULL);
|
|
|
|
ctx->scissors.dirty_mask &= ~1; /* clear one bit */
|
2016-04-10 03:26:50 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (mask) {
|
|
|
|
int start, count, i;
|
|
|
|
|
|
|
|
u_bit_scan_consecutive_range(&mask, &start, &count);
|
|
|
|
|
|
|
|
radeon_set_context_reg_seq(cs, R_028250_PA_SC_VPORT_SCISSOR_0_TL +
|
|
|
|
start * 4 * 2, count * 2);
|
|
|
|
for (i = start; i < start+count; i++) {
|
2017-09-26 16:56:15 +01:00
|
|
|
si_emit_one_scissor(ctx, cs, &ctx->viewports.as_scissor[i],
|
|
|
|
scissor_enabled ? &states[i] : NULL);
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|
|
|
|
}
|
2017-09-26 16:56:15 +01:00
|
|
|
ctx->scissors.dirty_mask = 0;
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|
|
|
|
|
2017-09-26 16:56:15 +01:00
|
|
|
static void si_set_viewport_states(struct pipe_context *pctx,
|
|
|
|
unsigned start_slot,
|
|
|
|
unsigned num_viewports,
|
|
|
|
const struct pipe_viewport_state *state)
|
2016-04-10 03:26:50 +01:00
|
|
|
{
|
2017-09-26 16:56:15 +01:00
|
|
|
struct si_context *ctx = (struct si_context *)pctx;
|
2016-08-26 16:26:43 +01:00
|
|
|
unsigned mask;
|
2016-04-10 03:26:50 +01:00
|
|
|
int i;
|
|
|
|
|
|
|
|
for (i = 0; i < num_viewports; i++) {
|
|
|
|
unsigned index = start_slot + i;
|
|
|
|
|
2017-09-26 16:56:15 +01:00
|
|
|
ctx->viewports.states[index] = state[i];
|
|
|
|
si_get_scissor_from_viewport(ctx, &state[i],
|
|
|
|
&ctx->viewports.as_scissor[index]);
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|
|
|
|
|
2016-08-26 16:26:43 +01:00
|
|
|
mask = ((1 << num_viewports) - 1) << start_slot;
|
2017-09-26 16:56:15 +01:00
|
|
|
ctx->viewports.dirty_mask |= mask;
|
|
|
|
ctx->viewports.depth_range_dirty_mask |= mask;
|
|
|
|
ctx->scissors.dirty_mask |= mask;
|
2018-04-09 01:54:02 +01:00
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
|
2018-05-31 03:38:05 +01:00
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
|
2018-04-09 01:54:02 +01:00
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|
|
|
|
|
2017-09-26 16:56:15 +01:00
|
|
|
static void si_emit_one_viewport(struct si_context *ctx,
|
|
|
|
struct pipe_viewport_state *state)
|
2016-08-26 10:53:47 +01:00
|
|
|
{
|
2018-06-19 02:07:10 +01:00
|
|
|
struct radeon_cmdbuf *cs = ctx->gfx_cs;
|
2016-08-26 10:53:47 +01:00
|
|
|
|
|
|
|
radeon_emit(cs, fui(state->scale[0]));
|
|
|
|
radeon_emit(cs, fui(state->translate[0]));
|
|
|
|
radeon_emit(cs, fui(state->scale[1]));
|
|
|
|
radeon_emit(cs, fui(state->translate[1]));
|
|
|
|
radeon_emit(cs, fui(state->scale[2]));
|
|
|
|
radeon_emit(cs, fui(state->translate[2]));
|
|
|
|
}
|
|
|
|
|
2017-09-26 16:56:15 +01:00
|
|
|
static void si_emit_viewports(struct si_context *ctx)
|
2016-04-10 03:26:50 +01:00
|
|
|
{
|
2018-06-19 02:07:10 +01:00
|
|
|
struct radeon_cmdbuf *cs = ctx->gfx_cs;
|
2017-09-26 16:56:15 +01:00
|
|
|
struct pipe_viewport_state *states = ctx->viewports.states;
|
|
|
|
unsigned mask = ctx->viewports.dirty_mask;
|
2016-04-10 03:26:50 +01:00
|
|
|
|
|
|
|
/* The simple case: Only 1 viewport is active. */
|
2017-09-26 16:56:15 +01:00
|
|
|
if (!ctx->vs_writes_viewport_index) {
|
2016-04-10 03:26:50 +01:00
|
|
|
if (!(mask & 1))
|
|
|
|
return;
|
|
|
|
|
|
|
|
radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE, 6);
|
2017-09-26 16:56:15 +01:00
|
|
|
si_emit_one_viewport(ctx, &states[0]);
|
|
|
|
ctx->viewports.dirty_mask &= ~1; /* clear one bit */
|
2016-04-10 03:26:50 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (mask) {
|
|
|
|
int start, count, i;
|
|
|
|
|
|
|
|
u_bit_scan_consecutive_range(&mask, &start, &count);
|
|
|
|
|
|
|
|
radeon_set_context_reg_seq(cs, R_02843C_PA_CL_VPORT_XSCALE +
|
|
|
|
start * 4 * 6, count * 6);
|
2016-08-26 10:53:47 +01:00
|
|
|
for (i = start; i < start+count; i++)
|
2017-09-26 16:56:15 +01:00
|
|
|
si_emit_one_viewport(ctx, &states[i]);
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|
2017-09-26 16:56:15 +01:00
|
|
|
ctx->viewports.dirty_mask = 0;
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|
|
|
|
|
2017-10-05 23:19:22 +01:00
|
|
|
static inline void
|
|
|
|
si_viewport_zmin_zmax(const struct pipe_viewport_state *vp, bool halfz,
|
|
|
|
bool window_space_position, float *zmin, float *zmax)
|
|
|
|
{
|
|
|
|
if (window_space_position) {
|
|
|
|
*zmin = 0;
|
|
|
|
*zmax = 1;
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
util_viewport_zmin_zmax(vp, halfz, zmin, zmax);
|
|
|
|
}
|
|
|
|
|
2017-09-26 16:56:15 +01:00
|
|
|
static void si_emit_depth_ranges(struct si_context *ctx)
|
2016-04-10 03:26:50 +01:00
|
|
|
{
|
2018-06-19 02:07:10 +01:00
|
|
|
struct radeon_cmdbuf *cs = ctx->gfx_cs;
|
2017-09-26 16:56:15 +01:00
|
|
|
struct pipe_viewport_state *states = ctx->viewports.states;
|
|
|
|
unsigned mask = ctx->viewports.depth_range_dirty_mask;
|
2018-05-31 04:21:28 +01:00
|
|
|
bool clip_halfz = ctx->queued.named.rasterizer->clip_halfz;
|
2017-10-05 23:19:22 +01:00
|
|
|
bool window_space = ctx->vs_disables_clipping_viewport;
|
2016-08-26 16:26:43 +01:00
|
|
|
float zmin, zmax;
|
|
|
|
|
|
|
|
/* The simple case: Only 1 viewport is active. */
|
2017-09-26 16:56:15 +01:00
|
|
|
if (!ctx->vs_writes_viewport_index) {
|
2016-08-26 16:26:43 +01:00
|
|
|
if (!(mask & 1))
|
|
|
|
return;
|
|
|
|
|
2017-10-05 23:19:22 +01:00
|
|
|
si_viewport_zmin_zmax(&states[0], clip_halfz, window_space,
|
|
|
|
&zmin, &zmax);
|
2016-08-26 16:26:43 +01:00
|
|
|
|
|
|
|
radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0, 2);
|
|
|
|
radeon_emit(cs, fui(zmin));
|
|
|
|
radeon_emit(cs, fui(zmax));
|
2017-09-26 16:56:15 +01:00
|
|
|
ctx->viewports.depth_range_dirty_mask &= ~1; /* clear one bit */
|
2016-08-26 16:26:43 +01:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
while (mask) {
|
|
|
|
int start, count, i;
|
|
|
|
|
|
|
|
u_bit_scan_consecutive_range(&mask, &start, &count);
|
|
|
|
|
|
|
|
radeon_set_context_reg_seq(cs, R_0282D0_PA_SC_VPORT_ZMIN_0 +
|
|
|
|
start * 4 * 2, count * 2);
|
|
|
|
for (i = start; i < start+count; i++) {
|
2017-10-05 23:19:22 +01:00
|
|
|
si_viewport_zmin_zmax(&states[i], clip_halfz, window_space,
|
|
|
|
&zmin, &zmax);
|
2016-08-26 16:26:43 +01:00
|
|
|
radeon_emit(cs, fui(zmin));
|
|
|
|
radeon_emit(cs, fui(zmax));
|
|
|
|
}
|
|
|
|
}
|
2017-09-26 16:56:15 +01:00
|
|
|
ctx->viewports.depth_range_dirty_mask = 0;
|
2016-08-26 16:26:43 +01:00
|
|
|
}
|
|
|
|
|
2018-04-09 02:20:53 +01:00
|
|
|
static void si_emit_viewport_states(struct si_context *ctx)
|
2016-08-26 16:26:43 +01:00
|
|
|
{
|
2017-09-26 16:56:15 +01:00
|
|
|
si_emit_viewports(ctx);
|
|
|
|
si_emit_depth_ranges(ctx);
|
2016-08-26 16:26:43 +01:00
|
|
|
}
|
|
|
|
|
2016-04-10 03:26:50 +01:00
|
|
|
/**
|
2017-10-05 23:14:17 +01:00
|
|
|
* This reacts to 2 state changes:
|
|
|
|
* - VS.writes_viewport_index
|
|
|
|
* - VS output position in window space (enable/disable)
|
|
|
|
*
|
2016-04-10 03:26:50 +01:00
|
|
|
* Normally, we only emit 1 viewport and 1 scissor if no shader is using
|
|
|
|
* the VIEWPORT_INDEX output, and emitting the other viewports and scissors
|
|
|
|
* is delayed. When a shader with VIEWPORT_INDEX appears, this should be
|
|
|
|
* called to emit the rest.
|
|
|
|
*/
|
2017-10-05 23:14:17 +01:00
|
|
|
void si_update_vs_viewport_state(struct si_context *ctx)
|
2016-04-10 03:26:50 +01:00
|
|
|
{
|
2017-09-26 17:00:21 +01:00
|
|
|
struct tgsi_shader_info *info = si_get_vs_info(ctx);
|
2016-04-13 16:28:30 +01:00
|
|
|
bool vs_window_space;
|
|
|
|
|
2016-04-10 03:26:50 +01:00
|
|
|
if (!info)
|
|
|
|
return;
|
|
|
|
|
2016-04-13 16:28:30 +01:00
|
|
|
/* When the VS disables clipping and viewport transformation. */
|
|
|
|
vs_window_space =
|
|
|
|
info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
|
|
|
|
|
2017-09-26 16:56:15 +01:00
|
|
|
if (ctx->vs_disables_clipping_viewport != vs_window_space) {
|
|
|
|
ctx->vs_disables_clipping_viewport = vs_window_space;
|
|
|
|
ctx->scissors.dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
|
2017-10-05 23:19:22 +01:00
|
|
|
ctx->viewports.depth_range_dirty_mask = (1 << SI_MAX_VIEWPORTS) - 1;
|
2018-04-09 01:54:02 +01:00
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
|
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
|
2016-04-13 16:28:30 +01:00
|
|
|
}
|
|
|
|
|
|
|
|
/* Viewport index handling. */
|
2018-05-31 03:38:05 +01:00
|
|
|
if (ctx->vs_writes_viewport_index == info->writes_viewport_index)
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* This changes how the guardband is computed. */
|
2017-09-26 16:56:15 +01:00
|
|
|
ctx->vs_writes_viewport_index = info->writes_viewport_index;
|
2018-05-31 03:38:05 +01:00
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.guardband);
|
|
|
|
|
2017-09-26 16:56:15 +01:00
|
|
|
if (!ctx->vs_writes_viewport_index)
|
2016-04-10 03:26:50 +01:00
|
|
|
return;
|
|
|
|
|
2017-09-26 16:56:15 +01:00
|
|
|
if (ctx->scissors.dirty_mask)
|
2018-04-09 01:54:02 +01:00
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.scissors);
|
2016-08-26 16:26:43 +01:00
|
|
|
|
2017-09-26 16:56:15 +01:00
|
|
|
if (ctx->viewports.dirty_mask ||
|
|
|
|
ctx->viewports.depth_range_dirty_mask)
|
2018-04-09 01:54:02 +01:00
|
|
|
si_mark_atom_dirty(ctx, &ctx->atoms.s.viewports);
|
2016-04-10 03:26:50 +01:00
|
|
|
}
|
|
|
|
|
2018-08-06 09:20:30 +01:00
|
|
|
static void si_emit_window_rectangles(struct si_context *sctx)
|
|
|
|
{
|
|
|
|
/* There are four clipping rectangles. Their corner coordinates are inclusive.
|
|
|
|
* Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
|
|
|
|
* on whether the pixel is inside cliprects 0-3, respectively. For example,
|
|
|
|
* if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
|
|
|
|
* the number 3 (binary 0011).
|
|
|
|
*
|
|
|
|
* If CLIPRECT_RULE & (1 << number), the pixel is rasterized.
|
|
|
|
*/
|
|
|
|
struct radeon_cmdbuf *cs = sctx->gfx_cs;
|
|
|
|
static const unsigned outside[4] = {
|
|
|
|
/* outside rectangle 0 */
|
|
|
|
V_02820C_OUT |
|
|
|
|
V_02820C_IN_1 |
|
|
|
|
V_02820C_IN_2 |
|
|
|
|
V_02820C_IN_21 |
|
|
|
|
V_02820C_IN_3 |
|
|
|
|
V_02820C_IN_31 |
|
|
|
|
V_02820C_IN_32 |
|
|
|
|
V_02820C_IN_321,
|
|
|
|
/* outside rectangles 0, 1 */
|
|
|
|
V_02820C_OUT |
|
|
|
|
V_02820C_IN_2 |
|
|
|
|
V_02820C_IN_3 |
|
|
|
|
V_02820C_IN_32,
|
|
|
|
/* outside rectangles 0, 1, 2 */
|
|
|
|
V_02820C_OUT |
|
|
|
|
V_02820C_IN_3,
|
|
|
|
/* outside rectangles 0, 1, 2, 3 */
|
|
|
|
V_02820C_OUT,
|
|
|
|
};
|
|
|
|
const unsigned disabled = 0xffff; /* all inside and outside cases */
|
|
|
|
unsigned num_rectangles = sctx->num_window_rectangles;
|
|
|
|
struct pipe_scissor_state *rects = sctx->window_rectangles;
|
|
|
|
unsigned rule;
|
|
|
|
|
|
|
|
assert(num_rectangles <= 4);
|
|
|
|
|
|
|
|
if (num_rectangles == 0)
|
|
|
|
rule = disabled;
|
|
|
|
else if (sctx->window_rectangles_include)
|
|
|
|
rule = ~outside[num_rectangles - 1];
|
|
|
|
else
|
|
|
|
rule = outside[num_rectangles - 1];
|
|
|
|
|
|
|
|
radeon_opt_set_context_reg(sctx, R_02820C_PA_SC_CLIPRECT_RULE,
|
|
|
|
SI_TRACKED_PA_SC_CLIPRECT_RULE, rule);
|
|
|
|
if (num_rectangles == 0)
|
|
|
|
return;
|
|
|
|
|
|
|
|
radeon_set_context_reg_seq(cs, R_028210_PA_SC_CLIPRECT_0_TL,
|
|
|
|
num_rectangles * 2);
|
|
|
|
for (unsigned i = 0; i < num_rectangles; i++) {
|
|
|
|
radeon_emit(cs, S_028210_TL_X(rects[i].minx) |
|
|
|
|
S_028210_TL_Y(rects[i].miny));
|
|
|
|
radeon_emit(cs, S_028214_BR_X(rects[i].maxx) |
|
|
|
|
S_028214_BR_Y(rects[i].maxy));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void si_set_window_rectangles(struct pipe_context *ctx,
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boolean include,
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unsigned num_rectangles,
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const struct pipe_scissor_state *rects)
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{
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struct si_context *sctx = (struct si_context *)ctx;
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sctx->num_window_rectangles = num_rectangles;
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sctx->window_rectangles_include = include;
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if (num_rectangles) {
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memcpy(sctx->window_rectangles, rects,
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sizeof(*rects) * num_rectangles);
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}
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si_mark_atom_dirty(sctx, &sctx->atoms.s.window_rectangles);
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}
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2017-09-26 16:56:15 +01:00
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void si_init_viewport_functions(struct si_context *ctx)
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2016-04-10 03:26:50 +01:00
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{
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2018-05-31 03:38:05 +01:00
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ctx->atoms.s.guardband.emit = si_emit_guardband;
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2018-04-09 01:54:02 +01:00
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ctx->atoms.s.scissors.emit = si_emit_scissors;
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ctx->atoms.s.viewports.emit = si_emit_viewport_states;
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2018-08-06 09:20:30 +01:00
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ctx->atoms.s.window_rectangles.emit = si_emit_window_rectangles;
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2016-04-10 03:26:50 +01:00
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2018-04-02 00:44:25 +01:00
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ctx->b.set_scissor_states = si_set_scissor_states;
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ctx->b.set_viewport_states = si_set_viewport_states;
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2018-08-06 09:20:30 +01:00
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ctx->b.set_window_rectangles = si_set_window_rectangles;
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2016-04-10 03:26:50 +01:00
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}
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