radeonsi: remove unused atom parameter from si_atom::emit

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
This commit is contained in:
Marek Olšák 2018-04-08 21:20:53 -04:00
parent de344209ad
commit 3160ee876a
10 changed files with 26 additions and 36 deletions

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@ -864,8 +864,7 @@ static void si_launch_grid(
si_emit_compute_shader_pointers(sctx);
if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond)) {
sctx->atoms.s.render_cond.emit(sctx,
&sctx->atoms.s.render_cond);
sctx->atoms.s.render_cond.emit(sctx);
si_set_atom_dirty(sctx, &sctx->atoms.s.render_cond, false);
}

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@ -2153,8 +2153,7 @@ static void si_emit_global_shader_pointers(struct si_context *sctx,
R_00B530_SPI_SHADER_USER_DATA_LS_0);
}
void si_emit_graphics_shader_pointers(struct si_context *sctx,
struct si_atom *atom)
void si_emit_graphics_shader_pointers(struct si_context *sctx)
{
uint32_t *sh_base = sctx->shader_pointers.sh_base;

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@ -936,8 +936,7 @@ static void emit_set_predicate(struct si_context *ctx,
RADEON_PRIO_QUERY);
}
static void si_emit_query_predication(struct si_context *ctx,
struct si_atom *atom)
static void si_emit_query_predication(struct si_context *ctx)
{
struct si_query_hw *query = (struct si_query_hw *)ctx->render_cond;
struct si_query_buffer *qbuf;

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@ -64,7 +64,7 @@ static unsigned si_pack_float_12p4(float x)
* CB_TARGET_MASK is emitted here to avoid a hang with dual source blending
* if there is not enough PS outputs.
*/
static void si_emit_cb_render_state(struct si_context *sctx, struct si_atom *atom)
static void si_emit_cb_render_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_state_blend *blend = sctx->queued.named.blend;
@ -697,7 +697,7 @@ static void si_set_blend_color(struct pipe_context *ctx,
si_mark_atom_dirty(sctx, &sctx->atoms.s.blend_color);
}
static void si_emit_blend_color(struct si_context *sctx, struct si_atom *atom)
static void si_emit_blend_color(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
@ -731,7 +731,7 @@ static void si_set_clip_state(struct pipe_context *ctx,
pipe_resource_reference(&cb.buffer, NULL);
}
static void si_emit_clip_state(struct si_context *sctx, struct si_atom *atom)
static void si_emit_clip_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
@ -739,7 +739,7 @@ static void si_emit_clip_state(struct si_context *sctx, struct si_atom *atom)
radeon_emit_array(cs, (uint32_t*)sctx->clip_state.state.ucp, 6*4);
}
static void si_emit_clip_regs(struct si_context *sctx, struct si_atom *atom)
static void si_emit_clip_regs(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_shader *vs = si_get_vs_state(sctx);
@ -1053,7 +1053,7 @@ static void si_delete_rs_state(struct pipe_context *ctx, void *state)
/*
* infeered state between dsa and stencil ref
*/
static void si_emit_stencil_ref(struct si_context *sctx, struct si_atom *atom)
static void si_emit_stencil_ref(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct pipe_stencil_ref *ref = &sctx->stencil_ref.state;
@ -1341,7 +1341,7 @@ void si_save_qbo_state(struct si_context *sctx, struct si_qbo_state *st)
si_get_shader_buffers(sctx, PIPE_SHADER_COMPUTE, 0, 3, st->saved_ssbo);
}
static void si_emit_db_render_state(struct si_context *sctx, struct si_atom *state)
static void si_emit_db_render_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
@ -2933,7 +2933,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx,
}
}
static void si_emit_framebuffer_state(struct si_context *sctx, struct si_atom *atom)
static void si_emit_framebuffer_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct pipe_framebuffer_state *state = &sctx->framebuffer.state;
@ -3190,8 +3190,7 @@ static void si_emit_framebuffer_state(struct si_context *sctx, struct si_atom *a
sctx->framebuffer.dirty_zsbuf = false;
}
static void si_emit_msaa_sample_locs(struct si_context *sctx,
struct si_atom *atom)
static void si_emit_msaa_sample_locs(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
unsigned nr_samples = sctx->framebuffer.nr_samples;
@ -3302,7 +3301,7 @@ static bool si_out_of_order_rasterization(struct si_context *sctx)
return true;
}
static void si_emit_msaa_config(struct si_context *sctx, struct si_atom *atom)
static void si_emit_msaa_config(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
unsigned num_tile_pipes = sctx->screen->info.num_tile_pipes;
@ -4158,7 +4157,7 @@ static void si_set_sample_mask(struct pipe_context *ctx, unsigned sample_mask)
si_mark_atom_dirty(sctx, &sctx->atoms.s.sample_mask);
}
static void si_emit_sample_mask(struct si_context *sctx, struct si_atom *atom)
static void si_emit_sample_mask(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
unsigned mask = sctx->sample_mask;

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@ -49,7 +49,7 @@ struct si_qbo_state;
* command buffer (AKA indirect buffer, AKA IB, AKA command stream, AKA CS).
*/
struct si_atom {
void (*emit)(struct si_context *ctx, struct si_atom *state);
void (*emit)(struct si_context *ctx);
};
struct si_state_blend {
@ -361,8 +361,7 @@ void si_upload_const_buffer(struct si_context *sctx, struct r600_resource **rbuf
void si_update_all_texture_descriptors(struct si_context *sctx);
void si_shader_change_notify(struct si_context *sctx);
void si_update_needs_color_decompress_masks(struct si_context *sctx);
void si_emit_graphics_shader_pointers(struct si_context *sctx,
struct si_atom *atom);
void si_emit_graphics_shader_pointers(struct si_context *sctx);
void si_emit_compute_shader_pointers(struct si_context *sctx);
void si_set_rw_buffer(struct si_context *sctx,
uint slot, const struct pipe_constant_buffer *input);
@ -411,7 +410,7 @@ void si_set_occlusion_query_state(struct si_context *sctx,
bool old_perfect_enable);
/* si_state_binning.c */
void si_emit_dpbb_state(struct si_context *sctx, struct si_atom *state);
void si_emit_dpbb_state(struct si_context *sctx);
/* si_state_shaders.c */
bool si_update_shaders(struct si_context *sctx);

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@ -334,7 +334,7 @@ static void si_emit_dpbb_disable(struct si_context *sctx)
S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF));
}
void si_emit_dpbb_state(struct si_context *sctx, struct si_atom *state)
void si_emit_dpbb_state(struct si_context *sctx)
{
struct si_screen *sscreen = sctx->screen;
struct si_state_blend *blend = sctx->queued.named.blend;

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@ -1181,11 +1181,9 @@ static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_i
{
/* Emit state atoms. */
unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
while (mask) {
struct si_atom *atom = &sctx->atoms.array[u_bit_scan(&mask)];
while (mask)
sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
atom->emit(sctx, atom);
}
sctx->dirty_atoms &= skip_atom_mask;
/* Emit states. */
@ -1447,7 +1445,7 @@ void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
/* <-- CUs are idle here. */
if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
sctx->atoms.s.render_cond.emit(sctx, NULL);
sctx->atoms.s.render_cond.emit(sctx);
sctx->dirty_atoms = 0;
si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset);

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@ -2598,7 +2598,7 @@ static unsigned si_get_ps_input_cntl(struct si_context *sctx,
return ps_input_cntl;
}
static void si_emit_spi_map(struct si_context *sctx, struct si_atom *atom)
static void si_emit_spi_map(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_shader *ps = sctx->ps_shader.current;
@ -3328,8 +3328,7 @@ bool si_update_shaders(struct si_context *sctx)
return true;
}
static void si_emit_scratch_state(struct si_context *sctx,
struct si_atom *atom)
static void si_emit_scratch_state(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;

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@ -254,7 +254,7 @@ static void si_flush_vgt_streamout(struct si_context *sctx)
radeon_emit(cs, 4); /* poll interval */
}
static void si_emit_streamout_begin(struct si_context *sctx, struct si_atom *atom)
static void si_emit_streamout_begin(struct si_context *sctx)
{
struct radeon_winsys_cs *cs = sctx->gfx_cs;
struct si_streamout_target **t = sctx->streamout.targets;
@ -356,8 +356,7 @@ void si_emit_streamout_end(struct si_context *sctx)
* are no buffers bound.
*/
static void si_emit_streamout_enable(struct si_context *sctx,
struct si_atom *atom)
static void si_emit_streamout_enable(struct si_context *sctx)
{
radeon_set_context_reg_seq(sctx->gfx_cs, R_028B94_VGT_STRMOUT_CONFIG, 2);
radeon_emit(sctx->gfx_cs,

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@ -210,7 +210,7 @@ static void si_emit_guardband(struct si_context *ctx,
radeon_emit(cs, fui(discard_x)); /* R_028BF4_PA_CL_GB_HORZ_DISC_ADJ */
}
static void si_emit_scissors(struct si_context *ctx, struct si_atom *atom)
static void si_emit_scissors(struct si_context *ctx)
{
struct radeon_winsys_cs *cs = ctx->gfx_cs;
struct pipe_scissor_state *states = ctx->scissors.states;
@ -382,8 +382,7 @@ static void si_emit_depth_ranges(struct si_context *ctx)
ctx->viewports.depth_range_dirty_mask = 0;
}
static void si_emit_viewport_states(struct si_context *ctx,
struct si_atom *atom)
static void si_emit_viewport_states(struct si_context *ctx)
{
si_emit_viewports(ctx);
si_emit_depth_ranges(ctx);