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radeonsi: move si_shader_info::stage into si_shader_selector 

This will help me see all places where we use "info", which will
be moved from si_shader_selector to shader variants.

Acked-by: Pierre-Eric Pelloux-Prayer <pierre-eric.pelloux-prayer@amd.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14414>
This commit is contained in:
Marek Olšák 2022-01-04 14:41:46 -05:00 committed by Marge Bot
parent 8de5b11b29
commit 4e8b8555c6
11 changed files with 154 additions and 160 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

18
src/gallium/drivers/radeonsi/gfx10_shader_ngg.c
View File

@ -120,7 +120,7 @@ bool gfx10_ngg_export_prim_early(struct si_shader *shader)
assert(shader->key.ge.as_ngg && !shader->key.ge.as_es);
return sel->info.stage != MESA_SHADER_GEOMETRY &&
return sel->stage != MESA_SHADER_GEOMETRY &&
!gfx10_ngg_writes_user_edgeflags(shader);
}
@ -616,15 +616,15 @@ static unsigned ngg_nogs_vertex_size(struct si_shader *shader)
* to the ES thread of the provoking vertex. All ES threads
* load and export PrimitiveID for their thread.
*/
if (shader->selector->info.stage == MESA_SHADER_VERTEX && shader->key.ge.mono.u.vs_export_prim_id)
if (shader->selector->stage == MESA_SHADER_VERTEX && shader->key.ge.mono.u.vs_export_prim_id)
lds_vertex_size = MAX2(lds_vertex_size, 1);
if (shader->key.ge.opt.ngg_culling) {
if (shader->selector->info.stage == MESA_SHADER_VERTEX) {
if (shader->selector->stage == MESA_SHADER_VERTEX) {
STATIC_ASSERT(lds_instance_id + 1 == 7);
lds_vertex_size = MAX2(lds_vertex_size, 7);
} else {
assert(shader->selector->info.stage == MESA_SHADER_TESS_EVAL);
assert(shader->selector->stage == MESA_SHADER_TESS_EVAL);
if (shader->selector->info.uses_primid || shader->key.ge.mono.u.vs_export_prim_id) {
STATIC_ASSERT(lds_tes_patch_id + 2 == 9); /* +1 for LDS padding */
@ -926,8 +926,8 @@ void gfx10_emit_ngg_culling_epilogue(struct ac_shader_abi *abi)
assert(shader->key.ge.opt.ngg_culling);
assert(shader->key.ge.as_ngg);
assert(sel->info.stage == MESA_SHADER_VERTEX ||
(sel->info.stage == MESA_SHADER_TESS_EVAL && !shader->key.ge.as_es));
assert(sel->stage == MESA_SHADER_VERTEX ||
(sel->stage == MESA_SHADER_TESS_EVAL && !shader->key.ge.as_es));
LLVMValueRef es_vtxptr = ngg_nogs_vertex_ptr(ctx, gfx10_get_thread_id_in_tg(ctx));
LLVMValueRef packed_data = ctx->ac.i32_0;
@ -2169,7 +2169,7 @@ unsigned gfx10_ngg_get_scratch_dw_size(struct si_shader *shader)
{
const struct si_shader_selector *sel = shader->selector;
if (sel->info.stage == MESA_SHADER_GEOMETRY && sel->info.enabled_streamout_buffer_mask)
if (sel->stage == MESA_SHADER_GEOMETRY && sel->info.enabled_streamout_buffer_mask)
return 44;
return 8;
@ -2186,7 +2186,7 @@ bool gfx10_ngg_calculate_subgroup_info(struct si_shader *shader)
const struct si_shader_selector *gs_sel = shader->selector;
const struct si_shader_selector *es_sel =
shader->previous_stage_sel ? shader->previous_stage_sel : gs_sel;
const gl_shader_stage gs_stage = gs_sel->info.stage;
const gl_shader_stage gs_stage = gs_sel->stage;
const unsigned gs_num_invocations = MAX2(gs_sel->info.base.gs.invocations, 1);
const unsigned input_prim = si_get_input_prim(gs_sel, &shader->key);
const bool use_adjacency =
@ -2231,7 +2231,7 @@ retry_select_mode:
gsprim_lds_size = (gs_sel->info.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
if (gsprim_lds_size > target_lds_size && !force_multi_cycling) {
if (gs_sel->tess_turns_off_ngg || es_sel->info.stage != MESA_SHADER_TESS_EVAL) {
if (gs_sel->tess_turns_off_ngg || es_sel->stage != MESA_SHADER_TESS_EVAL) {
force_multi_cycling = true;
goto retry_select_mode;
}

2
src/gallium/drivers/radeonsi/si_compute.c
View File

@ -231,7 +231,7 @@ static void *si_create_compute_state(struct pipe_context *ctx, const struct pipe
struct si_shader_selector *sel = &program->sel;
pipe_reference_init(&sel->base.reference, 1);
sel->info.stage = MESA_SHADER_COMPUTE;
sel->stage = MESA_SHADER_COMPUTE;
sel->screen = sscreen;
sel->const_and_shader_buf_descriptors_index =
si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_COMPUTE);

4
src/gallium/drivers/radeonsi/si_debug.c
View File

@ -814,7 +814,7 @@ static void si_dump_gfx_descriptors(struct si_context *sctx,
if (!state->cso || !state->current)
return;
si_dump_descriptors(sctx, state->cso->info.stage, &state->cso->info, log);
si_dump_descriptors(sctx, state->cso->stage, &state->cso->info, log);
}
static void si_dump_compute_descriptors(struct si_context *sctx, struct u_log_context *log)
@ -897,7 +897,7 @@ static void si_print_annotated_shader(struct si_shader *shader, struct ac_wave_i
return;
struct si_screen *screen = shader->selector->screen;
gl_shader_stage stage = shader->selector->info.stage;
gl_shader_stage stage = shader->selector->stage;
uint64_t start_addr = shader->bo->gpu_address;
uint64_t end_addr = start_addr + shader->bo->b.b.width0;
unsigned i;

7
src/gallium/drivers/radeonsi/si_pipe.h
View File

@ -1738,13 +1738,6 @@ static inline struct si_shader_ctx_state *si_get_vs(struct si_context *sctx)
sctx->shader.gs.cso ? GS_ON : GS_OFF);
}
static inline struct si_shader_info *si_get_vs_info(struct si_context *sctx)
{
struct si_shader_ctx_state *vs = si_get_vs(sctx);
return vs->cso ? &vs->cso->info : NULL;
}
static inline bool si_can_dump_shader(struct si_screen *sscreen, gl_shader_stage stage)
{
return sscreen->debug_flags & (1 << stage);

88
src/gallium/drivers/radeonsi/si_shader.c
View File

@ -46,18 +46,18 @@ static void si_dump_shader_key(const struct si_shader *shader, FILE *f);
bool si_is_multi_part_shader(struct si_shader *shader)
{
if (shader->selector->screen->info.chip_class <= GFX8 ||
shader->selector->info.stage > MESA_SHADER_GEOMETRY)
shader->selector->stage > MESA_SHADER_GEOMETRY)
return false;
return shader->key.ge.as_ls || shader->key.ge.as_es ||
shader->selector->info.stage == MESA_SHADER_TESS_CTRL ||
shader->selector->info.stage == MESA_SHADER_GEOMETRY;
shader->selector->stage == MESA_SHADER_TESS_CTRL ||
shader->selector->stage == MESA_SHADER_GEOMETRY;
}
/** Whether the shader runs on a merged HW stage (LSHS or ESGS) */
bool si_is_merged_shader(struct si_shader *shader)
{
if (shader->selector->info.stage > MESA_SHADER_GEOMETRY)
if (shader->selector->stage > MESA_SHADER_GEOMETRY)
return false;
return shader->key.ge.as_ngg || si_is_multi_part_shader(shader);
@ -211,7 +211,7 @@ static void declare_streamout_params(struct si_shader_context *ctx,
unsigned si_get_max_workgroup_size(const struct si_shader *shader)
{
switch (shader->selector->info.stage) {
switch (shader->selector->stage) {
case MESA_SHADER_VERTEX:
case MESA_SHADER_TESS_EVAL:
return shader->key.ge.as_ngg ? 128 : 0;
@ -805,15 +805,15 @@ static bool si_shader_binary_open(struct si_screen *screen, struct si_shader *sh
unsigned num_lds_symbols = 0;
if (sel && screen->info.chip_class >= GFX9 && !shader->is_gs_copy_shader &&
(sel->info.stage == MESA_SHADER_GEOMETRY ||
(sel->info.stage <= MESA_SHADER_GEOMETRY && shader->key.ge.as_ngg))) {
(sel->stage == MESA_SHADER_GEOMETRY ||
(sel->stage <= MESA_SHADER_GEOMETRY && shader->key.ge.as_ngg))) {
struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
sym->name = "esgs_ring";
sym->size = shader->gs_info.esgs_ring_size * 4;
sym->align = 64 * 1024;
}
if (sel->info.stage == MESA_SHADER_GEOMETRY && shader->key.ge.as_ngg) {
if (sel->stage == MESA_SHADER_GEOMETRY && shader->key.ge.as_ngg) {
struct ac_rtld_symbol *sym = &lds_symbols[num_lds_symbols++];
sym->name = "ngg_emit";
sym->size = shader->ngg.ngg_emit_size * 4;
@ -826,7 +826,7 @@ static bool si_shader_binary_open(struct si_screen *screen, struct si_shader *sh
{
.halt_at_entry = screen->options.halt_shaders,
},
.shader_type = sel->info.stage,
.shader_type = sel->stage,
.wave_size = shader->wave_size,
.num_parts = num_parts,
.elf_ptrs = part_elfs,
@ -983,7 +983,7 @@ static void si_calculate_max_simd_waves(struct si_shader *shader)
max_simd_waves = sscreen->info.max_wave64_per_simd;
/* Compute LDS usage for PS. */
switch (shader->selector->info.stage) {
switch (shader->selector->stage) {
case MESA_SHADER_FRAGMENT:
/* The minimum usage per wave is (num_inputs * 48). The maximum
* usage is (num_inputs * 48 * 16).
@ -1033,7 +1033,7 @@ void si_shader_dump_stats_for_shader_db(struct si_screen *screen, struct si_shad
static const char *stages[] = {"VS", "TCS", "TES", "GS", "PS", "CS"};
if (screen->options.debug_disassembly)
si_shader_dump_disassembly(screen, &shader->binary, shader->selector->info.stage,
si_shader_dump_disassembly(screen, &shader->binary, shader->selector->stage,
shader->wave_size, debug, "main", NULL);
util_debug_message(debug, SHADER_INFO,
@ -1047,7 +1047,7 @@ void si_shader_dump_stats_for_shader_db(struct si_screen *screen, struct si_shad
shader->selector->info.has_divergent_loop,
shader->selector->info.base.num_inlinable_uniforms,
shader->info.nr_param_exports,
stages[shader->selector->info.stage], shader->wave_size);
stages[shader->selector->stage], shader->wave_size);
}
static void si_shader_dump_stats(struct si_screen *sscreen, struct si_shader *shader, FILE *file,
@ -1055,8 +1055,8 @@ static void si_shader_dump_stats(struct si_screen *sscreen, struct si_shader *sh
{
const struct ac_shader_config *conf = &shader->config;
if (!check_debug_option || si_can_dump_shader(sscreen, shader->selector->info.stage)) {
if (shader->selector->info.stage == MESA_SHADER_FRAGMENT) {
if (!check_debug_option || si_can_dump_shader(sscreen, shader->selector->stage)) {
if (shader->selector->stage == MESA_SHADER_FRAGMENT) {
fprintf(file,
"*** SHADER CONFIG ***\n"
"SPI_PS_INPUT_ADDR = 0x%04x\n"
@ -1084,7 +1084,7 @@ static void si_shader_dump_stats(struct si_screen *sscreen, struct si_shader *sh
const char *si_get_shader_name(const struct si_shader *shader)
{
switch (shader->selector->info.stage) {
switch (shader->selector->stage) {
case MESA_SHADER_VERTEX:
if (shader->key.ge.as_es)
return "Vertex Shader as ES";
@ -1120,7 +1120,7 @@ const char *si_get_shader_name(const struct si_shader *shader)
void si_shader_dump(struct si_screen *sscreen, struct si_shader *shader,
struct util_debug_callback *debug, FILE *file, bool check_debug_option)
{
gl_shader_stage stage = shader->selector->info.stage;
gl_shader_stage stage = shader->selector->stage;
if (!check_debug_option || si_can_dump_shader(sscreen, stage))
si_dump_shader_key(shader, file);
@ -1185,7 +1185,7 @@ static void si_dump_shader_key_vs(const union si_shader_key *key,
static void si_dump_shader_key(const struct si_shader *shader, FILE *f)
{
const union si_shader_key *key = &shader->key;
gl_shader_stage stage = shader->selector->info.stage;
gl_shader_stage stage = shader->selector->stage;
fprintf(f, "SHADER KEY\n");
fprintf(f, " source_sha1 = {");
@ -1223,7 +1223,7 @@ static void si_dump_shader_key(const struct si_shader *shader, FILE *f)
break;
if (shader->selector->screen->info.chip_class >= GFX9 &&
key->ge.part.gs.es->info.stage == MESA_SHADER_VERTEX) {
key->ge.part.gs.es->stage == MESA_SHADER_VERTEX) {
si_dump_shader_key_vs(key, &key->ge.part.gs.vs_prolog, "part.gs.vs_prolog", f);
}
fprintf(f, " mono.u.gs_tri_strip_adj_fix = %u\n", key->ge.mono.u.gs_tri_strip_adj_fix);
@ -1315,7 +1315,7 @@ bool si_vs_needs_prolog(const struct si_shader_selector *sel,
const union si_shader_key *key, bool ngg_cull_shader,
bool is_gs)
{
assert(sel->info.stage == MESA_SHADER_VERTEX);
assert(sel->stage == MESA_SHADER_VERTEX);
/* VGPR initialization fixup for Vega10 and Raven is always done in the
* VS prolog. */
@ -1348,14 +1348,14 @@ void si_get_vs_prolog_key(const struct si_shader_info *info, unsigned num_input_
key->vs_prolog.as_es = shader_out->key.ge.as_es;
key->vs_prolog.as_ngg = shader_out->key.ge.as_ngg;
if (shader_out->selector->info.stage != MESA_SHADER_GEOMETRY &&
if (shader_out->selector->stage != MESA_SHADER_GEOMETRY &&
!ngg_cull_shader && shader_out->key.ge.opt.ngg_culling)
key->vs_prolog.load_vgprs_after_culling = 1;
if (shader_out->selector->info.stage == MESA_SHADER_TESS_CTRL) {
if (shader_out->selector->stage == MESA_SHADER_TESS_CTRL) {
key->vs_prolog.as_ls = 1;
key->vs_prolog.num_merged_next_stage_vgprs = 2;
} else if (shader_out->selector->info.stage == MESA_SHADER_GEOMETRY) {
} else if (shader_out->selector->stage == MESA_SHADER_GEOMETRY) {
key->vs_prolog.as_es = 1;
key->vs_prolog.num_merged_next_stage_vgprs = 5;
} else if (shader_out->key.ge.as_ngg) {
@ -1468,7 +1468,7 @@ struct nir_shader *si_get_nir_shader(struct si_shader_selector *sel,
} else if (sel->nir_binary) {
struct pipe_screen *screen = &sel->screen->b;
const void *options = screen->get_compiler_options(screen, PIPE_SHADER_IR_NIR,
pipe_shader_type_from_mesa(sel->info.stage));
pipe_shader_type_from_mesa(sel->stage));
struct blob_reader blob_reader;
blob_reader_init(&blob_reader, sel->nir_binary, sel->nir_size);
@ -1481,7 +1481,7 @@ struct nir_shader *si_get_nir_shader(struct si_shader_selector *sel,
bool progress = false;
/* Kill outputs according to the shader key. */
if (sel->info.stage <= MESA_SHADER_GEOMETRY)
if (sel->stage <= MESA_SHADER_GEOMETRY)
NIR_PASS(progress, nir, si_nir_kill_outputs, key);
bool inline_uniforms = false;
@ -1594,7 +1594,7 @@ bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compi
/* Dump NIR before doing NIR->LLVM conversion in case the
* conversion fails. */
if (si_can_dump_shader(sscreen, sel->info.stage) &&
if (si_can_dump_shader(sscreen, sel->stage) &&
!(sscreen->debug_flags & DBG(NO_NIR))) {
nir_print_shader(nir, stderr);
si_dump_streamout(&so);
@ -1618,7 +1618,7 @@ bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compi
return false;
/* The GS copy shader is compiled next. */
if (sel->info.stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg) {
if (sel->stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg) {
shader->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, &so, debug);
if (!shader->gs_copy_shader) {
fprintf(stderr, "radeonsi: can't create GS copy shader\n");
@ -1627,13 +1627,13 @@ bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compi
}
/* Compute vs_output_ps_input_cntl. */
if ((sel->info.stage == MESA_SHADER_VERTEX ||
sel->info.stage == MESA_SHADER_TESS_EVAL ||
sel->info.stage == MESA_SHADER_GEOMETRY) &&
if ((sel->stage == MESA_SHADER_VERTEX ||
sel->stage == MESA_SHADER_TESS_EVAL ||
sel->stage == MESA_SHADER_GEOMETRY) &&
!shader->key.ge.as_ls && !shader->key.ge.as_es) {
ubyte *vs_output_param_offset = shader->info.vs_output_param_offset;
if (sel->info.stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg)
if (sel->stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg)
vs_output_param_offset = shader->gs_copy_shader->info.vs_output_param_offset;
/* VS and TES should also set primitive ID output if it's used. */
@ -1664,7 +1664,7 @@ bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compi
}
/* Validate SGPR and VGPR usage for compute to detect compiler bugs. */
if (sel->info.stage == MESA_SHADER_COMPUTE) {
if (sel->stage == MESA_SHADER_COMPUTE) {
unsigned max_vgprs =
sscreen->info.num_physical_wave64_vgprs_per_simd * (shader->wave_size == 32 ? 2 : 1);
unsigned max_sgprs = sscreen->info.num_physical_sgprs_per_simd;
@ -1697,7 +1697,7 @@ bool si_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *compi
shader->info.num_input_sgprs += 1; /* scratch byte offset */
/* Calculate the number of fragment input VGPRs. */
if (sel->info.stage == MESA_SHADER_FRAGMENT) {
if (sel->stage == MESA_SHADER_FRAGMENT) {
shader->info.num_input_vgprs = ac_get_fs_input_vgpr_cnt(
&shader->config, &shader->info.face_vgpr_index, &shader->info.ancillary_vgpr_index,
&shader->info.sample_coverage_vgpr_index);
@ -1810,7 +1810,7 @@ static bool si_get_vs_prolog(struct si_screen *sscreen, struct ac_llvm_compiler
struct si_shader_selector *vs = main_part->selector;
if (!si_vs_needs_prolog(vs, key, &shader->key, false,
shader->selector->info.stage == MESA_SHADER_GEOMETRY))
shader->selector->stage == MESA_SHADER_GEOMETRY))
return true;
/* Get the prolog. */
@ -1875,7 +1875,7 @@ static bool si_shader_select_gs_parts(struct si_screen *sscreen, struct ac_llvm_
else
es_main_part = shader->key.ge.part.gs.es->main_shader_part_es;
if (shader->key.ge.part.gs.es->info.stage == MESA_SHADER_VERTEX &&
if (shader->key.ge.part.gs.es->stage == MESA_SHADER_VERTEX &&
!si_get_vs_prolog(sscreen, compiler, shader, debug, es_main_part,
&shader->key.ge.part.gs.vs_prolog))
return false;
@ -2153,7 +2153,7 @@ void si_fix_resource_usage(struct si_screen *sscreen, struct si_shader *shader)
shader->config.num_sgprs = MAX2(shader->config.num_sgprs, min_sgprs);
if (shader->selector->info.stage == MESA_SHADER_COMPUTE &&
if (shader->selector->stage == MESA_SHADER_COMPUTE &&
si_get_max_workgroup_size(shader) > shader->wave_size) {
si_multiwave_lds_size_workaround(sscreen, &shader->config.lds_size);
}
@ -2206,7 +2206,7 @@ bool si_create_shader_variant(struct si_screen *sscreen, struct ac_llvm_compiler
shader->info = mainp->info;
/* Select prologs and/or epilogs. */
switch (sel->info.stage) {
switch (sel->stage) {
case MESA_SHADER_VERTEX:
if (!si_shader_select_vs_parts(sscreen, compiler, shader, debug))
return false;
@ -2293,40 +2293,40 @@ bool si_create_shader_variant(struct si_screen *sscreen, struct ac_llvm_compiler
si_calculate_max_simd_waves(shader);
}
if (sel->info.stage <= MESA_SHADER_GEOMETRY && shader->key.ge.as_ngg) {
if (sel->stage <= MESA_SHADER_GEOMETRY && shader->key.ge.as_ngg) {
assert(!shader->key.ge.as_es && !shader->key.ge.as_ls);
if (!gfx10_ngg_calculate_subgroup_info(shader)) {
fprintf(stderr, "Failed to compute subgroup info\n");
return false;
}
} else if (sscreen->info.chip_class >= GFX9 && sel->info.stage == MESA_SHADER_GEOMETRY) {
} else if (sscreen->info.chip_class >= GFX9 && sel->stage == MESA_SHADER_GEOMETRY) {
gfx9_get_gs_info(shader->previous_stage_sel, sel, &shader->gs_info);
}
shader->uses_vs_state_provoking_vertex =
sscreen->use_ngg &&
/* Used to convert triangle strips from GS to triangles. */
((sel->info.stage == MESA_SHADER_GEOMETRY &&
((sel->stage == MESA_SHADER_GEOMETRY &&
util_rast_prim_is_triangles(sel->info.base.gs.output_primitive)) ||
(sel->info.stage == MESA_SHADER_VERTEX &&
(sel->stage == MESA_SHADER_VERTEX &&
/* Used to export PrimitiveID from the correct vertex. */
shader->key.ge.mono.u.vs_export_prim_id));
shader->uses_vs_state_outprim = sscreen->use_ngg &&
/* Only used by streamout in vertex shaders. */
sel->info.stage == MESA_SHADER_VERTEX &&
sel->stage == MESA_SHADER_VERTEX &&
sel->info.enabled_streamout_buffer_mask;
if (sel->info.stage == MESA_SHADER_VERTEX) {
if (sel->stage == MESA_SHADER_VERTEX) {
shader->uses_base_instance = sel->info.uses_base_instance ||
shader->key.ge.part.vs.prolog.instance_divisor_is_one ||
shader->key.ge.part.vs.prolog.instance_divisor_is_fetched;
} else if (sel->info.stage == MESA_SHADER_TESS_CTRL) {
} else if (sel->stage == MESA_SHADER_TESS_CTRL) {
shader->uses_base_instance = shader->previous_stage_sel &&
(shader->previous_stage_sel->info.uses_base_instance ||
shader->key.ge.part.tcs.ls_prolog.instance_divisor_is_one ||
shader->key.ge.part.tcs.ls_prolog.instance_divisor_is_fetched);
} else if (sel->info.stage == MESA_SHADER_GEOMETRY) {
} else if (sel->stage == MESA_SHADER_GEOMETRY) {
shader->uses_base_instance = shader->previous_stage_sel &&
(shader->previous_stage_sel->info.uses_base_instance ||
shader->key.ge.part.gs.vs_prolog.instance_divisor_is_one ||

6
src/gallium/drivers/radeonsi/si_shader.h
View File

@ -351,7 +351,6 @@ union si_input_info {
struct si_shader_info {
shader_info base;
gl_shader_stage stage;
uint32_t options; /* bitmask of SI_PROFILE_* */
ubyte num_inputs;
@ -468,6 +467,7 @@ struct si_shader_selector {
struct si_screen *screen;
struct util_queue_fence ready;
struct si_compiler_ctx_state compiler_ctx_state;
gl_shader_stage stage;
simple_mtx_t mutex;
struct si_shader *first_variant; /* immutable after the first variant */
@ -978,7 +978,7 @@ bool gfx10_is_ngg_passthrough(struct si_shader *shader);
static inline struct si_shader **si_get_main_shader_part(struct si_shader_selector *sel,
const union si_shader_key *key)
{
if (sel->info.stage <= MESA_SHADER_GEOMETRY) {
if (sel->stage <= MESA_SHADER_GEOMETRY) {
if (key->ge.as_ls)
return &sel->main_shader_part_ls;
if (key->ge.as_es && key->ge.as_ngg)
@ -1003,7 +1003,7 @@ static inline bool si_shader_uses_bindless_images(struct si_shader_selector *sel
static inline bool gfx10_edgeflags_have_effect(struct si_shader *shader)
{
if (shader->selector->info.stage == MESA_SHADER_VERTEX &&
if (shader->selector->stage == MESA_SHADER_VERTEX &&
!shader->selector->info.base.vs.blit_sgprs_amd &&
!(shader->key.ge.opt.ngg_culling & SI_NGG_CULL_LINES))
return true;

29
src/gallium/drivers/radeonsi/si_shader_info.c
View File

@ -219,8 +219,8 @@ static const nir_src *get_texture_src(nir_tex_instr *instr, nir_tex_src_type typ
return NULL;
}
static void scan_io_usage(struct si_shader_info *info, nir_intrinsic_instr *intr,
bool is_input)
static void scan_io_usage(const nir_shader *nir, struct si_shader_info *info,
nir_intrinsic_instr *intr, bool is_input)
{
unsigned interp = INTERP_MODE_FLAT; /* load_input uses flat shading */
@ -272,10 +272,10 @@ static void scan_io_usage(struct si_shader_info *info, nir_intrinsic_instr *intr
unsigned semantic = 0;
/* VS doesn't have semantics. */
if (info->stage != MESA_SHADER_VERTEX || !is_input)
if (nir->info.stage != MESA_SHADER_VERTEX || !is_input)
semantic = nir_intrinsic_io_semantics(intr).location;
if (info->stage == MESA_SHADER_FRAGMENT && !is_input) {
if (nir->info.stage == MESA_SHADER_FRAGMENT && !is_input) {
/* Never use FRAG_RESULT_COLOR directly. */
if (semantic == FRAG_RESULT_COLOR)
semantic = FRAG_RESULT_DATA0;
@ -357,7 +357,7 @@ static void scan_io_usage(struct si_shader_info *info, nir_intrinsic_instr *intr
info->output_usagemask[loc] |= mask;
info->num_outputs = MAX2(info->num_outputs, loc + 1);
if (info->stage == MESA_SHADER_FRAGMENT &&
if (nir->info.stage == MESA_SHADER_FRAGMENT &&
semantic >= FRAG_RESULT_DATA0 && semantic <= FRAG_RESULT_DATA7) {
unsigned index = semantic - FRAG_RESULT_DATA0;
@ -559,13 +559,13 @@ static void scan_instruction(const struct nir_shader *nir, struct si_shader_info
case nir_intrinsic_load_per_vertex_input:
case nir_intrinsic_load_input_vertex:
case nir_intrinsic_load_interpolated_input:
scan_io_usage(info, intr, true);
scan_io_usage(nir, info, intr, true);
break;
case nir_intrinsic_load_output:
case nir_intrinsic_load_per_vertex_output:
case nir_intrinsic_store_output:
case nir_intrinsic_store_per_vertex_output:
scan_io_usage(info, intr, false);
scan_io_usage(nir, info, intr, false);
break;
case nir_intrinsic_load_deref:
case nir_intrinsic_store_deref:
@ -587,7 +587,6 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
{
memset(info, 0, sizeof(*info));
info->base = nir->info;
info->stage = nir->info.stage;
/* Get options from shader profiles. */
for (unsigned i = 0; i < ARRAY_SIZE(profiles); i++) {
@ -677,7 +676,7 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
scan_instruction(nir, info, instr);
}
if (info->stage == MESA_SHADER_VERTEX || info->stage == MESA_SHADER_TESS_EVAL) {
if (nir->info.stage == MESA_SHADER_VERTEX || nir->info.stage == MESA_SHADER_TESS_EVAL) {
/* Add the PrimitiveID output, but don't increment num_outputs.
* The driver inserts PrimitiveID only when it's used by the pixel shader,
* and si_emit_spi_map uses this unconditionally when such a pixel shader is used.
@ -733,11 +732,11 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
info->has_divergent_loop = nir_has_divergent_loop((nir_shader*)nir);
if (info->stage == MESA_SHADER_VERTEX ||
info->stage == MESA_SHADER_TESS_CTRL ||
info->stage == MESA_SHADER_TESS_EVAL ||
info->stage == MESA_SHADER_GEOMETRY) {
if (info->stage == MESA_SHADER_TESS_CTRL) {
if (nir->info.stage == MESA_SHADER_VERTEX ||
nir->info.stage == MESA_SHADER_TESS_CTRL ||
nir->info.stage == MESA_SHADER_TESS_EVAL ||
nir->info.stage == MESA_SHADER_GEOMETRY) {
if (nir->info.stage == MESA_SHADER_TESS_CTRL) {
/* Always reserve space for these. */
info->patch_outputs_written |=
(1ull << si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_INNER)) |
@ -767,7 +766,7 @@ void si_nir_scan_shader(struct si_screen *sscreen, const struct nir_shader *nir,
if (nir->info.stage == MESA_SHADER_VERTEX) {
info->num_vs_inputs =
info->stage == MESA_SHADER_VERTEX && !info->base.vs.blit_sgprs_amd ? info->num_inputs : 0;
nir->info.stage == MESA_SHADER_VERTEX && !info->base.vs.blit_sgprs_amd ? info->num_inputs : 0;
unsigned num_vbos_in_sgprs = si_num_vbos_in_user_sgprs_inline(sscreen->info.chip_class);
info->num_vbos_in_user_sgprs = MIN2(info->num_vs_inputs, num_vbos_in_sgprs);

20
src/gallium/drivers/radeonsi/si_shader_llvm.c
View File

@ -847,7 +847,7 @@ bool si_llvm_translate_nir(struct si_shader_context *ctx, struct si_shader *shad
const struct si_shader_info *info = &sel->info;
ctx->shader = shader;
ctx->stage = sel->info.stage;
ctx->stage = sel->stage;
ctx->num_const_buffers = info->base.num_ubos;
ctx->num_shader_buffers = info->base.num_ssbos;
@ -1058,7 +1058,7 @@ static bool si_should_optimize_less(struct ac_llvm_compiler *compiler,
/* For a crazy dEQP test containing 2597 memory opcodes, mostly
* buffer stores. */
return sel->info.stage == MESA_SHADER_COMPUTE && sel->info.num_memory_stores > 1000;
return sel->stage == MESA_SHADER_COMPUTE && sel->info.num_memory_stores > 1000;
}
static void si_optimize_vs_outputs(struct si_shader_context *ctx)
@ -1098,7 +1098,7 @@ bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *
ctx.so = *so;
LLVMValueRef ngg_cull_main_fn = NULL;
if (sel->info.stage <= MESA_SHADER_TESS_EVAL && shader->key.ge.opt.ngg_culling) {
if (sel->stage <= MESA_SHADER_TESS_EVAL && shader->key.ge.opt.ngg_culling) {
if (!si_llvm_translate_nir(&ctx, shader, nir, false, true)) {
si_llvm_dispose(&ctx);
return false;
@ -1112,7 +1112,7 @@ bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *
return false;
}
if (shader->is_monolithic && sel->info.stage == MESA_SHADER_VERTEX) {
if (shader->is_monolithic && sel->stage == MESA_SHADER_VERTEX) {
LLVMValueRef parts[4];
unsigned num_parts = 0;
bool first_is_prolog = false;
@ -1144,7 +1144,7 @@ bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *
parts[num_parts++] = main_fn;
si_build_wrapper_function(&ctx, parts, num_parts, first_is_prolog ? 1 : 0, 0, false);
} else if (shader->is_monolithic && sel->info.stage == MESA_SHADER_TESS_EVAL && ngg_cull_main_fn) {
} else if (shader->is_monolithic && sel->stage == MESA_SHADER_TESS_EVAL && ngg_cull_main_fn) {
LLVMValueRef parts[3], prolog, main_fn = ctx.main_fn;
/* We reuse the VS prolog code for TES just to load the input VGPRs from LDS. */
@ -1163,7 +1163,7 @@ bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *
parts[2] = main_fn;
si_build_wrapper_function(&ctx, parts, 3, 0, 0, false);
} else if (shader->is_monolithic && sel->info.stage == MESA_SHADER_TESS_CTRL) {
} else if (shader->is_monolithic && sel->stage == MESA_SHADER_TESS_CTRL) {
if (sscreen->info.chip_class >= GFX9) {
struct si_shader_selector *ls = shader->key.ge.part.tcs.ls;
LLVMValueRef parts[4];
@ -1232,7 +1232,7 @@ bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *
si_build_wrapper_function(&ctx, parts, 2, 0, 0, false);
}
} else if (shader->is_monolithic && sel->info.stage == MESA_SHADER_GEOMETRY) {
} else if (shader->is_monolithic && sel->stage == MESA_SHADER_GEOMETRY) {
if (ctx.screen->info.chip_class >= GFX9) {
struct si_shader_selector *es = shader->key.ge.part.gs.es;
LLVMValueRef es_prolog = NULL;
@ -1261,7 +1261,7 @@ bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *
es_main = ctx.main_fn;
/* ES prolog */
if (es->info.stage == MESA_SHADER_VERTEX &&
if (es->stage == MESA_SHADER_VERTEX &&
si_vs_needs_prolog(es, &shader->key.ge.part.gs.vs_prolog, &shader->key, false, true)) {
union si_shader_part_key vs_prolog_key;
si_get_vs_prolog_key(&es->info, shader_es.info.num_input_sgprs, false,
@ -1289,7 +1289,7 @@ bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *
} else {
/* Nothing to do for gfx6-8. The shader has only 1 part and it's ctx.main_fn. */
}
} else if (shader->is_monolithic && sel->info.stage == MESA_SHADER_FRAGMENT) {
} else if (shader->is_monolithic && sel->stage == MESA_SHADER_FRAGMENT) {
si_llvm_build_monolithic_ps(&ctx, shader);
}
@ -1303,7 +1303,7 @@ bool si_llvm_compile_shader(struct si_screen *sscreen, struct ac_llvm_compiler *
/* Compile to bytecode. */
if (!si_compile_llvm(sscreen, &shader->binary, &shader->config, compiler, &ctx.ac, debug,
sel->info.stage, si_get_shader_name(shader),
sel->stage, si_get_shader_name(shader),
si_should_optimize_less(compiler, shader->selector))) {
si_llvm_dispose(&ctx);
fprintf(stderr, "LLVM failed to compile shader\n");

2
src/gallium/drivers/radeonsi/si_state.c
View File

@ -832,7 +832,7 @@ static void si_emit_clip_regs(struct si_context *sctx)
struct si_shader_selector *vs_sel = vs->selector;
struct si_shader_info *info = &vs_sel->info;
struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
bool window_space = info->stage == MESA_SHADER_VERTEX ?
bool window_space = vs_sel->stage == MESA_SHADER_VERTEX ?
info->base.vs.window_space_position : 0;
unsigned clipdist_mask = vs_sel->info.clipdist_mask;
unsigned ucp_mask = clipdist_mask ? 0 : rs->clip_plane_enable & SI_USER_CLIP_PLANE_MASK;

133
src/gallium/drivers/radeonsi/si_state_shaders.cpp
View File

@ -41,7 +41,7 @@ unsigned si_determine_wave_size(struct si_screen *sscreen, struct si_shader *sha
{
/* There are a few uses that pass shader=NULL here, expecting the default compute wave size. */
struct si_shader_info *info = shader ? &shader->selector->info : NULL;
gl_shader_stage stage = info ? info->stage : MESA_SHADER_COMPUTE;
gl_shader_stage stage = shader ? shader->selector->stage : MESA_SHADER_COMPUTE;
if (sscreen->info.chip_class < GFX10)
return 64;
@ -170,7 +170,7 @@ void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
shader_variant_flags |= 1 << 1;
if (wave_size == 32)
shader_variant_flags |= 1 << 2;
if (sel->info.stage == MESA_SHADER_FRAGMENT &&
if (sel->stage == MESA_SHADER_FRAGMENT &&
/* Derivatives imply helper invocations so check for needs_quad_helper_invocations. */
sel->info.base.fs.needs_quad_helper_invocations &&
sel->info.base.fs.uses_discard &&
@ -190,9 +190,9 @@ void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
shader_variant_flags |= 1 << 7;
if (sel->screen->options.clamp_div_by_zero)
shader_variant_flags |= 1 << 8;
if ((sel->info.stage == MESA_SHADER_VERTEX ||
sel->info.stage == MESA_SHADER_TESS_EVAL ||
sel->info.stage == MESA_SHADER_GEOMETRY) &&
if ((sel->stage == MESA_SHADER_VERTEX ||
sel->stage == MESA_SHADER_TESS_EVAL ||
sel->stage == MESA_SHADER_GEOMETRY) &&
!es &&
sel->screen->options.vrs2x2)
shader_variant_flags |= 1 << 10;
@ -313,7 +313,7 @@ static bool si_load_shader_binary(struct si_shader *shader, void *binary)
ptr = read_chunk(ptr, (void **)&shader->binary.llvm_ir_string, &chunk_size);
if (!shader->is_gs_copy_shader &&
shader->selector->info.stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg) {
shader->selector->stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg) {
shader->gs_copy_shader = CALLOC_STRUCT(si_shader);
if (!shader->gs_copy_shader)
return false;
@ -363,7 +363,7 @@ void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_s
unsigned size = *hw_binary;
if (shader->selector->info.stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg) {
if (shader->selector->stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg) {
uint32_t *gs_copy_binary = si_get_shader_binary(shader->gs_copy_shader);
if (!gs_copy_binary) {
FREE(hw_binary);
@ -432,7 +432,7 @@ bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha
unsigned gs_copy_binary_size = 0;
/* The GS copy shader binary is after the GS binary. */
if (shader->selector->info.stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg)
if (shader->selector->stage == MESA_SHADER_GEOMETRY && !shader->key.ge.as_ngg)
gs_copy_binary_size = buffer[size / 4];
if (total_size >= sizeof(uint32_t) && size + gs_copy_binary_size == total_size) {
@ -588,13 +588,13 @@ static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_sh
return;
/* VS as VS, or VS as ES: */
if ((sel->info.stage == MESA_SHADER_VERTEX &&
if ((sel->stage == MESA_SHADER_VERTEX &&
(!shader->key.ge.as_ls && !shader->is_gs_copy_shader)) ||
/* TES as VS, or TES as ES: */
sel->info.stage == MESA_SHADER_TESS_EVAL) {
sel->stage == MESA_SHADER_TESS_EVAL) {
unsigned vtx_reuse_depth = 30;
if (sel->info.stage == MESA_SHADER_TESS_EVAL &&
if (sel->stage == MESA_SHADER_TESS_EVAL &&
sel->info.base.tess.spacing == TESS_SPACING_FRACTIONAL_ODD)
vtx_reuse_depth = 14;
@ -630,15 +630,15 @@ static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen, struct si_shader *shader,
bool legacy_vs_prim_id)
{
assert(shader->selector->info.stage == MESA_SHADER_VERTEX ||
(shader->previous_stage_sel && shader->previous_stage_sel->info.stage == MESA_SHADER_VERTEX));
assert(shader->selector->stage == MESA_SHADER_VERTEX ||
(shader->previous_stage_sel && shader->previous_stage_sel->stage == MESA_SHADER_VERTEX));
/* GFX6-9 LS (VertexID, RelAutoIndex, InstanceID / StepRate0, InstanceID)
* GFX6-9 ES,VS (VertexID, InstanceID / StepRate0, VSPrimID, InstanceID)
* GFX10 LS (VertexID, RelAutoIndex, UserVGPR1, UserVGPR2 or InstanceID)
* GFX10 ES,VS (VertexID, UserVGPR1, UserVGPR2 or VSPrimID, UserVGPR3 or InstanceID)
*/
bool is_ls = shader->selector->info.stage == MESA_SHADER_TESS_CTRL || shader->key.ge.as_ls;
bool is_ls = shader->selector->stage == MESA_SHADER_TESS_CTRL || shader->key.ge.as_ls;
unsigned max = 0;
if (shader->info.uses_instanceid) {
@ -746,7 +746,7 @@ static void si_emit_shader_es(struct si_context *sctx)
SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
shader->selector->info.esgs_itemsize / 4);
if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
shader->vgt_tf_param);
@ -774,16 +774,16 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
pm4->atom.emit = si_emit_shader_es;
va = shader->bo->gpu_address;
if (shader->selector->info.stage == MESA_SHADER_VERTEX) {
if (shader->selector->stage == MESA_SHADER_VERTEX) {
vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
} else if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL) {
} else if (shader->selector->stage == MESA_SHADER_TESS_EVAL) {
vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
num_user_sgprs = SI_TES_NUM_USER_SGPR;
} else
unreachable("invalid shader selector type");
oc_lds_en = shader->selector->info.stage == MESA_SHADER_TESS_EVAL ? 1 : 0;
oc_lds_en = shader->selector->stage == MESA_SHADER_TESS_EVAL ? 1 : 0;
si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES,
@ -797,7 +797,7 @@ static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
S_00B32C_USER_SGPR(num_user_sgprs) | S_00B32C_OC_LDS_EN(oc_lds_en) |
S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
si_set_tesseval_regs(sscreen, shader->selector, shader);
polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader);
@ -944,7 +944,7 @@ static void si_emit_shader_gs(struct si_context *sctx)
SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
if (shader->key.ge.part.gs.es->info.stage == MESA_SHADER_TESS_EVAL)
if (shader->key.ge.part.gs.es->stage == MESA_SHADER_TESS_EVAL)
radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
shader->vgt_tf_param);
if (shader->vgt_vertex_reuse_block_cntl)
@ -1039,7 +1039,7 @@ static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
if (sscreen->info.chip_class >= GFX9) {
unsigned input_prim = sel->info.base.gs.input_primitive;
gl_shader_stage es_stage = shader->key.ge.part.gs.es->info.stage;
gl_shader_stage es_stage = shader->key.ge.part.gs.es->stage;
unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
if (es_stage == MESA_SHADER_VERTEX) {
@ -1147,7 +1147,7 @@ bool gfx10_is_ngg_passthrough(struct si_shader *shader)
*
* NGG passthrough still allows the use of LDS.
*/
return sel->info.stage != MESA_SHADER_GEOMETRY && !shader->key.ge.opt.ngg_culling;
return sel->stage != MESA_SHADER_GEOMETRY && !shader->key.ge.opt.ngg_culling;
}
/* Common tail code for NGG primitive shaders. */
@ -1265,10 +1265,10 @@ static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
unsigned si_get_input_prim(const struct si_shader_selector *gs, const union si_shader_key *key)
{
if (gs->info.stage == MESA_SHADER_GEOMETRY)
if (gs->stage == MESA_SHADER_GEOMETRY)
return gs->info.base.gs.input_primitive;
if (gs->info.stage == MESA_SHADER_TESS_EVAL) {
if (gs->stage == MESA_SHADER_TESS_EVAL) {
if (gs->info.base.tess.point_mode)
return PIPE_PRIM_POINTS;
if (gs->info.base.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES)
@ -1312,15 +1312,15 @@ static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader
{
const struct si_shader_selector *gs_sel = shader->selector;
const struct si_shader_info *gs_info = &gs_sel->info;
const gl_shader_stage gs_stage = shader->selector->info.stage;
const gl_shader_stage gs_stage = shader->selector->stage;
const struct si_shader_selector *es_sel =
shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
const struct si_shader_info *es_info = &es_sel->info;
const gl_shader_stage es_stage = es_sel->info.stage;
const gl_shader_stage es_stage = es_sel->stage;
unsigned num_user_sgprs;
unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
uint64_t va;
bool window_space = gs_info->stage == MESA_SHADER_VERTEX ?
bool window_space = gs_sel->stage == MESA_SHADER_VERTEX ?
gs_info->base.vs.window_space_position : 0;
bool es_enable_prim_id = shader->key.ge.mono.u.vs_export_prim_id || es_info->uses_primid;
unsigned gs_num_invocations = MAX2(gs_sel->info.base.gs.invocations, 1);
@ -1541,7 +1541,7 @@ static void si_emit_shader_vs(struct si_context *sctx)
radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
shader->ctx_reg.vs.pa_cl_vte_cntl);
if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
shader->vgt_tf_param);
@ -1551,7 +1551,7 @@ static void si_emit_shader_vs(struct si_context *sctx)
shader->vgt_vertex_reuse_block_cntl);
/* Required programming for tessellation. (legacy pipeline only) */
if (sctx->chip_class >= GFX10 && shader->selector->info.stage == MESA_SHADER_TESS_EVAL) {
if (sctx->chip_class >= GFX10 && shader->selector->stage == MESA_SHADER_TESS_EVAL) {
radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
SI_TRACKED_VGT_GS_ONCHIP_CNTL,
S_028A44_ES_VERTS_PER_SUBGRP(250) |
@ -1585,7 +1585,7 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
unsigned num_user_sgprs, vgpr_comp_cnt;
uint64_t va;
unsigned nparams, oc_lds_en;
bool window_space = info->stage == MESA_SHADER_VERTEX ?
bool window_space = shader->selector->stage == MESA_SHADER_VERTEX ?
info->base.vs.window_space_position : 0;
bool enable_prim_id = shader->key.ge.mono.u.vs_export_prim_id || info->uses_primid;
@ -1627,7 +1627,7 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
if (gs) {
vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
} else if (shader->selector->info.stage == MESA_SHADER_VERTEX) {
} else if (shader->selector->stage == MESA_SHADER_VERTEX) {
vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
if (info->base.vs.blit_sgprs_amd) {
@ -1635,7 +1635,7 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
} else {
num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
}
} else if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL) {
} else if (shader->selector->stage == MESA_SHADER_TESS_EVAL) {
vgpr_comp_cnt = enable_prim_id ? 3 : 2;
num_user_sgprs = SI_TES_NUM_USER_SGPR;
} else
@ -1667,7 +1667,7 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, shader, false);
oc_lds_en = shader->selector->info.stage == MESA_SHADER_TESS_EVAL ? 1 : 0;
oc_lds_en = shader->selector->stage == MESA_SHADER_TESS_EVAL ? 1 : 0;
if (sscreen->info.chip_class >= GFX7) {
ac_set_reg_cu_en(pm4, R_00B118_SPI_SHADER_PGM_RSRC3_VS,
@ -1717,7 +1717,7 @@ static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
if (shader->selector->stage == MESA_SHADER_TESS_EVAL)
si_set_tesseval_regs(sscreen, shader->selector, shader);
polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader);
@ -1922,7 +1922,7 @@ static void si_shader_init_pm4_state(struct si_screen *sscreen, struct si_shader
{
assert(shader->wave_size);
switch (shader->selector->info.stage) {
switch (shader->selector->stage) {
case MESA_SHADER_VERTEX:
if (shader->key.ge.as_ls)
si_shader_ls(sscreen, shader);
@ -2085,7 +2085,7 @@ static void si_get_vs_key_outputs(struct si_context *sctx, struct si_shader_sele
key->ge.opt.kill_outputs = ~linked & outputs_written;
key->ge.opt.ngg_culling = sctx->ngg_culling;
key->ge.mono.u.vs_export_prim_id = vs->info.stage != MESA_SHADER_GEOMETRY &&
key->ge.mono.u.vs_export_prim_id = vs->stage != MESA_SHADER_GEOMETRY &&
sctx->shader.ps.cso && sctx->shader.ps.cso->info.uses_primid;
key->ge.opt.kill_pointsize = vs->info.writes_psize &&
sctx->current_rast_prim != PIPE_PRIM_POINTS &&
@ -2326,7 +2326,7 @@ static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_sh
{
struct si_context *sctx = (struct si_context *)ctx;
switch (sel->info.stage) {
switch (sel->stage) {
case MESA_SHADER_VERTEX:
if (!sctx->shader.tes.cso && !sctx->shader.gs.cso)
si_get_vs_key_outputs(sctx, sel, key);
@ -2396,7 +2396,7 @@ static void si_build_shader_variant(struct si_shader *shader, int thread_index,
si_init_compiler(sscreen, compiler);
if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) {
PRINT_ERR("Failed to build shader variant (type=%u)\n", sel->info.stage);
PRINT_ERR("Failed to build shader variant (type=%u)\n", sel->stage);
shader->compilation_failed = true;
return;
}
@ -2442,7 +2442,7 @@ static bool si_check_missing_main_part(struct si_screen *sscreen, struct si_shad
util_queue_fence_init(&main_part->ready);
main_part->selector = sel;
if (sel->info.stage <= MESA_SHADER_GEOMETRY) {
if (sel->stage <= MESA_SHADER_GEOMETRY) {
main_part->key.ge.as_es = key->ge.as_es;
main_part->key.ge.as_ls = key->ge.as_ls;
main_part->key.ge.as_ngg = key->ge.as_ngg;
@ -2632,9 +2632,9 @@ current_not_ready:
/* If this is a merged shader, get the first shader's selector. */
if (sscreen->info.chip_class >= GFX9) {
if (sel->info.stage == MESA_SHADER_TESS_CTRL)
if (sel->stage == MESA_SHADER_TESS_CTRL)
previous_stage_sel = ((struct si_shader_key_ge*)key)->part.tcs.ls;
else if (sel->info.stage == MESA_SHADER_GEOMETRY)
else if (sel->stage == MESA_SHADER_GEOMETRY)
previous_stage_sel = ((struct si_shader_key_ge*)key)->part.gs.es;
/* We need to wait for the previous shader. */
@ -2664,9 +2664,9 @@ current_not_ready:
if (previous_stage_sel) {
union si_shader_key shader1_key = zeroed;
if (sel->info.stage == MESA_SHADER_TESS_CTRL) {
if (sel->stage == MESA_SHADER_TESS_CTRL) {
shader1_key.ge.as_ls = 1;
} else if (sel->info.stage == MESA_SHADER_GEOMETRY) {
} else if (sel->stage == MESA_SHADER_GEOMETRY) {
shader1_key.ge.as_es = 1;
shader1_key.ge.as_ngg = ((struct si_shader_key_ge*)key)->as_ngg; /* for Wave32 vs Wave64 */
} else {
@ -2766,7 +2766,7 @@ int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state
si_shader_selector_key(ctx, state->cso, &state->key);
if (state->cso->info.stage == MESA_SHADER_FRAGMENT) {
if (state->cso->stage == MESA_SHADER_FRAGMENT) {
if (state->key.ps.opt.inline_uniforms)
return si_shader_select_with_key(sctx, state, &state->key.ps, -1, false);
else
@ -2785,7 +2785,7 @@ static void si_parse_next_shader_property(const struct si_shader_info *info,
{
gl_shader_stage next_shader = info->base.next_stage;
switch (info->stage) {
switch (info->base.stage) {
case MESA_SHADER_VERTEX:
switch (next_shader) {
case MESA_SHADER_GEOMETRY:
@ -2873,17 +2873,17 @@ static void si_init_shader_selector_async(void *job, void *gdata, int thread_ind
shader->is_monolithic = false;
si_parse_next_shader_property(&sel->info, &shader->key);
if (sel->info.stage <= MESA_SHADER_GEOMETRY &&
if (sel->stage <= MESA_SHADER_GEOMETRY &&
sscreen->use_ngg && (!sel->info.enabled_streamout_buffer_mask ||
sscreen->use_ngg_streamout) &&
((sel->info.stage == MESA_SHADER_VERTEX && !shader->key.ge.as_ls) ||
sel->info.stage == MESA_SHADER_TESS_EVAL || sel->info.stage == MESA_SHADER_GEOMETRY))
((sel->stage == MESA_SHADER_VERTEX && !shader->key.ge.as_ls) ||
sel->stage == MESA_SHADER_TESS_EVAL || sel->stage == MESA_SHADER_GEOMETRY))
shader->key.ge.as_ngg = 1;
shader->wave_size = si_determine_wave_size(sscreen, shader);
if (sel->nir) {
if (sel->info.stage <= MESA_SHADER_GEOMETRY) {
if (sel->stage <= MESA_SHADER_GEOMETRY) {
si_get_ir_cache_key(sel, shader->key.ge.as_ngg, shader->key.ge.as_es,
shader->wave_size, ir_sha1_cache_key);
} else {
@ -2921,9 +2921,9 @@ static void si_init_shader_selector_async(void *job, void *gdata, int thread_ind
*
* This is only done if non-monolithic shaders are enabled.
*/
if ((sel->info.stage == MESA_SHADER_VERTEX ||
sel->info.stage == MESA_SHADER_TESS_EVAL ||
sel->info.stage == MESA_SHADER_GEOMETRY) &&
if ((sel->stage == MESA_SHADER_VERTEX ||
sel->stage == MESA_SHADER_TESS_EVAL ||
sel->stage == MESA_SHADER_GEOMETRY) &&
!shader->key.ge.as_ls && !shader->key.ge.as_es) {
unsigned i;
@ -3041,7 +3041,8 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
si_nir_scan_shader(sscreen, sel->nir, &sel->info);
const enum pipe_shader_type type = pipe_shader_type_from_mesa(sel->info.stage);
sel->stage = sel->nir->info.stage;
const enum pipe_shader_type type = pipe_shader_type_from_mesa(sel->stage);
sel->pipe_shader_type = type;
sel->const_and_shader_buf_descriptors_index =
si_const_and_shader_buffer_descriptors_idx(type);
@ -3052,7 +3053,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
si_get_active_slot_masks(&sel->info, &sel->active_const_and_shader_buffers,
&sel->active_samplers_and_images);
switch (sel->info.stage) {
switch (sel->stage) {
case MESA_SHADER_GEOMETRY:
/* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
sel->rast_prim = (enum pipe_prim_type)sel->info.base.gs.output_primitive;
@ -3072,7 +3073,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
case MESA_SHADER_VERTEX:
case MESA_SHADER_TESS_EVAL:
if (sel->info.stage == MESA_SHADER_TESS_EVAL) {
if (sel->stage == MESA_SHADER_TESS_EVAL) {
if (sel->info.base.tess.point_mode)
sel->rast_prim = PIPE_PRIM_POINTS;
else if (sel->info.base.tess._primitive_mode == TESS_PRIMITIVE_ISOLINES)
@ -3093,22 +3094,22 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
!sel->info.writes_viewport_index && /* cull only against viewport 0 */
!sel->info.base.writes_memory &&
/* NGG GS supports culling with streamout because it culls after streamout. */
(sel->info.stage == MESA_SHADER_GEOMETRY || !sel->info.enabled_streamout_buffer_mask) &&
(sel->info.stage != MESA_SHADER_GEOMETRY || sel->info.num_stream_output_components[0]) &&
(sel->info.stage != MESA_SHADER_VERTEX ||
(sel->stage == MESA_SHADER_GEOMETRY || !sel->info.enabled_streamout_buffer_mask) &&
(sel->stage != MESA_SHADER_GEOMETRY || sel->info.num_stream_output_components[0]) &&
(sel->stage != MESA_SHADER_VERTEX ||
(!sel->info.base.vs.blit_sgprs_amd &&
!sel->info.base.vs.window_space_position));
sel->ngg_cull_vert_threshold = UINT_MAX; /* disabled (changed below) */
if (ngg_culling_allowed) {
if (sel->info.stage == MESA_SHADER_VERTEX) {
if (sel->stage == MESA_SHADER_VERTEX) {
if (sscreen->debug_flags & DBG(ALWAYS_NGG_CULLING_ALL))
sel->ngg_cull_vert_threshold = 0; /* always enabled */
else
sel->ngg_cull_vert_threshold = 128;
} else if (sel->info.stage == MESA_SHADER_TESS_EVAL ||
sel->info.stage == MESA_SHADER_GEOMETRY) {
} else if (sel->stage == MESA_SHADER_TESS_EVAL ||
sel->stage == MESA_SHADER_GEOMETRY) {
if (sel->rast_prim != PIPE_PRIM_POINTS)
sel->ngg_cull_vert_threshold = 0; /* always enabled */
}
@ -3116,7 +3117,7 @@ static void *si_create_shader_selector(struct pipe_context *ctx,
(void)simple_mtx_init(&sel->mutex, mtx_plain);
si_schedule_initial_compile(sctx, sel->info.stage, &sel->ready, &sel->compiler_ctx_state,
si_schedule_initial_compile(sctx, sel->stage, &sel->ready, &sel->compiler_ctx_state,
sel, si_init_shader_selector_async);
return sel;
}
@ -3162,8 +3163,8 @@ static void si_update_clip_regs(struct si_context *sctx, struct si_shader_select
{
if (next_hw_vs &&
(!old_hw_vs ||
(old_hw_vs->info.stage == MESA_SHADER_VERTEX && old_hw_vs->info.base.vs.window_space_position) !=
(next_hw_vs->info.stage == MESA_SHADER_VERTEX && next_hw_vs->info.base.vs.window_space_position) ||
(old_hw_vs->stage == MESA_SHADER_VERTEX && old_hw_vs->info.base.vs.window_space_position) !=
(next_hw_vs->stage == MESA_SHADER_VERTEX && next_hw_vs->info.base.vs.window_space_position) ||
old_hw_vs->info.clipdist_mask != next_hw_vs->info.clipdist_mask ||
old_hw_vs->info.culldist_mask != next_hw_vs->info.culldist_mask || !old_hw_vs_variant ||
!next_hw_vs_variant ||
@ -3500,7 +3501,7 @@ static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
*/
int state_index = -1;
switch (shader->selector->info.stage) {
switch (shader->selector->stage) {
case MESA_SHADER_VERTEX:
if (shader->key.ge.as_ls) {
if (sctx->chip_class <= GFX8)
@ -3552,7 +3553,7 @@ static void si_destroy_shader_selector(struct pipe_context *ctx, void *cso)
struct si_context *sctx = (struct si_context *)ctx;
struct si_shader_selector *sel = (struct si_shader_selector *)cso;
struct si_shader *p = sel->first_variant, *c;
enum pipe_shader_type type = pipe_shader_type_from_mesa(sel->info.stage);
enum pipe_shader_type type = pipe_shader_type_from_mesa(sel->stage);
util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);

5
src/gallium/drivers/radeonsi/si_state_viewport.c
View File

@ -590,14 +590,15 @@ static void si_emit_viewport_states(struct si_context *ctx)
*/
void si_update_vs_viewport_state(struct si_context *ctx)
{
struct si_shader_info *info = si_get_vs_info(ctx);
struct si_shader_ctx_state *vs = si_get_vs(ctx);
struct si_shader_info *info = vs->cso ? &vs->cso->info : NULL;
bool vs_window_space;
if (!info)
return;
/* When the VS disables clipping and viewport transformation. */
vs_window_space = info->stage == MESA_SHADER_VERTEX && info->base.vs.window_space_position;
vs_window_space = vs->cso->stage == MESA_SHADER_VERTEX && info->base.vs.window_space_position;
if (ctx->vs_disables_clipping_viewport != vs_window_space) {
ctx->vs_disables_clipping_viewport = vs_window_space;