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mesa/src/freedreno/ir3
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Emma Anholt 3d62a41dcc freedreno/ir3: Enable core NIR's 16-bit ALU optimizations. 
In addition to hopefully generating shorter code, this optimizes out a
comparison of a mediump-cast value in
dEQP-GLES2.functional.shaders.algorithm.rgb_to_hsl_fragment passed
through ANGLE, and allows the test to pass.  We believe it to be a
test bug, but emitting better code like apparently everyone else does
is also a fine result.

No change on GLES gfxbench shaders.

Fixes: #6585
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17546>
 		2022-07-18 22:41:18 +00:00
..
tests ir3: Refactor ir3_compiler_create() to take an options struct 2022-03-17 12:15:45 +00:00
.dir-locals.el
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.editorconfig
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disasm-a3xx.c
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instr-a3xx.h
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ir3.c Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3.h Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3_a4xx.c Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3_a6xx.c
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ir3_array_to_ssa.c
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ir3_assembler.c ir3: Remove ir3_shader_variant::shader 2022-05-13 17:07:05 +00:00
ir3_assembler.h freedreno/a6xx: Add EARLYPREAMBLE flag to all a6xx_sp_xs_ctrl_reg0 2022-05-18 11:17:47 +00:00
ir3_cf.c
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ir3_compiler.c freedreno/ir3: Enable core NIR's 16-bit ALU optimizations. 2022-07-18 22:41:18 +00:00
ir3_compiler.h Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3_compiler_nir.c ir3: Implement [iu]sub_sat. 2022-07-13 07:34:09 +00:00
ir3_context.c Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3_context.h ir3: Remove ir3_shader_variant::shader 2022-05-13 17:07:05 +00:00
ir3_cp.c Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3_cse.c
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ir3_dce.c
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ir3_delay.c
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ir3_disk_cache.c freedreno/ir3: Enable load/store vectorization for SSBO access, too. 2022-06-01 22:19:44 +00:00
ir3_dominance.c
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ir3_image.c freedreno/ir3: Fold 16-bit conversions into image load/store src/dsts. 2022-06-01 22:19:44 +00:00
ir3_image.h
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ir3_legalize.c Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3_lexer.l freedreno/a6xx: Add EARLYPREAMBLE flag to all a6xx_sp_xs_ctrl_reg0 2022-05-18 11:17:47 +00:00
ir3_liveness.c
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ir3_lower_parallelcopy.c ir3: Add ir3_shader_variant::compiler 2022-05-13 17:07:05 +00:00
ir3_lower_spill.c
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ir3_lower_subgroups.c
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ir3_merge_regs.c
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ir3_nir.c Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3_nir.h
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ir3_nir_analyze_ubo_ranges.c Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3_nir_imul.py
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ir3_nir_lower_64b.c
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ir3_nir_lower_io_offsets.c Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3_nir_lower_load_barycentric_at_offset.c ir3: Use non-persp interpolation when appropriate for interpolateAtOffset. 2022-07-11 16:56:05 +00:00
ir3_nir_lower_load_barycentric_at_sample.c ir3: Make sure to pass the interp_mode through in our load_bary lowering. 2022-07-11 16:56:05 +00:00
ir3_nir_lower_tess.c ir3: Fix the no-emitted-vertex condition emission in geom lowering. 2022-07-13 18:16:45 +00:00
ir3_nir_lower_tex_prefetch.c Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3_nir_lower_wide_load_store.c
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ir3_nir_move_varying_inputs.c Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3_nir_opt_preamble.c ir3, fd, tu: Copy misc. info from ir3_shader to ir3_shader_variant 2022-05-13 17:07:05 +00:00
ir3_nir_trig.py
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ir3_parser.y freedreno/a6xx: Add EARLYPREAMBLE flag to all a6xx_sp_xs_ctrl_reg0 2022-05-18 11:17:47 +00:00
ir3_postsched.c Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3_print.c
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ir3_ra.c ir3: Add ir3_shader_variant::compiler 2022-05-13 17:07:05 +00:00
ir3_ra.h
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ir3_ra_validate.c
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ir3_remove_unreachable.c
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ir3_sched.c Change all debug_assert calls to assert 2022-07-10 00:50:35 +00:00
ir3_shader.c nir+ir3: Rename load_size_ir3 to load_center_rhw_ir3. 2022-07-11 16:56:05 +00:00
ir3_shader.h nir+ir3: Rename load_size_ir3 to load_center_rhw_ir3. 2022-07-11 16:56:05 +00:00
ir3_spill.c ir3: Add ir3_shader_variant::compiler 2022-05-13 17:07:05 +00:00
ir3_validate.c freedreno/ir3: Fix validation of half-precision image store values. 2022-06-01 22:19:44 +00:00
meson.build ir3: Retire the cp postsched pass now that we do RA in SSA. 2022-07-04 22:15:58 +00:00