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freedreno/ir3: Enable load/store vectorization for SSBO access, too. 

Saves a few ldib/stib instructions in gfxbench vk-5-normal compute shaders
by grouping vec4 accesses together.

Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16616>
This commit is contained in:
Emma Anholt 2022-05-19 12:40:18 -07:00 committed by Marge Bot
parent 6e087f96c9
commit bf49d4a084
6 changed files with 10 additions and 10 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/freedreno/ir3/ir3_compiler.c
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@ -206,7 +206,7 @@ ir3_compiler_create(struct fd_device *dev, const struct fd_dev_id *dev_id,
compiler->dev = dev;
compiler->dev_id = dev_id;
compiler->gen = fd_dev_gen(dev_id);
compiler->robust_ubo_access = options->robust_ubo_access;
compiler->robust_buffer_access2 = options->robust_buffer_access2;
/* All known GPU's have 32k local memory (aka shared) */
compiler->local_mem_size = 32 * 1024;

6
src/freedreno/ir3/ir3_compiler.h
View File

@ -48,7 +48,7 @@ struct ir3_compiler {
struct nir_shader_compiler_options nir_options;
bool robust_ubo_access;
bool robust_buffer_access2;
/*
* Configuration options for things that are handled differently on
@ -187,10 +187,10 @@ struct ir3_compiler {
};
struct ir3_compiler_options {
/* If true, UBO accesses are assumed to be bounds-checked as defined by
/* If true, UBO/SSBO accesses are assumed to be bounds-checked as defined by
* VK_EXT_robustness2 and optimizations may have to be more conservative.
*/
bool robust_ubo_access;
bool robust_buffer_access2;
/* If true, promote UBOs (except for constant data) to constants using ldc.k
* in the preamble. The driver should ignore everything in ubo_state except

2
src/freedreno/ir3/ir3_disk_cache.c
View File

@ -63,7 +63,7 @@ ir3_disk_cache_init(struct ir3_compiler *compiler)
_mesa_sha1_format(timestamp, id_sha1);
uint64_t driver_flags = ir3_shader_debug;
if (compiler->robust_ubo_access)
if (compiler->robust_buffer_access2)
driver_flags |= IR3_DBG_ROBUST_UBO_ACCESS;
compiler->disk_cache = disk_cache_create(renderer, timestamp, driver_flags);
}

4
src/freedreno/ir3/ir3_nir.c
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@ -134,9 +134,9 @@ ir3_optimize_loop(struct ir3_compiler *compiler, nir_shader *s)
progress |= OPT(s, nir_opt_offsets, &offset_options);
nir_load_store_vectorize_options vectorize_opts = {
.modes = nir_var_mem_ubo,
.modes = nir_var_mem_ubo | nir_var_mem_ssbo,
.callback = ir3_nir_should_vectorize_mem,
.robust_modes = compiler->robust_ubo_access ? nir_var_mem_ubo : 0,
.robust_modes = compiler->robust_buffer_access2 ? nir_var_mem_ubo | nir_var_mem_ssbo: 0,
};
progress |= OPT(s, nir_opt_load_store_vectorize, &vectorize_opts);

2
src/freedreno/vulkan/tu_device.c
View File

@ -1803,7 +1803,7 @@ tu_CreateDevice(VkPhysicalDevice physicalDevice,
device->compiler =
ir3_compiler_create(NULL, &physical_device->dev_id,
&(struct ir3_compiler_options) {
.robust_ubo_access = robust_buffer_access2,
.robust_buffer_access2 = robust_buffer_access2,
.push_ubo_with_preamble = true,
.disable_cache = true,
});

4
src/freedreno/vulkan/tu_pipeline.c
View File

@ -2512,8 +2512,8 @@ tu_hash_stage(struct mesa_sha1 *ctx,
static void
tu_hash_compiler(struct mesa_sha1 *ctx, const struct ir3_compiler *compiler)
{
_mesa_sha1_update(ctx, &compiler->robust_ubo_access,
sizeof(compiler->robust_ubo_access));
_mesa_sha1_update(ctx, &compiler->robust_buffer_access2,
sizeof(compiler->robust_buffer_access2));
_mesa_sha1_update(ctx, &ir3_shader_debug, sizeof(ir3_shader_debug));
}