523 lines
19 KiB
C
523 lines
19 KiB
C
/*
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* Copyright (C) 2017-2018 Rob Clark <robclark@freedesktop.org>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*
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* Authors:
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* Rob Clark <robclark@freedesktop.org>
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*/
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#define GPU 600
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#include "ir3_context.h"
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#include "ir3_image.h"
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/*
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* Handlers for instructions changed/added in a6xx:
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*
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* Starting with a6xx, isam and stbi is used for SSBOs as well; stbi and the
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* atomic instructions (used for both SSBO and image) use a new instruction
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* encoding compared to a4xx/a5xx.
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*/
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/* src[] = { buffer_index, offset }. No const_index */
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static void
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emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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struct ir3_instruction **dst)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *offset;
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struct ir3_instruction *ldib;
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offset = ir3_get_src(ctx, &intr->src[2])[0];
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ldib = ir3_LDIB(b, ir3_ssbo_to_ibo(ctx, intr->src[0]), 0, offset, 0);
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ldib->dsts[0]->wrmask = MASK(intr->num_components);
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ldib->cat6.iim_val = intr->num_components;
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ldib->cat6.d = 1;
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ldib->cat6.type = intr->dest.ssa.bit_size == 16 ? TYPE_U16 : TYPE_U32;
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ldib->barrier_class = IR3_BARRIER_BUFFER_R;
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ldib->barrier_conflict = IR3_BARRIER_BUFFER_W;
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ir3_handle_bindless_cat6(ldib, intr->src[0]);
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ir3_handle_nonuniform(ldib, intr);
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ir3_split_dest(b, dst, ldib, 0, intr->num_components);
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}
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/* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
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static void
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emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *stib, *val, *offset;
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unsigned wrmask = nir_intrinsic_write_mask(intr);
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unsigned ncomp = ffs(~wrmask) - 1;
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assert(wrmask == BITFIELD_MASK(intr->num_components));
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/* src0 is offset, src1 is value:
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*/
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val = ir3_create_collect(b, ir3_get_src(ctx, &intr->src[0]), ncomp);
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offset = ir3_get_src(ctx, &intr->src[3])[0];
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stib = ir3_STIB(b, ir3_ssbo_to_ibo(ctx, intr->src[1]), 0, offset, 0, val, 0);
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stib->cat6.iim_val = ncomp;
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stib->cat6.d = 1;
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stib->cat6.type = intr->src[0].ssa->bit_size == 16 ? TYPE_U16 : TYPE_U32;
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stib->barrier_class = IR3_BARRIER_BUFFER_W;
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stib->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
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ir3_handle_bindless_cat6(stib, intr->src[1]);
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ir3_handle_nonuniform(stib, intr);
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array_insert(b, b->keeps, stib);
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}
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/*
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* SSBO atomic intrinsics
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*
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* All of the SSBO atomic memory operations read a value from memory,
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* compute a new value using one of the operations below, write the new
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* value to memory, and return the original value read.
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*
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* All operations take 3 sources except CompSwap that takes 4. These
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* sources represent:
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*
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* 0: The SSBO buffer index.
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* 1: The offset into the SSBO buffer of the variable that the atomic
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* operation will operate on.
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* 2: The data parameter to the atomic function (i.e. the value to add
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* in ssbo_atomic_add, etc).
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* 3: For CompSwap only: the second data parameter.
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*/
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static struct ir3_instruction *
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emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *atomic, *ibo, *src0, *src1, *data, *dummy;
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type_t type = TYPE_U32;
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ibo = ir3_ssbo_to_ibo(ctx, intr->src[0]);
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data = ir3_get_src(ctx, &intr->src[2])[0];
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/* So this gets a bit creative:
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*
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* src0 - vecN offset/coords
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* src1.x - is actually destination register
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* src1.y - is 'data' except for cmpxchg where src2.y is 'compare'
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* src1.z - is 'data' for cmpxchg
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*
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* The combining src and dest kinda doesn't work out so well with how
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* scheduling and RA work. So we create a dummy src2 which is tied to the
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* destination in RA (i.e. must be allocated to the same vec2/vec3
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* register) and then immediately extract the first component.
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*
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* Note that nir already multiplies the offset by four
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*/
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dummy = create_immed(b, 0);
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if (intr->intrinsic == nir_intrinsic_ssbo_atomic_comp_swap_ir3) {
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src0 = ir3_get_src(ctx, &intr->src[4])[0];
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struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[3])[0];
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src1 = ir3_collect(b, dummy, compare, data);
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} else {
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src0 = ir3_get_src(ctx, &intr->src[3])[0];
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src1 = ir3_collect(b, dummy, data);
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}
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switch (intr->intrinsic) {
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case nir_intrinsic_ssbo_atomic_add_ir3:
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atomic = ir3_ATOMIC_B_ADD(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_imin_ir3:
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atomic = ir3_ATOMIC_B_MIN(b, ibo, 0, src0, 0, src1, 0);
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type = TYPE_S32;
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break;
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case nir_intrinsic_ssbo_atomic_umin_ir3:
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atomic = ir3_ATOMIC_B_MIN(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_imax_ir3:
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atomic = ir3_ATOMIC_B_MAX(b, ibo, 0, src0, 0, src1, 0);
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type = TYPE_S32;
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break;
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case nir_intrinsic_ssbo_atomic_umax_ir3:
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atomic = ir3_ATOMIC_B_MAX(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_and_ir3:
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atomic = ir3_ATOMIC_B_AND(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_or_ir3:
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atomic = ir3_ATOMIC_B_OR(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_xor_ir3:
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atomic = ir3_ATOMIC_B_XOR(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_exchange_ir3:
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atomic = ir3_ATOMIC_B_XCHG(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
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atomic = ir3_ATOMIC_B_CMPXCHG(b, ibo, 0, src0, 0, src1, 0);
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break;
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default:
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unreachable("boo");
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}
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atomic->cat6.iim_val = 1;
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atomic->cat6.d = 1;
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atomic->cat6.type = type;
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atomic->barrier_class = IR3_BARRIER_BUFFER_W;
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atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
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ir3_handle_bindless_cat6(atomic, intr->src[0]);
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/* even if nothing consume the result, we can't DCE the instruction: */
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array_insert(b, b->keeps, atomic);
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atomic->dsts[0]->wrmask = src1->dsts[0]->wrmask;
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ir3_reg_tie(atomic->dsts[0], atomic->srcs[2]);
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struct ir3_instruction *split;
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ir3_split_dest(b, &split, atomic, 0, 1);
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return split;
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}
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/* src[] = { deref, coord, sample_index }. const_index[] = {} */
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static void
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emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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struct ir3_instruction **dst)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *ldib;
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struct ir3_instruction *const *coords = ir3_get_src(ctx, &intr->src[1]);
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unsigned ncoords = ir3_get_image_coords(intr, NULL);
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ldib = ir3_LDIB(b, ir3_image_to_ibo(ctx, intr->src[0]), 0,
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ir3_create_collect(b, coords, ncoords), 0);
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ldib->dsts[0]->wrmask = MASK(intr->num_components);
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ldib->cat6.iim_val = intr->num_components;
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ldib->cat6.d = ncoords;
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ldib->cat6.type = ir3_get_type_for_image_intrinsic(intr);
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ldib->cat6.typed = true;
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ldib->barrier_class = IR3_BARRIER_IMAGE_R;
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ldib->barrier_conflict = IR3_BARRIER_IMAGE_W;
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ir3_handle_bindless_cat6(ldib, intr->src[0]);
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ir3_handle_nonuniform(ldib, intr);
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ir3_split_dest(b, dst, ldib, 0, intr->num_components);
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}
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/* src[] = { deref, coord, sample_index, value }. const_index[] = {} */
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static void
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emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *stib;
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struct ir3_instruction *const *value = ir3_get_src(ctx, &intr->src[3]);
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struct ir3_instruction *const *coords = ir3_get_src(ctx, &intr->src[1]);
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unsigned ncoords = ir3_get_image_coords(intr, NULL);
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enum pipe_format format = nir_intrinsic_format(intr);
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unsigned ncomp = ir3_get_num_components_for_image_format(format);
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/* src0 is offset, src1 is value:
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*/
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stib = ir3_STIB(b, ir3_image_to_ibo(ctx, intr->src[0]), 0,
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ir3_create_collect(b, coords, ncoords), 0,
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ir3_create_collect(b, value, ncomp), 0);
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stib->cat6.iim_val = ncomp;
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stib->cat6.d = ncoords;
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stib->cat6.type = ir3_get_type_for_image_intrinsic(intr);
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stib->cat6.typed = true;
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stib->barrier_class = IR3_BARRIER_IMAGE_W;
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stib->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
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ir3_handle_bindless_cat6(stib, intr->src[0]);
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ir3_handle_nonuniform(stib, intr);
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array_insert(b, b->keeps, stib);
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}
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/* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
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static struct ir3_instruction *
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emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *atomic, *ibo, *src0, *src1, *dummy;
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struct ir3_instruction *const *coords = ir3_get_src(ctx, &intr->src[1]);
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struct ir3_instruction *value = ir3_get_src(ctx, &intr->src[3])[0];
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unsigned ncoords = ir3_get_image_coords(intr, NULL);
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ibo = ir3_image_to_ibo(ctx, intr->src[0]);
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/* So this gets a bit creative:
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*
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* src0 - vecN offset/coords
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* src1.x - is actually destination register
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* src1.y - is 'value' except for cmpxchg where src2.y is 'compare'
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* src1.z - is 'value' for cmpxchg
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*
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* The combining src and dest kinda doesn't work out so well with how
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* scheduling and RA work. So we create a dummy src2 which is tied to the
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* destination in RA (i.e. must be allocated to the same vec2/vec3
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* register) and then immediately extract the first component.
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*/
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dummy = create_immed(b, 0);
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src0 = ir3_create_collect(b, coords, ncoords);
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if (intr->intrinsic == nir_intrinsic_image_atomic_comp_swap ||
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intr->intrinsic == nir_intrinsic_bindless_image_atomic_comp_swap) {
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struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[4])[0];
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src1 = ir3_collect(b, dummy, compare, value);
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} else {
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src1 = ir3_collect(b, dummy, value);
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}
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switch (intr->intrinsic) {
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case nir_intrinsic_image_atomic_add:
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case nir_intrinsic_bindless_image_atomic_add:
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atomic = ir3_ATOMIC_B_ADD(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_image_atomic_imin:
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case nir_intrinsic_image_atomic_umin:
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case nir_intrinsic_bindless_image_atomic_imin:
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case nir_intrinsic_bindless_image_atomic_umin:
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atomic = ir3_ATOMIC_B_MIN(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_image_atomic_imax:
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case nir_intrinsic_image_atomic_umax:
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case nir_intrinsic_bindless_image_atomic_imax:
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case nir_intrinsic_bindless_image_atomic_umax:
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atomic = ir3_ATOMIC_B_MAX(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_image_atomic_and:
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case nir_intrinsic_bindless_image_atomic_and:
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atomic = ir3_ATOMIC_B_AND(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_image_atomic_or:
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case nir_intrinsic_bindless_image_atomic_or:
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atomic = ir3_ATOMIC_B_OR(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_image_atomic_xor:
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case nir_intrinsic_bindless_image_atomic_xor:
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atomic = ir3_ATOMIC_B_XOR(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_image_atomic_exchange:
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case nir_intrinsic_bindless_image_atomic_exchange:
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atomic = ir3_ATOMIC_B_XCHG(b, ibo, 0, src0, 0, src1, 0);
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break;
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case nir_intrinsic_image_atomic_comp_swap:
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case nir_intrinsic_bindless_image_atomic_comp_swap:
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atomic = ir3_ATOMIC_B_CMPXCHG(b, ibo, 0, src0, 0, src1, 0);
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break;
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default:
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unreachable("boo");
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}
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atomic->cat6.iim_val = 1;
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atomic->cat6.d = ncoords;
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atomic->cat6.type = ir3_get_type_for_image_intrinsic(intr);
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atomic->cat6.typed = true;
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atomic->barrier_class = IR3_BARRIER_IMAGE_W;
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atomic->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
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ir3_handle_bindless_cat6(atomic, intr->src[0]);
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/* even if nothing consume the result, we can't DCE the instruction: */
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array_insert(b, b->keeps, atomic);
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atomic->dsts[0]->wrmask = src1->dsts[0]->wrmask;
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ir3_reg_tie(atomic->dsts[0], atomic->srcs[2]);
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struct ir3_instruction *split;
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ir3_split_dest(b, &split, atomic, 0, 1);
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return split;
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}
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static void
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emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
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struct ir3_instruction **dst)
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{
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struct ir3_block *b = ctx->block;
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struct ir3_instruction *ibo = ir3_image_to_ibo(ctx, intr->src[0]);
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struct ir3_instruction *resinfo = ir3_RESINFO(b, ibo, 0);
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resinfo->cat6.iim_val = 1;
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resinfo->cat6.d = intr->num_components;
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resinfo->cat6.type = TYPE_U32;
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resinfo->cat6.typed = false;
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/* resinfo has no writemask and always writes out 3 components: */
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compile_assert(ctx, intr->num_components <= 3);
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resinfo->dsts[0]->wrmask = MASK(3);
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ir3_handle_bindless_cat6(resinfo, intr->src[0]);
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ir3_handle_nonuniform(resinfo, intr);
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ir3_split_dest(b, dst, resinfo, 0, intr->num_components);
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}
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static void
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emit_intrinsic_load_global_ir3(struct ir3_context *ctx,
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nir_intrinsic_instr *intr,
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struct ir3_instruction **dst)
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{
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struct ir3_block *b = ctx->block;
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unsigned dest_components = nir_intrinsic_dest_components(intr);
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struct ir3_instruction *addr, *offset;
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addr = ir3_collect(b, ir3_get_src(ctx, &intr->src[0])[0],
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ir3_get_src(ctx, &intr->src[0])[1]);
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struct ir3_instruction *load;
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bool const_offset_in_bounds = nir_src_is_const(intr->src[1]) &&
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nir_src_as_int(intr->src[1]) < (1 << 13) &&
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nir_src_as_int(intr->src[1]) > -(1 << 13);
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if (const_offset_in_bounds) {
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load = ir3_LDG(b, addr, 0, create_immed(b, nir_src_as_int(intr->src[1])),
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0, create_immed(b, dest_components), 0);
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} else {
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offset = ir3_get_src(ctx, &intr->src[1])[0];
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load =
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ir3_LDG_A(b, addr, 0, offset, 0, create_immed(b, 0), 0,
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create_immed(b, 0), 0, create_immed(b, dest_components), 0);
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}
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load->cat6.type = type_uint_size(intr->dest.ssa.bit_size);
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load->dsts[0]->wrmask = MASK(dest_components);
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load->barrier_class = IR3_BARRIER_BUFFER_R;
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load->barrier_conflict = IR3_BARRIER_BUFFER_W;
|
|
|
|
ir3_split_dest(b, dst, load, 0, dest_components);
|
|
}
|
|
|
|
static void
|
|
emit_intrinsic_store_global_ir3(struct ir3_context *ctx,
|
|
nir_intrinsic_instr *intr)
|
|
{
|
|
struct ir3_block *b = ctx->block;
|
|
struct ir3_instruction *value, *addr, *offset;
|
|
unsigned ncomp = nir_intrinsic_src_components(intr, 0);
|
|
|
|
addr = ir3_collect(b, ir3_get_src(ctx, &intr->src[1])[0],
|
|
ir3_get_src(ctx, &intr->src[1])[1]);
|
|
|
|
value = ir3_create_collect(b, ir3_get_src(ctx, &intr->src[0]), ncomp);
|
|
|
|
struct ir3_instruction *stg;
|
|
|
|
bool const_offset_in_bounds = nir_src_is_const(intr->src[2]) &&
|
|
nir_src_as_int(intr->src[2]) < (1 << 13) &&
|
|
nir_src_as_int(intr->src[2]) > -(1 << 13);
|
|
|
|
if (const_offset_in_bounds) {
|
|
stg = ir3_STG(b, addr, 0,
|
|
create_immed(b, nir_src_as_int(intr->src[2])), 0,
|
|
value, 0,
|
|
create_immed(b, ncomp), 0);
|
|
} else {
|
|
offset = ir3_get_src(ctx, &intr->src[2])[0];
|
|
stg =
|
|
ir3_STG_A(b, addr, 0, offset, 0, create_immed(b, 0), 0,
|
|
create_immed(b, 0), 0, value, 0, create_immed(b, ncomp), 0);
|
|
}
|
|
|
|
stg->cat6.type = type_uint_size(intr->src[0].ssa->bit_size);
|
|
stg->cat6.iim_val = 1;
|
|
|
|
array_insert(b, b->keeps, stg);
|
|
|
|
stg->barrier_class = IR3_BARRIER_BUFFER_W;
|
|
stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
|
|
}
|
|
|
|
static struct ir3_instruction *
|
|
emit_intrinsic_atomic_global(struct ir3_context *ctx, nir_intrinsic_instr *intr)
|
|
{
|
|
struct ir3_block *b = ctx->block;
|
|
struct ir3_instruction *addr, *atomic, *src1;
|
|
struct ir3_instruction *value = ir3_get_src(ctx, &intr->src[1])[0];
|
|
type_t type = TYPE_U32;
|
|
|
|
addr = ir3_collect(b, ir3_get_src(ctx, &intr->src[0])[0],
|
|
ir3_get_src(ctx, &intr->src[0])[1]);
|
|
|
|
if (intr->intrinsic == nir_intrinsic_global_atomic_comp_swap_ir3) {
|
|
struct ir3_instruction *compare = ir3_get_src(ctx, &intr->src[2])[0];
|
|
src1 = ir3_collect(b, compare, value);
|
|
} else {
|
|
src1 = value;
|
|
}
|
|
|
|
switch (intr->intrinsic) {
|
|
case nir_intrinsic_global_atomic_add_ir3:
|
|
atomic = ir3_ATOMIC_G_ADD(b, addr, 0, src1, 0);
|
|
break;
|
|
case nir_intrinsic_global_atomic_imin_ir3:
|
|
atomic = ir3_ATOMIC_G_MIN(b, addr, 0, src1, 0);
|
|
type = TYPE_S32;
|
|
break;
|
|
case nir_intrinsic_global_atomic_umin_ir3:
|
|
atomic = ir3_ATOMIC_G_MIN(b, addr, 0, src1, 0);
|
|
break;
|
|
case nir_intrinsic_global_atomic_imax_ir3:
|
|
atomic = ir3_ATOMIC_G_MAX(b, addr, 0, src1, 0);
|
|
type = TYPE_S32;
|
|
break;
|
|
case nir_intrinsic_global_atomic_umax_ir3:
|
|
atomic = ir3_ATOMIC_G_MAX(b, addr, 0, src1, 0);
|
|
break;
|
|
case nir_intrinsic_global_atomic_and_ir3:
|
|
atomic = ir3_ATOMIC_G_AND(b, addr, 0, src1, 0);
|
|
break;
|
|
case nir_intrinsic_global_atomic_or_ir3:
|
|
atomic = ir3_ATOMIC_G_OR(b, addr, 0, src1, 0);
|
|
break;
|
|
case nir_intrinsic_global_atomic_xor_ir3:
|
|
atomic = ir3_ATOMIC_G_XOR(b, addr, 0, src1, 0);
|
|
break;
|
|
case nir_intrinsic_global_atomic_exchange_ir3:
|
|
atomic = ir3_ATOMIC_G_XCHG(b, addr, 0, src1, 0);
|
|
break;
|
|
case nir_intrinsic_global_atomic_comp_swap_ir3:
|
|
atomic = ir3_ATOMIC_G_CMPXCHG(b, addr, 0, src1, 0);
|
|
break;
|
|
default:
|
|
unreachable("Unknown global atomic op");
|
|
}
|
|
|
|
atomic->cat6.iim_val = 1;
|
|
atomic->cat6.d = 1;
|
|
atomic->cat6.type = type;
|
|
atomic->barrier_class = IR3_BARRIER_BUFFER_W;
|
|
atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
|
|
|
|
/* even if nothing consume the result, we can't DCE the instruction: */
|
|
array_insert(b, b->keeps, atomic);
|
|
|
|
return atomic;
|
|
}
|
|
|
|
const struct ir3_context_funcs ir3_a6xx_funcs = {
|
|
.emit_intrinsic_load_ssbo = emit_intrinsic_load_ssbo,
|
|
.emit_intrinsic_store_ssbo = emit_intrinsic_store_ssbo,
|
|
.emit_intrinsic_atomic_ssbo = emit_intrinsic_atomic_ssbo,
|
|
.emit_intrinsic_load_image = emit_intrinsic_load_image,
|
|
.emit_intrinsic_store_image = emit_intrinsic_store_image,
|
|
.emit_intrinsic_atomic_image = emit_intrinsic_atomic_image,
|
|
.emit_intrinsic_image_size = emit_intrinsic_image_size,
|
|
.emit_intrinsic_load_global_ir3 = emit_intrinsic_load_global_ir3,
|
|
.emit_intrinsic_store_global_ir3 = emit_intrinsic_store_global_ir3,
|
|
.emit_intrinsic_atomic_global = emit_intrinsic_atomic_global,
|
|
};
|