e28b8530b9
radeonsi: set CB_SHADER_MASK according to SPI color formats
...
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
8667a1aea2
radeonsi: use SPI_SHADER_COL_FORMAT fields instead of export_16bpc
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This does change the behavior slightly:
If a shader writes COLOR[i] and that color buffer isn't bound,
the shader will export MRT_NULL instead and discard the IR tree that
calculates the output. The only exception is alpha-to-coverage, which
requires an alpha export.
v2: - update a comment about 16BPC
- account for MRTZ when when fixing alpha-test/kill
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-22 15:02:40 +01:00
dc96a18d24
radeonsi: don't miss changes to SPI_TMPRING_SIZE
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I'm not sure about the consequences of this bug, but it's definitely
dangerous.
This applies to SI, CIK, VI.
Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-14 19:55:41 +01:00
4ea0febcb0
radeonsi: move POSITION and FACE fragment shader inputs to system values
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And FACE becomes integer instead of float.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-01-13 12:27:28 +01:00
caf3c2abea
radeonsi: simplify gl_FragCoord behavior
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It will become a system value, not an input.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2016-01-13 12:27:28 +01:00
20b9b5d7f5
radeonsi: add struct si_shader_config
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There will be 1 config per variant, which will be a union of configs
from {prolog, main, epilog}. For now, just add the structure.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-07 18:26:06 +01:00
0ffe3d3772
radeonsi: use EXP_NULL for pixel shaders without outputs
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This never happens currently.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-07 18:26:06 +01:00
5f3e6b5b0f
radeonsi: simplify setting the DONE bit for PS exports
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First find out what the last export is and simply set the DONE bit there.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-07 18:26:06 +01:00
e00f3f23b1
radeonsi: set SPI color formats and CB_SHADER_MASK outside of compilation
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-07 18:26:06 +01:00
4e597c25c7
radeonsi: write all MRTs only if there is exactly one output
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This doesn't fix a known bug, but better safe than sorry.
Also, simplify the expression in si_shader.c.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-07 18:26:06 +01:00
746a7a7498
radeonsi: determine SPI_SHADER_Z_FORMAT outside of shader compilation
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-07 18:26:05 +01:00
2cb8bf90cd
radeonsi: determine DB_SHADER_CONTROL outside of shader compilation
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because the API pixel shader binary will not emulate alpha test one day,
so the KILL_ENABLE bit must be determined elsewhere.
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2016-01-07 18:26:05 +01:00
4bb1c8dfec
radeonsi: pass pipe_debug_callback down into si_shader_binary_read (v2)
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This will allow us to send shader debug info.
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> (v1)
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2016-01-02 16:47:23 -05:00
7d1fc2cf51
radeonsi: count compilations in si_compile_llvm
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This changes the count slightly (because of si_generate_gs_copy_shader), but
this is only relevant for the driver-specific num-compilations query. It sets
the stage for the next commit.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-12-29 09:07:01 -05:00
51603af390
radeonsi: use tgsi_shader_info::colors_written
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Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11 15:25:11 +01:00
13eb5f596b
gallium/drivers: Sanitize NULL checks into canonical form
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Use NULL tests of the form `if (ptr)' or `if (!ptr)'.
They do not depend on the definition of the symbol NULL.
Further, they provide the opportunity for the accidental
assignment, are clear and succinct.
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
2015-12-06 17:10:23 +01:00
95e0510916
radeonsi: Rename si_shader::ls_rsrc{1,2} to si_shader::rsrc{1,2}
...
In the future, these will be used by other shaders types.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-11-25 11:03:05 -05:00
3694d58e6c
radeonsi: remove dead code after ES-GS linkage change
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-11-13 19:54:42 +01:00
d79a3449a7
radeonsi: link ES-GS just like LS-HS
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This reduces the shader key for ES.
Use a fixed attrib location based on (semantic name, index).
The ESGS item size is determined by the physical index of the highest ES
output, so it's almost always larger than before, but I think that
shouldn't matter as long as the ESGS ring buffer is large enough.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-11-13 19:54:42 +01:00
b1c5f3faa9
radeonsi: calculate optimal GS ring sizes to fix GS hangs on Tonga
...
I discovered that increasing the ESGS ring size fixes GS hangs on Tonga,
so let's do it properly.
There is now a separate init_config_gs_rings state that is not immutable,
because GS rings are resized when needed.
This also saves some memory. Most apps won't need more than 1MB
per ring per shader engine.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2015-11-13 19:54:42 +01:00
2f5d911ba2
radeonsi: rename si_update_gs_rings
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2015-11-13 19:54:42 +01:00
4acd856088
radeonsi: calculate ESGS_RING_ITEMSIZE in create_shader
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2015-11-13 19:54:42 +01:00
a0cf589961
radeonsi: move maximum gs stream calculation into create_shader
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2015-11-13 19:54:42 +01:00
3ab0c49f04
radeonsi: clean up small duplication in si_shader_gs
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2015-11-13 19:54:42 +01:00
6cc8f6c6a7
gallium/radeon: inline the r600_rings structure
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Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
2015-11-13 19:54:41 +01:00
3a157e6e68
radeonsi: allow unbinding vertex shaders
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Draw calls without a vertex shader are skipped.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-24 00:01:20 +02:00
07b3cc6ecf
radeonsi: allow unbinding pixel shaders and remove the dummy shader
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-24 00:01:20 +02:00
ed95cb3a31
radeonsi: add checks for a NULL pixel shader
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This will allow removing the dummy PS.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-24 00:01:20 +02:00
8339585b12
radeonsi: enable BC_OPTIMIZE if centroid isn't used
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This solution was recommended by a Catalyst developer.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-20 12:56:46 +02:00
9b54ce3362
radeonsi: support thread-safe shaders shared by multiple contexts
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The "current" shader pointer is moved from the CSO to the context, so that
the CSO is mostly immutable.
The only drawback is that the "current" pointer isn't saved when unbinding
a shader and it must be looked up when the shader is bound again.
This is also a prerequisite for multithreaded shader compilation.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-20 12:51:51 +02:00
5bc871a4ca
radeonsi: implement vertex color clamping
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This is only supported in the compatibility profile (without GS and tess).
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-17 21:40:03 +02:00
208d1ed38d
radeonsi: implement fragment color clamping
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using the shader key for now.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-17 21:40:03 +02:00
acc6a07874
radeonsi: clean up other scratch buffer functions
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-17 21:40:03 +02:00
9098d7e9bd
radeonsi: clean up copy-pasted scratch buffer updates
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-17 21:40:03 +02:00
938a1bee34
radeonsi: unify shader create functions
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The shader specifies the processor type, so use that instead.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-17 21:40:03 +02:00
b0167809f1
radeonsi: unify shader delete functions
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-17 21:40:03 +02:00
c4f086f399
radeonsi: remove an unused ctx parameter in si_shader_destroy
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-17 21:40:03 +02:00
b11edf8872
radeonsi: disable NaNs for LS and HS
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They're disabled for all other shaders except compute, but I forgot
to do this for tess stages.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-17 21:40:03 +02:00
13e69805ea
radeonsi: fix a GS hang on VI
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Broken by one of the cleanups: 0d46c3bc9d
2015-10-07 19:18:50 +02:00
b3c55fc669
radeonsi: do force_persample_interp in shaders for non-trivial cases
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-03 22:06:09 +02:00
9652bfcf2d
radeonsi: implement the simple case of force_persample_interp
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-03 22:06:09 +02:00
214de2d815
radeonsi: move SPI_PS_INPUT_ENA/ADDR registers to a separate state
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This will be a derived state used for changing center->sample and
centroid->sample at runtime.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-03 22:06:09 +02:00
2edb060639
gallium/radeon: tell the winsys the exact resource binding types
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Use the priority flags and expand them.
This information will be used for debugging.
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-10-03 22:06:07 +02:00
9932142192
radeonsi: add scratch buffer to the buffer list when it's re-allocated
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Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Cc: mesa-stable@lists.freedesktop.org
2015-09-26 01:51:05 +02:00
b737d9c1dc
radeonsi: don't forget to update scratch relocations for LS, HS, ES shaders
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Cc: 11.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-09-24 19:51:43 +02:00
d556346b35
radeonsi: skip drawing if updating the scratch buffer fails
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Cc: 11.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-09-24 19:51:43 +02:00
1f99b0be7e
radeonsi: skip drawing if PS fails to compile or upload
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Cc: 11.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-09-24 19:51:43 +02:00
237d7cccce
radeonsi: skip drawing if VS, TCS, TES, GS fail to compile or upload
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Cc: 11.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-09-24 19:51:43 +02:00
9b6d9dd7d8
radeonsi: handle fixed-func TCS shader create failure
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Cc: 11.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-09-24 19:51:43 +02:00
5dbadb0257
radeonsi: handle shader precompile failures
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Cc: 11.0 <mesa-stable@lists.freedesktop.org>
Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-09-24 19:51:43 +02:00
Marek Olšák
Nicolai Hähnle
Edward O'Callaghan
Tom Stellard