No more progress loop needed. I'm skeptical we really want a dataflow
approach long-term, though, this is annoyingly expensive.
No shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9421>
We need to update `replacement` with the results of copyprop earlier
within the pass, but after that there's no point running more than once
if we're not going to materialize any new moves.
No shader-db changes.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9421>
UBO index assignment is a bit special in Vulkan, it's based on the
descriptor set layout, which doesn't know about shaders' internal UBOs
(our sysval UBOs). Extend the backend compilers so we can place sysval
UBOs where we want: after all explicit UBOs.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9517>
Some opcodes come with both type and size variants. Right now, only the
size is taken into account. Extend the builder to provide wrappers that
take a nir_type in addition to the bitsize.
While at it, fix wrappers taking a compare operator to use the proper
.{i,s,u} variant based on the comparison (equal and non-equal should
use .i, other comparisons should use .{u,s}).
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9520>
A block that has all its successors empty is not necessarily a leaf
block in the CFG, and removing the JUMP in that causes the shader
to continue executing code from another block instead of exiting.
This reverts commit a496b41d50.
Reviewed-by: Alyssa Rosenzweig <alyssa@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9520>
Instead of lowering it in NIR, use the lookup tables as inputs to a
second-order Taylor expansion. shader-db results aren't amazing but keep
in mind this is without backend CSE yet.
total instructions in shared programs: 115913 -> 115707 (-0.18%)
instructions in affected programs: 3151 -> 2945 (-6.54%)
helped: 12
HURT: 0
Instructions are helped.
total nops in shared programs: 84045 -> 84041 (<.01%)
nops in affected programs: 1571 -> 1567 (-0.25%)
helped: 1
HURT: 7
Inconclusive result (value mean confidence interval includes 0).
total clauses in shared programs: 20498 -> 20489 (-0.04%)
clauses in affected programs: 188 -> 179 (-4.79%)
helped: 6
HURT: 0
Clauses are helped.
total quadwords in shared programs: 90395 -> 90291 (-0.12%)
quadwords in affected programs: 2287 -> 2183 (-4.55%)
helped: 12
HURT: 0
Quadwords are helped.
Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9420>
If there are no destinations, don't produce a _to version, and let the
bare version return the bi_instr.
If there are multiple destinations, take each in the _to version and
don't produce a bare version.
Both cares are probably what you wanted anyway.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9164>
Fixes excessive (and failing) spilling in dEQP-GLES31.functional.ssbo.layout.*
shader-db results are a toss up (I suspect we'd see better results if we
tracked register pressure directly):
total instructions in shared programs: 161377 -> 161377 (0.00%)
total nops in shared programs: 121159 -> 121203 (0.04%)
nops in affected programs: 1839 -> 1883 (2.39%)
Nops are HURT.
total clauses in shared programs: 31604 -> 31606 (<.01%)
clauses in affected programs: 38 -> 40 (5.26%)
Inconclusive result (value mean confidence interval includes 0).
total quadwords in shared programs: 130847 -> 130845 (<.01%)
quadwords in affected programs: 1246 -> 1244 (-0.16%)
Inconclusive result (value mean confidence interval includes 0).
total loops in shared programs: 18 -> 18 (0.00%)
total spills in shared programs: 705 -> 705 (0.00%)
total fills in shared programs: 1645 -> 1645 (0.00%)
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9164>
How many times can I break such a small pass?
Fixes: a805d999c0 ("pan/bi: Fix jumps to terminal block again")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9137>
Here's another edge case: there could be instructions in the last block
after NIR->BIR but they could be optimized out by backend DCE, causing
the block to become a terminal block.
Noticed while toying with geometry shaders.
Fixes: a805d999c0 ("pan/bi: Fix jumps to terminal block again")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9137>
Otherwise we get a bad RA if RT 0 = RT 3 (for example), fixes
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_literal.fragment.sampler2d
Fixes: a6f1500bed ("pan/bi: Workaround BLEND precolour with explicit moves")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9105>
Passes the relevant tests of
dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.*, a few
failures that seem to relate to MRT instead of this.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9105>
Needs to support non-blend shader operation (conversion descriptor
sourced from a sysval), as well as MRT. Fixes fbfetch on Bifrost.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9105>
Don't hardcode the RT to 0. Affects ES3.0 which already exposes MRT --
despite no dEQP coverage of this particular corner case, apps could hit
this in the wild on 21.0. Fixes
dEQP-GLES31.functional.draw_buffers_indexed.overwrite_indexed.common_blend_func_buffer_blend_func
Fixes: c7e1ef7c0c ("panfrost: Advertise ES3.0 on Bifrost")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9105>
All the same formula: calculate an address, emit a pseudoinstruction for
the atomic, emit a postprocess that can be DCE'd if not needed.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Icecream95 <ixn@disroot.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9105>
Multiply by the destination bit size to get the number of bits to
load instead of assuming 32 bits.
Fixes: 2e57684d2d ("pan/bi: Implement load_ubo with the builder")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9071>
While at it, rework the code to avoid copies between intermediate
structures: the pan_shader_info is passed to the compiler context so
the compiler can fill shader information directly.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8963>
So we can re-use the panfrost_sysvals definition outside of the
compiler without dragging the sysval_to_id hash table.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Acked-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8963>
Conceptually same lowering as the DDK, although we're missing a number
of relevant compiler optimizations so the generated code is awful.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8774>
Lowered to #(sz - 1) - clz(x), taking advantage of the machine's
8-bit and 16-bit variants of clz and the widening on the second argument
of ISUB to implement neatly in two instructions.
Note that in NIR, ufind_msb can take any integer type but always output
i32.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8774>
Fixes INSTR_INVALID_ENC fault on dEQP-GLES31.functional.compute.basic.empty
Fixes: bfcdc8f174 ("pan/bi: Add some zero bytes after shaders on Bifrost")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9011>
New scheduler broke this. We need to shuffle some code around so we do
the lower pre-schedule instead of post-schedule (no clauses to work
with).
Fixes: 77933d16d8 ("pan/bi: Switch to new scheduler")
Reported-by: Icecream95 <ixn@disroot.org>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9011>
There are blit shader specific optimizations available.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9002>
Now that we lower FAU correctly, we don't need to write the extra move
explicitly, it will be lowered in later.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8973>
Move and reshape bi_lower_fau to bi_schedule.c. This generalizes the
pass for FAU reads, allowing copyprop to work with FAU without problems.
The pass must run immediately before scheduling. Its post-conditions are
directly specified as the scheduler's pre-conditions. It momentarily
will depend on internal scheduler predicates. It is, for all intents and
purposes, part of the scheduler. Keep it all together.
Finally, adjust the 0 handling to avoid a move at the expense of
constrained scheduling of something like `FADD.v2f16.clamp_0_1 u0, #0`
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8973>
This makes UBO 0 less special, allowing us to generalize uniform
optimization. Note this disables RMU on Midgard as we're about to
rewrite the RMU mechanism.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8973>
Forces a trivial schedule to replicate the old behaviour (for debugging
or benchmarking). Actually the new scheduler is still used, just highly
constrained; the net result should still do what's expected.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
Rather than doing this at pack time like before, or adding extra
constraints to the already overcomplicated scheduler, let's just include
it like a regular FAU source.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
Less critical than other metrics, but still matters for instruction
cache hit rate, and worth being aware of.
And, fine, it makes the scheduler look like a bigger win on another
axis.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
The prefetch buffer size is larger than first thought, but includes
the final clause, so subtract the size of the final clause from the
prefetch size.
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8354>
For G71 but should work on any Bifrost, probably overlaps some CL stuff.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Acked-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8894>
Needs to take a cursor to be applicable outside NIR->BIR of course.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
We would like to reuse the DCE logic to eliminate register writes
without eliminating instructions, as a post-sched pass. This type of
operation will eventually generalize to intrinsics that write a register
*and* have side effects (just atomics, I think).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Ported from Midgard due to the same quirk of our code generation.
Additional validation, though.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
Since 3186401751 ("pan/bi: Suppress disassembly for internal shaders"),
we haven't had a good way to debug blit shaders. I keep rewriting this
patch manually, let's just a debug flag for it.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8723>
The intrinsics covered by the pass are implemented by reading 32-bit
registers, so there is no reason to keep them 64-bit.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8358>
The base offset was ignored, take it into account.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8469>
Saves a few instructions in the common case. Requires refactoring the
TEXS check.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8287>
Shifting by the bitsize was not only wrong, the shift is undefined
behavior when bitsize is 32, causing the assertion to fire on AArch32.
Fixes: 95d62ee7cf ("pan/bi: Add bi_alu_src_index helper")
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8460>
Bifrost will prefetch bytes after the end of shaders, so make sure
these bytes are allocated and zeroed.
Fixes GPU faults in Xonotic.
Suggested-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8428>
Found by adding NOPs to the start of a shader and checking dmesg to
see at what sizes the GPU faulted trying to read the following
non-executable page.
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8428>
Bifrost does not support passing fragment colors through 8 bit registers.
(Rewrote to use NIR helpers -Alyssa)
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Doesn't work for vectors though that's the vectorization branch's
problem to deal with now. Suffices for fragment output.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Needed for fragment output. Not nearly sufficient for actual 8-bit
types in e.g OpenCL.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
It doesn't matter what we pass due to a subtlety in the spec but the
assert is still wrong.
Fixes: 49f38aa9e7 ("pan/bi: Implement fragment_out by builder")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
Where we need a power efficient encoding but don't care about the value
read, corresponding to rNULL in canonical assembly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Tested-by: Maciej Matuszczyk <maccraft123mc@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8427>
A given tuple can only load a single entry from FAU-RAM, so we need a
lowering pass before scheduling to assign FAU and lower the other
sources to moves.
Right now this only handles constants. Uniforms and general FAU are
todo.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8135>
Generates bi_index from nir_alu_src, taking into account the applied
swizzle, and using (swizzle / 32-bit) portion as an offset, to be
applied later during RA. The sub 32-bit portion only applies for 8-bit
and 16-bit instructions, which need to either handle them explicitly as
a swizzle specifier, or lower to a swizzle explicitly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8135>
There's no flag/mode to reflect when a LOD is zero on FETCH instructions,
we have to emit the LOD/CUBE word unconditionally.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
If we don't add this check we clobber fetch mode when a 0 LOD is
specified on a txf instruction.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7653>
v2: Drop register tracking since it was wrong, and meaningful accounting
is tricky for Bifrost (which wants round robin RA for at least some
registers)... we'll cross that bridge when we get there, possibly
preferring a "max liveness" estimate to the raw RA output.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Prevents attempts to spill tied TEXC src/dest, resulting in a crash,
seen in shaders/tesseract/229.shader_test
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
We need that to account for potential swizzling on the source reg.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
Enough to get shaders/humus-celshading/1.shader_test compiling, no idea
if it actually works but it looks reasonable.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
src0 and src1 were mixed leading to invalid varying indices. In order to
fix that properly, we first extend load_vary to pass the immediate index
through a dedicated field and add a special boolean. This way, we don't
have to make sure src0 always contains the index, and can instead match
the src numbering defined in ISA.xml.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7636>
It's just clearer to have dedicated fields encoding the fact that the
LD_VAR should be SPECIAL, and another field storing the special var id.
With this change, the source index know matches the ISA.xml definition.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7636>
Let the compiler pass the update mode instead of inferring from the
constant value.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7636>
Some instructions differ between v6 and v7 and we'll need to know which
architecture we're compiling for if we want to generate the right
instructions.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7530>
Now that we lower uniforms to UBO we can get rid of bi_emit_ld_uniform().
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
The number of src swizzle to initialize depends on the number of source
properties (size and number of components) not the destination ones.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
So we can extend bi_emit_ld_vary() to support centroid and sample modes.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7472>
We need to do the transform specified in the OpenGL spec ourselves, with
some assistance from the hardware.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7408>
Some special instructions are scheduled on the FMA unit, let's add a
new class for this case and rename the old one accordingly.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7408>
nir_tex_instr_src_index() returns a negative result when the requested
source does not exist, but we cast that to an unsigned type thus losing
this information.
Fixes: b83c293674 ("pan/bi: Add basic support for txf_ms")
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7314>
We don't handle undefs explicitly in NIR->BIR which means if they aren't
optimized out they won't be RA'd to anything and then backend RA will
crash (as occurs in a glamor shader seen in MATE).
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7206>
Letting the caller zero-initialize the program object is error prone,
not to mention that resources attached to the program might not be freed
by the caller. Let's simplify that by letting the compiler allocate the
panfrost_program object. Those objects should be freed with ralloc_free().
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7206>
We currently don't support txf_ms instructions specifying a texel offset
src.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7206>
No need to add a COMBINE instruction if TEXC only needs zero or one
staging reg.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7206>
Blend shaders are passed blend inputs through r0-r3. Let's emit a MOV
from those register when we see a load_input intrinsic.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7151>
Blend shaders shouldn't use the blend descriptors stored in the FAU RAM
since this is what triggered the blend shader call in the first place.
The descriptor is instead extracted from the compiler inputs and passed
as a constant to the blend instruction.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7151>
We will need that for blend shaders so they can be passed a return
address and jump back to the fragment shader when they're done.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7151>
This is mapped to the LD_TILE instruction. Note that multi-sample RTs
are not supported yet.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7151>
The current logic assumes blend descriptors are always retrieved from
the blend descriptor slots present in the FAU RAM, but this assumption
no longer stands when we add blend shaders to the mix. In that case we
need to use an 'opaque blend' whose descriptor is passed through
embedded constants.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7151>
The uniform_constant field and BIFROST_SRC_CONST_{LO,HI} definitions
seem to imply that those only deal with embedded constants. Let's
rename them to reflect the fact that they actually encode accesses to
the Fast-Access-Uniform RAM.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7151>
For texelFetch. A few earlier header fields were wrong.
Fixes dEQP-GLES2.functional.texture.mipmap.2d.generate.rgba8888_fastest
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
There's a different LOD format used for TXF that will be able to
accomodate cube maps as well.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
Also uses the 8.8 signed fixed-point format.
dEQP-GLES2.functional.shaders.texture_functions.fragment.texture2d_bias
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
We need to emit some lowering code to convert it to the 8:8 format
expected by the hardware.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
Lower to a COMBINE, which in turn will lower to moves so RA does the
right thing.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
We still need to handle actual complex texturing instructions, as well
as packing, but this is the start.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
And fix the bad assertion that let this slip.
Like combines, nir_op_vec can be vector, and we need to lower this
ourselves. Thankfully, the lowering is simple.
Fixes
dEQP-GLES2.functional.shaders.loops.for_uniform_iterations.nested_tricky_dataflow_1_*
Fixes: b2c6cf2b6d ("pan/bi: Eliminate writemasks in the IR")
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
If a block ends in an unconditional jump, we don't need to record a
fallthrough successor as well, since it's unreachable.
Likely harmless but makes the IR harder to parse with messy CF graphs.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7081>
So we can extend it more easily without having to patch all callers.
Signed-off-by: Boris Brezillon <boris.brezillon@collabora.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7066>
Varying stores require us to generate a LEA_ATTR_IMM instruction, which
is a load.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Fixes: 0aa08ae2f6 ("nir: Split NIR_INTRINSIC_TYPE into separate src/dest indices")
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6985>
We're about to introduce conversion ops which are going to want two
different types. We may as well just split the one we have rather than
end up with three. There are a couple places where this is mildly
inconvenient but most of the time I find it to actually be nicer.
Reviewed-by: Jesse Natalie <jenatali@microsoft.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6945>
This makes it explicit that this intrinsic is only for SSBOs. For the
v3dv driver, we'll be adding a get_ubo_size intrinsic and we want to be
able to distinguish between the two.
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Iago Toral Quiroga <itoral@igalia.com>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6812>
This maps more closely to the hardware, which makes for easier packing.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6749>
Logically, it doesn't matter, but we want the IR to accurately reflect
the hardware behaviour.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6749>
To make register_format packing explicit, and possibly in the future
support the auto mode.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6749>
Needed to select between global, UBO, TLS, and WLS addressing modes,
required to implement loads/stores correctly.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6749>
On FMA, a carry/borrow is required for iaddc/isubb (whereas the ADD
counterparts don't support carrying/borrowing). The trick is to model
this with an extra dummy (ZERO) argument which is free to encode on FMA,
and in the scheduler, "demote" to the non-carried versions if we want to
schedule to ADD.
Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Daniel Stone <daniels@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6749>
This also fixes the inverted last parameter of nir_lower_flrp in most drivers.
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6599>
It was always fneu but naming it fne causes confusion from time to time. So
lets rename it. Later we also want to add other unordered and fne, this is
a smaller preparation for that.
Signed-off-by: Karol Herbst <kherbst@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Connor Abbott <cwabbott0@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/6377>
Alyssa Rosenzweig
Timur Kristóf
Boris Brezillon
Alyssa Rosenzweig
Icecream95
Connor Abbott
Adam Jackson
Jesse Natalie
Jason Ekstrand
Marek Olšák
Karol Herbst
Rhys Perry