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pan/bi: Ensure TEXC src0 is not marked SSA 

Prevents attempts to spill tied TEXC src/dest, resulting in a crash,
seen in shaders/tesseract/229.shader_test

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@collabora.com>
Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7615>
This commit is contained in:
Alyssa Rosenzweig 2020-11-24 14:53:55 -05:00 committed by Marge Bot
parent bbd3a8eadd
commit 45de02bdac
2 changed files with 5 additions and 3 deletions
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1
src/panfrost/bifrost/bi_ra.c
View File

@ -366,6 +366,7 @@ bi_register_allocate(bi_context *ctx)
unsigned both = BI_DATA_REG_SRC | BI_DATA_REG_DEST;
if ((props & both) != both) continue;
assert(ins->src[0] & PAN_IS_REG);
bi_rewrite_uses(ctx, ins->dest, 0, ins->src[0], 0);
ins->dest = ins->src[0];
}

7
src/panfrost/bifrost/bifrost_compile.c
View File

@ -2052,11 +2052,12 @@ emit_texc(bi_context *ctx, nir_tex_instr *instr)
}
}
/* Allocate data registers contiguously */
/* Allocate data registers contiguously. Index must not be marked SSA
* due to a quirk of RA for tied operands, could be fixed eventually */
bi_instruction combine = {
.type = BI_COMBINE,
.dest_type = nir_type_uint32,
.dest = bi_make_temp(ctx),
.dest = bi_make_temp_reg(ctx),
.src_types = {
nir_type_uint32, nir_type_uint32,
nir_type_uint32, nir_type_uint32,
@ -2082,7 +2083,7 @@ emit_texc(bi_context *ctx, nir_tex_instr *instr)
for (unsigned i = 0; i < dreg_index; ++i)
tex.swizzle[0][i] = i;
} else {
tex.src[0] = tex.dest;
tex.src[0] = bi_make_temp_reg(ctx);
}
/* Pass the texture operation descriptor in src2 */