Commit Graph

75155 Commits

Author SHA1 Message Date
Eric Anholt b70a2f4d81 vc4: Add missing progress note in opt_algebraic. 2015-12-11 12:21:22 -08:00
Eric Anholt 5989ef2b0f vc4: Add debugging of the estimated time to run the shader to shader-db. 2015-12-11 12:21:22 -08:00
Eric Anholt 53b2523c6e vc4: Fix handling of sample_mask output.
I apparently broke this in a late refactor, in such a way that I decided
its tests were some of those interminable ones that I should just
blacklist from my testing.  As a result, the refactors related to it were
totally wrong.
2015-12-11 12:21:22 -08:00
Edward O'Callaghan 53609de762 softpipe: enable GL_ARB_viewport_array support, update GL3.txt doc
Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-12-11 20:09:21 +01:00
Edward O'Callaghan 00f97ad5de softpipe: implement some support for multiple viewports
Mostly related to making sure the rasterizer can correctly
pick out the correct scissor box for the current viewport.

Signed-off-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2015-12-11 20:09:21 +01:00
Roland Scheidegger 6c2c1e0ffe draw: don't assume fixed offset for data in struct vertex_info
Otherwise, if struct vertex_info is changed, you're in for some surprises...

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2015-12-11 20:09:21 +01:00
Neil Roberts 583a5778f4 i965/gen9: Don't do fast clears when GL_FRAMEBUFFER_SRGB is enabled
When GL_FRAMEBUFFER_SRGB is enabled any single-sampled renderbuffers
are resolved in intel_update_state because the hardware can't cope
with fast clears on SRGB buffers. In that case it's pointless to do a
fast clear because it will just be immediately resolved.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-12-11 18:05:56 +00:00
Neil Roberts 0033c81344 i965/gen9: Allow fast clears for non-MSRT SRGB buffers
SRGB buffers are not marked as losslessly compressible so previously
they would not be used for fast clears. However in practice the
hardware will never actually see that we are using SRGB buffers for
fast clears if we use the linear equivalent format when clearing and
make sure to resolve the buffer as a linear format before sampling
from it.

This is an important use case because by default the window system
framebuffers are created as SRGB so without this fast clears won't be
used there.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-12-11 18:05:56 +00:00
Neil Roberts 82d459a423 i965/gen9: Resolve SRGB color buffers when GL_FRAMEBUFFER_SRGB enabled
SKL can't cope with the CCS buffer for SRGB buffers. Normally the
hardware won't see the SRGB formats because when GL_FRAMEBUFFER_SRGB
is disabled these get mapped to their linear equivalents. In order to
avoid relying on the CCS buffer when it is enabled this patch now
makes it flush the renderbuffers.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-12-11 18:05:56 +00:00
Neil Roberts eb291d7013 i965/gen8+: Don't upload the MCS buffer for single-sampled textures
For single-sampled textures the MCS buffer is only used to implement
fast clears. However the surface always needs to be resolved before
being used as a texture anyway so the the MCS buffer doesn't actually
achieve anything. This is important for Gen9 because in that case SRGB
surfaces are not supported for fast clears and we don't want the
hardware to see the MCS buffer in that case.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-12-11 18:05:56 +00:00
Neil Roberts 44902ed1fa i965/meta-fast-clear: Disable GL_FRAMEBUFFER_SRGB during clear
Adds MESA_META_FRAMEBUFFER_SRGB to the meta save state so that
GL_FRAMEBUFFER_SRGB will be disabled when performing the fast clear.
That way the render surface state will be programmed with the linear
equivalent format during the clear. This is important for Gen9 because
the SRGB formats are not marked as losslessly compressible so in
theory they aren't support for fast clears. It shouldn't make any
difference whether GL_FRAMEBUFFER_SRGB is enabled for the fast clear
operation because the color is not actually written to the framebuffer
so there is no chance for the hardware to apply the SRGB conversion on
it anyway.

Reviewed-by: Topi Pohjolainen <topi.pohjolainen@intel.com>
2015-12-11 18:05:56 +00:00
Marek Olšák 369afdb7b6 winsys/amdgpu: clear the buffer cache on mmap failure and try again
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:13 +01:00
Marek Olšák 84a38bfc29 winsys/radeon: clear the buffer cache on mmap failure and try again
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:13 +01:00
Marek Olšák eb1e1af676 winsys/amdgpu: clear the buffer cache on allocation failure and try again
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:13 +01:00
Marek Olšák f9d6fe8001 winsys/radeon: clear the buffer cache on allocation failure and try again
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:13 +01:00
Marek Olšák cf811faeff gallium/radeon: remove radeon_winsys_cs_handle
"radeon_winsys_cs_handle *cs_buf" is now equivalent to "pb_buffer *buf".

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:13 +01:00
Marek Olšák cf422d20ff winsys/radeon: use pb_cache instead of pb_cache_manager
This is a prerequisite for the removal of radeon_winsys_cs_handle.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:13 +01:00
Marek Olšák ebc9497fcb winsys/radeon: use radeon_bomgr less
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:13 +01:00
Marek Olšák a450f96ba9 winsys/radeon: rename radeon_bomgr_init_functions
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:13 +01:00
Marek Olšák 38ac20f7dd winsys/radeon: move variables from radeon_bomgr to radeon_drm_winsys
radeon_bomgr is going away.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:13 +01:00
Marek Olšák 3d090223ef winsys/radeon: remove redundant radeon_bomgr::va
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:12 +01:00
Marek Olšák 1e05812fcd winsys/amdgpu: don't use the "rws" abbreviation for amdgpu_winsys
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:12 +01:00
Marek Olšák 6f4e74d165 winsys/amdgpu: use pb_cache instead of pb_cache_manager
This is a prerequisite for the removal of radeon_winsys_cs_handle.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:12 +01:00
Marek Olšák 3fbf250dfa gallium/pb_bufmgr_cache: use the new pb_cache module
Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:12 +01:00
Marek Olšák 2b396eeed9 gallium/pb_cache: add a copy of cache bufmgr independent of pb_manager
This simplified (basically duplicated) version of pb_cache_manager will
allow removing some ugly hacks from radeon and amdgpu winsyses and
flatten simplify their design.

The difference is that winsyses must manually add buffers to the cache
in "destroy" functions and the cache doesn't know about the buffers before
that. The integration is therefore trivial and the impact on the winsys
design is negligible.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Acked-by: Michel Dänzer <michel.daenzer@amd.com>
2015-12-11 15:25:12 +01:00
Marek Olšák 1a24f443b4 radeonsi: implement fast stencil clear
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11 15:25:12 +01:00
Marek Olšák 8ee96ce834 radeonsi: re-enable Hyper-Z for stencil
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11 15:25:12 +01:00
Marek Olšák 99e63338fb r600g: remove a Hyper-Z workaround that's likely not needed anymore
FORCE_OFF == 0, no need to set that

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11 15:25:12 +01:00
Marek Olšák 96e8d38ac4 r600g: re-enable Hyper-Z for stencil on Evergreen & Cayman
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11 15:25:12 +01:00
Marek Olšák d3c08309ab gallium/radeon: fix Hyper-Z hangs by programming PA_SC_MODE_CNTL_1 correctly
This is the recommended setting according to hw people and it makes Hyper-Z
stable. Just the two magic states.

This fixes Evergreen, Cayman, SI, CI, VI (using the Cayman code).

Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11 15:25:12 +01:00
Marek Olšák 7c29bf26bb radeonsi: don't use the CP DMA workaround on Fiji and newer
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11 15:25:12 +01:00
Marek Olšák 787ada6bf6 radeonsi: apply the streamout workaround to Fiji as well
Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11 15:25:12 +01:00
Marek Olšák 62d82193b8 radeonsi: also print hexadecimal values for register fields in the IB parser
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-12-11 15:25:12 +01:00
Marek Olšák de887ba90c radeonsi: implement RB+ for Stoney (v2)
v2: fix dual source blending

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11 15:25:12 +01:00
Marek Olšák 0f9519b938 radeonsi: don't call of u_prims_for_vertices for patches and rectangles
Both caused a crash due to a division by zero in that function.
This is an alternative fix.

Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
2015-12-11 15:25:12 +01:00
Marek Olšák 51603af390 radeonsi: use tgsi_shader_info::colors_written
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11 15:25:11 +01:00
Marek Olšák b5b87c4ed1 r600g: write all MRTs only if there is exactly one output (fixes a hang)
This fixes a hang in
piglit/arb_blend_func_extended-fbo-extended-blend-pattern_gles2 on REDWOOD.

Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11 15:25:11 +01:00
Marek Olšák eb4813a952 tgsi/scan: add flag colors_written
This is a prerequisite for the following r600g fix.

Cc: 11.0 11.1 <mesa-stable@lists.freedesktop.org>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2015-12-11 15:25:11 +01:00
Marek Olšák 37208c4fd7 Revert "radeonsi: disable DCC on Stoney"
This reverts commit 32f05fadbb.

It turned out the problem with Stoney was caused by incorrect handling of
a non-power-two VRAM size in the kernel driver.
This is an optional BIOS setting and can be worked around by choosing
a different VRAM size in the BIOS.

Cc: 11.1 <mesa-stable@lists.freedesktop.org>
2015-12-11 15:25:11 +01:00
Timothy Arceri 4b9a79b7b8 nir: silence uninitialized warning
Reviewed-by: Rob Clark <robdclark@gmail.com>
2015-12-11 19:26:20 +11:00
Dave Airlie 18ad641c3b mesa/shader: return correct attribute location for double matrix arrays
If we have a dmat2[4], then dmat2[0] is at 17, dmat2[1] at 19,
dmat2[2] at 21 etc. The old code was returning 17,18,19.

I think this code is also wrong for float matricies as well.

There is now a piglit for the float case.

This partly fixes:
GL41-CTS.vertex_attrib_64bit.limits_test

[airlied: update with Tapani suggestion to clean it up].

Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-11 16:28:29 +10:00
Roland Scheidegger 64c59b0624 draw: fix clipping with linear interpolated values and gl_ClipVertex
Discovered this when working on other clip code, apparently didn't work
correctly - the combination of linear interpolated values and using
gl_ClipVertex produced wrong values (failing all such combinations
in piglits glsl-1.30 interpolation tests, named
interpolation-noperspective-XXX-vertex).
Use the pre-clip-pos values when determining the interpolation factor to
fix this.
Noone really understands this code well, but everybody agrees this looks
sane... This fixes all those failing tests (10 in total) both with
the llvm and non-llvm draw paths, with no piglit regressions.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
2015-12-11 02:21:39 +01:00
Dave Airlie 5362e53a06 r600: add missing return value check.
Pointed out by coverity scan.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2015-12-11 09:37:20 +10:00
Jason Ekstrand 78b81be627 nir: Get rid of *_indirect variants of input/output load/store intrinsics
There is some special-casing needed in a competent back-end.  However, they
can do their special-casing easily enough based on whether or not the
offset is a constant.  In the mean time, having the *_indirect variants
adds special cases a number of places where they don't need to be and, in
general, only complicates things.  To complicate matters, NIR had no way to
convdert an indirect load/store to a direct one in the case that the
indirect was a constant so we would still not really get what the back-ends
wanted.  The best solution seems to be to get rid of the *_indirect
variants entirely.

This commit is a bunch of different changes squashed together:

 - nir: Get rid of *_indirect variants of input/output load/store intrinsics
 - nir/glsl: Stop handling UBO/SSBO load/stores differently depending on indirect
 - nir/lower_io: Get rid of load/store_foo_indirect
 - i965/fs: Get rid of load/store_foo_indirect
 - i965/vec4: Get rid of load/store_foo_indirect
 - tgsi_to_nir: Get rid of load/store_foo_indirect
 - ir3/nir: Use the new unified io intrinsics
 - vc4: Do all uniform loads with byte offsets
 - vc4/nir: Use the new unified io intrinsics
 - vc4: Fix load_user_clip_plane crash
 - vc4: add missing src for store outputs
 - vc4: Fix state uniforms
 - nir/lower_clip: Update to the new load/store intrinsics
 - nir/lower_two_sided_color: Update to the new load intrinsic

NIR and i965 changes are

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>

NIR indirect declarations and vc4 changes are

Reviewed-by: Eric Anholt <eric@anholt.net>

ir3 changes are

Reviewed-by: Rob Clark <robdclark@gmail.com>

NIR changes are

Acked-by: Rob Clark <robdclark@gmail.com>
2015-12-10 12:25:16 -08:00
Jason Ekstrand f3970fad9e i965/fs_nir: Refactor store_output, load_input, and load_uniform
There was way too much incrementing of things going on.  Instead, let's
just start everything off at the right base location, and then increment in
the loop.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2015-12-10 12:25:16 -08:00
Patrick Rudolph 79bff488bc gallium/util: return correct number of bound vertex buffers
In case a state tracker unbinds every slot by a seperate
pipe->set_vertex_buffers() call, starting from slot zero, the number
of bound buffers would not reach zero at all.
The current algorithm does not account for pre-existing holes in the
buffer list.

Unbinding all buffers at once or starting at the top-most slot results
in correct behaviour.

Calculating the correct number of bound buffers fixes a NULL pointer
dereference in nvc0_validate_vertex_buffers_shared().

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93004
Signed-off-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Ilia Mirkin <imirkin@alum.mit.edu>
Cc: "11.0 11.1" <mesa-stable@lists.freedesktop.org>
2015-12-10 13:55:53 -05:00
Neil Roberts ba67739b66 blit: Don't take into account the Mesa format when checking MSRT blit
According to the GLES3 spec, blitting between multisample FBOs with
different internal formats should not be allowed. The
compatible_resolve_formats function implements this check. Previously
it had a shortcut where if the Mesa formats of the two renderbuffers
were the same then it would assume the blit is ok. However some
drivers map different internal formats to the same Mesa format, for
example it might implement both GL_RGB and GL_RGBA textures with
MESA_FORMAT_R8G8B8A_UNORM. The function is used to generate a GL error
according to what the GL spec requires so the blit should not be
allowed in that case. This patch just removes the shortcut so that it
only ever looks at the internal format.

Note that I posted a related patch to disable this check altogether
for desktop GL. However this function is still used on GLES3 because
there are conformance tests that require this behaviour so this patch
is still useful.

Cc: Marek Olšák <maraeo@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2015-12-10 11:03:58 +00:00
Neil Roberts 3f10774cba i965: Check base format to determine whether to use tiled memcpy
The tiled memcpy doesn't work for copying from RGBX to RGBA because it
doesn't override the alpha component to 1.0. Commit 2cebaac479 added
a check to disable it for RGBX formats by looking at the TexFormat.
However a lot of the rest of the code base is written with the
assumption that an RGBA texture can be used internally to implement a
GL_RGB texture. If that is done then this check breaks. This patch
makes it instead check the base format of the texture which I think
more directly matches the intention.

Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com>
2015-12-10 11:03:49 +00:00
Neil Roberts 9a31d9870b i965/gen8: Allow rendering to B8G8R8X8
Since Gen8 this is allowed as a rendering target so we don't need to
override it to B8G8R8A8. This is helpful on Gen9+ where using this
override causes fast clears not to work.

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2015-12-10 11:03:49 +00:00
Neil Roberts d151338594 i965/gen9: Allow fast clear for MSRT formats matching render
Previously fast clear was disallowed on Gen9 for MSRTs with the claim
that some formats don't work but we didn't understand why. On further
investigation it seems the formats that don't work are the ones where
the render surface format is being overriden to a different format
than the one used for texturing. The one used for texturing is not
actually a renderable format. It arguably makes sense that the sampler
hardware doesn't handle the fast color correctly in these cases
because it shouldn't be possible to end up with a fast cleared surface
that is non-renderable.

This patch changes the limitation to prevent fast clear for surfaces
where the format for rendering is overriden.

Reviewed-by: Ben Widawsky <benjamin.widawsky@intel.com>
2015-12-10 11:03:49 +00:00