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winsys/amdgpu: use pb_cache instead of pb_cache_manager 

This is a prerequisite for the removal of radeon_winsys_cs_handle.

Reviewed-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
This commit is contained in:
Marek Olšák 2015-12-06 20:57:05 +01:00
parent 3fbf250dfa
commit 6f4e74d165
4 changed files with 77 additions and 172 deletions
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208
src/gallium/winsys/amdgpu/drm/amdgpu_bo.c
View File

@ -37,46 +37,15 @@
#include <xf86drm.h>
#include <stdio.h>
static const struct pb_vtbl amdgpu_winsys_bo_vtbl;
static inline struct amdgpu_winsys_bo *amdgpu_winsys_bo(struct pb_buffer *bo)
{
assert(bo->vtbl == &amdgpu_winsys_bo_vtbl);
return (struct amdgpu_winsys_bo *)bo;
}
struct amdgpu_bomgr {
struct pb_manager base;
struct amdgpu_winsys *rws;
};
static struct amdgpu_winsys *get_winsys(struct pb_manager *mgr)
{
return ((struct amdgpu_bomgr*)mgr)->rws;
}
static struct amdgpu_winsys_bo *get_amdgpu_winsys_bo(struct pb_buffer *_buf)
{
struct amdgpu_winsys_bo *bo = NULL;
if (_buf->vtbl == &amdgpu_winsys_bo_vtbl) {
bo = amdgpu_winsys_bo(_buf);
} else {
struct pb_buffer *base_buf;
pb_size offset;
pb_get_base_buffer(_buf, &base_buf, &offset);
if (base_buf->vtbl == &amdgpu_winsys_bo_vtbl)
bo = amdgpu_winsys_bo(base_buf);
}
return bo;
}
static bool amdgpu_bo_wait(struct pb_buffer *_buf, uint64_t timeout,
enum radeon_bo_usage usage)
{
struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(_buf);
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
struct amdgpu_winsys *ws = bo->rws;
int i;
@ -154,7 +123,7 @@ static enum radeon_bo_domain amdgpu_bo_get_initial_domain(
return ((struct amdgpu_winsys_bo*)buf)->initial_domain;
}
static void amdgpu_bo_destroy(struct pb_buffer *_buf)
void amdgpu_bo_destroy(struct pb_buffer *_buf)
{
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
int i;
@ -173,6 +142,16 @@ static void amdgpu_bo_destroy(struct pb_buffer *_buf)
FREE(bo);
}
static void amdgpu_bo_destroy_or_cache(struct pb_buffer *_buf)
{
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
if (bo->use_reusable_pool)
pb_cache_add_buffer(&bo->cache_entry);
else
amdgpu_bo_destroy(_buf);
}
static void *amdgpu_bo_map(struct radeon_winsys_cs_handle *buf,
struct radeon_winsys_cs *rcs,
enum pipe_transfer_usage usage)
@ -260,42 +239,18 @@ static void amdgpu_bo_unmap(struct radeon_winsys_cs_handle *buf)
amdgpu_bo_cpu_unmap(bo->bo);
}
static void amdgpu_bo_get_base_buffer(struct pb_buffer *buf,
struct pb_buffer **base_buf,
unsigned *offset)
{
*base_buf = buf;
*offset = 0;
}
static enum pipe_error amdgpu_bo_validate(struct pb_buffer *_buf,
struct pb_validate *vl,
unsigned flags)
{
/* Always pinned */
return PIPE_OK;
}
static void amdgpu_bo_fence(struct pb_buffer *buf,
struct pipe_fence_handle *fence)
{
}
static const struct pb_vtbl amdgpu_winsys_bo_vtbl = {
amdgpu_bo_destroy,
NULL, /* never called */
NULL, /* never called */
amdgpu_bo_validate,
amdgpu_bo_fence,
amdgpu_bo_get_base_buffer,
amdgpu_bo_destroy_or_cache
/* other functions are never called */
};
static struct pb_buffer *amdgpu_bomgr_create_bo(struct pb_manager *_mgr,
pb_size size,
const struct pb_desc *desc)
static struct amdgpu_winsys_bo *amdgpu_create_bo(struct amdgpu_winsys *rws,
unsigned size,
unsigned alignment,
unsigned usage,
enum radeon_bo_domain initial_domain,
unsigned flags)
{
struct amdgpu_winsys *rws = get_winsys(_mgr);
struct amdgpu_bo_desc *rdesc = (struct amdgpu_bo_desc*)desc;
struct amdgpu_bo_alloc_request request = {0};
amdgpu_bo_handle buf_handle;
uint64_t va = 0;
@ -303,23 +258,24 @@ static struct pb_buffer *amdgpu_bomgr_create_bo(struct pb_manager *_mgr,
amdgpu_va_handle va_handle;
int r;
assert(rdesc->initial_domain & RADEON_DOMAIN_VRAM_GTT);
assert(initial_domain & RADEON_DOMAIN_VRAM_GTT);
bo = CALLOC_STRUCT(amdgpu_winsys_bo);
if (!bo) {
return NULL;
}
pb_cache_init_entry(&rws->bo_cache, &bo->cache_entry, &bo->base);
request.alloc_size = size;
request.phys_alignment = desc->alignment;
request.phys_alignment = alignment;
if (rdesc->initial_domain & RADEON_DOMAIN_VRAM) {
if (initial_domain & RADEON_DOMAIN_VRAM) {
request.preferred_heap |= AMDGPU_GEM_DOMAIN_VRAM;
if (rdesc->flags & RADEON_FLAG_CPU_ACCESS)
if (flags & RADEON_FLAG_CPU_ACCESS)
request.flags |= AMDGPU_GEM_CREATE_CPU_ACCESS_REQUIRED;
}
if (rdesc->initial_domain & RADEON_DOMAIN_GTT) {
if (initial_domain & RADEON_DOMAIN_GTT) {
request.preferred_heap |= AMDGPU_GEM_DOMAIN_GTT;
if (rdesc->flags & RADEON_FLAG_GTT_WC)
if (flags & RADEON_FLAG_GTT_WC)
request.flags |= AMDGPU_GEM_CREATE_CPU_GTT_USWC;
}
@ -327,13 +283,13 @@ static struct pb_buffer *amdgpu_bomgr_create_bo(struct pb_manager *_mgr,
if (r) {
fprintf(stderr, "amdgpu: Failed to allocate a buffer:\n");
fprintf(stderr, "amdgpu: size : %d bytes\n", size);
fprintf(stderr, "amdgpu: alignment : %d bytes\n", desc->alignment);
fprintf(stderr, "amdgpu: domains : %d\n", rdesc->initial_domain);
fprintf(stderr, "amdgpu: alignment : %d bytes\n", alignment);
fprintf(stderr, "amdgpu: domains : %d\n", initial_domain);
goto error_bo_alloc;
}
r = amdgpu_va_range_alloc(rws->dev, amdgpu_gpu_va_range_general,
size, desc->alignment, 0, &va, &va_handle, 0);
size, alignment, 0, &va, &va_handle, 0);
if (r)
goto error_va_alloc;
@ -342,23 +298,23 @@ static struct pb_buffer *amdgpu_bomgr_create_bo(struct pb_manager *_mgr,
goto error_va_map;
pipe_reference_init(&bo->base.reference, 1);
bo->base.alignment = desc->alignment;
bo->base.usage = desc->usage;
bo->base.alignment = alignment;
bo->base.usage = usage;
bo->base.size = size;
bo->base.vtbl = &amdgpu_winsys_bo_vtbl;
bo->rws = rws;
bo->bo = buf_handle;
bo->va = va;
bo->va_handle = va_handle;
bo->initial_domain = rdesc->initial_domain;
bo->initial_domain = initial_domain;
bo->unique_id = __sync_fetch_and_add(&rws->next_bo_unique_id, 1);
if (rdesc->initial_domain & RADEON_DOMAIN_VRAM)
if (initial_domain & RADEON_DOMAIN_VRAM)
rws->allocated_vram += align(size, rws->gart_page_size);
else if (rdesc->initial_domain & RADEON_DOMAIN_GTT)
else if (initial_domain & RADEON_DOMAIN_GTT)
rws->allocated_gtt += align(size, rws->gart_page_size);
return &bo->base;
return bo;
error_va_map:
amdgpu_va_range_free(va_handle);
@ -371,48 +327,15 @@ error_bo_alloc:
return NULL;
}
static void amdgpu_bomgr_flush(struct pb_manager *mgr)
{
/* NOP */
}
/* This is for the cache bufmgr. */
static boolean amdgpu_bomgr_is_buffer_busy(struct pb_manager *_mgr,
struct pb_buffer *_buf)
bool amdgpu_bo_can_reclaim(struct pb_buffer *_buf)
{
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
if (amdgpu_bo_is_referenced_by_any_cs(bo)) {
return TRUE;
return false;
}
if (!amdgpu_bo_wait((struct pb_buffer*)bo, 0, RADEON_USAGE_READWRITE)) {
return TRUE;
}
return FALSE;
}
static void amdgpu_bomgr_destroy(struct pb_manager *mgr)
{
FREE(mgr);
}
struct pb_manager *amdgpu_bomgr_create(struct amdgpu_winsys *rws)
{
struct amdgpu_bomgr *mgr;
mgr = CALLOC_STRUCT(amdgpu_bomgr);
if (!mgr)
return NULL;
mgr->base.destroy = amdgpu_bomgr_destroy;
mgr->base.create_buffer = amdgpu_bomgr_create_bo;
mgr->base.flush = amdgpu_bomgr_flush;
mgr->base.is_buffer_busy = amdgpu_bomgr_is_buffer_busy;
mgr->rws = rws;
return &mgr->base;
return amdgpu_bo_wait(_buf, 0, RADEON_USAGE_READWRITE);
}
static unsigned eg_tile_split(unsigned tile_split)
@ -453,7 +376,7 @@ static void amdgpu_bo_get_tiling(struct pb_buffer *_buf,
unsigned *mtilea,
bool *scanout)
{
struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(_buf);
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
struct amdgpu_bo_info info = {0};
uint32_t tiling_flags;
int r;
@ -494,7 +417,7 @@ static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
uint32_t pitch,
bool scanout)
{
struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(_buf);
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(_buf);
struct amdgpu_bo_metadata metadata = {0};
uint32_t tiling_flags = 0;
@ -526,7 +449,7 @@ static void amdgpu_bo_set_tiling(struct pb_buffer *_buf,
static struct radeon_winsys_cs_handle *amdgpu_get_cs_handle(struct pb_buffer *_buf)
{
/* return a direct pointer to amdgpu_winsys_bo. */
return (struct radeon_winsys_cs_handle*)get_amdgpu_winsys_bo(_buf);
return (struct radeon_winsys_cs_handle*)_buf;
}
static struct pb_buffer *
@ -538,9 +461,8 @@ amdgpu_bo_create(struct radeon_winsys *rws,
enum radeon_bo_flag flags)
{
struct amdgpu_winsys *ws = amdgpu_winsys(rws);
struct amdgpu_bo_desc desc;
struct pb_manager *provider;
struct pb_buffer *buffer;
struct amdgpu_winsys_bo *bo;
unsigned usage = 0;
/* Don't use VRAM if the GPU doesn't have much. This is only the initial
* domain. The kernel is free to move the buffer if it wants to.
@ -552,9 +474,6 @@ amdgpu_bo_create(struct radeon_winsys *rws,
flags = RADEON_FLAG_GTT_WC;
}
memset(&desc, 0, sizeof(desc));
desc.base.alignment = alignment;
/* Align size to page size. This is the minimum alignment for normal
* BOs. Aligning this here helps the cached bufmgr. Especially small BOs,
* like constant/uniform buffers, can benefit from better and more reuse.
@ -565,26 +484,28 @@ amdgpu_bo_create(struct radeon_winsys *rws,
* might consider different sets of domains / flags compatible
*/
if (domain == RADEON_DOMAIN_VRAM_GTT)
desc.base.usage = 1 << 2;
usage = 1 << 2;
else
desc.base.usage = domain >> 1;
assert(flags < sizeof(desc.base.usage) * 8 - 3);
desc.base.usage |= 1 << (flags + 3);
usage = domain >> 1;
assert(flags < sizeof(usage) * 8 - 3);
usage |= 1 << (flags + 3);
desc.initial_domain = domain;
desc.flags = flags;
/* Get a buffer from the cache. */
if (use_reusable_pool) {
bo = (struct amdgpu_winsys_bo*)
pb_cache_reclaim_buffer(&ws->bo_cache, size, alignment,
usage);
if (bo)
return &bo->base;
}
/* Assign a buffer manager. */
if (use_reusable_pool)
provider = ws->cman;
else
provider = ws->kman;
buffer = provider->create_buffer(provider, size, &desc.base);
if (!buffer)
/* Create a new one. */
bo = amdgpu_create_bo(ws, size, alignment, usage, domain, flags);
if (!bo)
return NULL;
return (struct pb_buffer*)buffer;
bo->use_reusable_pool = use_reusable_pool;
return &bo->base;
}
static struct pb_buffer *amdgpu_bo_from_handle(struct radeon_winsys *rws,
@ -680,12 +601,11 @@ static boolean amdgpu_bo_get_handle(struct pb_buffer *buffer,
unsigned stride,
struct winsys_handle *whandle)
{
struct amdgpu_winsys_bo *bo = get_amdgpu_winsys_bo(buffer);
struct amdgpu_winsys_bo *bo = amdgpu_winsys_bo(buffer);
enum amdgpu_bo_handle_type type;
int r;
if ((void*)bo != (void*)buffer)
pb_cache_manager_remove_buffer(buffer);
bo->use_reusable_pool = false;
switch (whandle->type) {
case DRM_API_HANDLE_TYPE_SHARED:
@ -767,7 +687,7 @@ static uint64_t amdgpu_bo_get_va(struct radeon_winsys_cs_handle *buf)
return ((struct amdgpu_winsys_bo*)buf)->va;
}
void amdgpu_bomgr_init_functions(struct amdgpu_winsys *ws)
void amdgpu_bo_init_functions(struct amdgpu_winsys *ws)
{
ws->base.buffer_get_cs_handle = amdgpu_get_cs_handle;
ws->base.buffer_set_tiling = amdgpu_bo_set_tiling;

14
src/gallium/winsys/amdgpu/drm/amdgpu_bo.h
View File

@ -36,15 +36,9 @@
#include "amdgpu_winsys.h"
#include "pipebuffer/pb_bufmgr.h"
struct amdgpu_bo_desc {
struct pb_desc base;
enum radeon_bo_domain initial_domain;
unsigned flags;
};
struct amdgpu_winsys_bo {
struct pb_buffer base;
struct pb_cache_entry cache_entry;
struct amdgpu_winsys *rws;
void *user_ptr; /* from buffer_from_ptr */
@ -54,6 +48,7 @@ struct amdgpu_winsys_bo {
amdgpu_va_handle va_handle;
uint64_t va;
enum radeon_bo_domain initial_domain;
bool use_reusable_pool;
/* how many command streams is this bo referenced in? */
int num_cs_references;
@ -67,8 +62,9 @@ struct amdgpu_winsys_bo {
struct pipe_fence_handle *fence[RING_LAST];
};
struct pb_manager *amdgpu_bomgr_create(struct amdgpu_winsys *rws);
void amdgpu_bomgr_init_functions(struct amdgpu_winsys *ws);
bool amdgpu_bo_can_reclaim(struct pb_buffer *_buf);
void amdgpu_bo_destroy(struct pb_buffer *_buf);
void amdgpu_bo_init_functions(struct amdgpu_winsys *ws);
static inline
void amdgpu_winsys_bo_reference(struct amdgpu_winsys_bo **dst,

22
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
View File

@ -304,11 +304,8 @@ static void amdgpu_winsys_destroy(struct radeon_winsys *rws)
struct amdgpu_winsys *ws = (struct amdgpu_winsys*)rws;
pipe_mutex_destroy(ws->bo_fence_lock);
ws->cman->destroy(ws->cman);
ws->kman->destroy(ws->kman);
pb_cache_deinit(&ws->bo_cache);
AddrDestroy(ws->addrlib);
amdgpu_device_deinitialize(ws->dev);
FREE(rws);
}
@ -461,13 +458,9 @@ amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
goto fail;
/* Create managers. */
ws->kman = amdgpu_bomgr_create(ws);
if (!ws->kman)
goto fail;
ws->cman = pb_cache_manager_create(ws->kman, 500000, 2.0f, 0,
(ws->info.vram_size + ws->info.gart_size) / 8);
if (!ws->cman)
goto fail;
pb_cache_init(&ws->bo_cache, 500000, 2.0f, 0,
(ws->info.vram_size + ws->info.gart_size) / 8,
amdgpu_bo_destroy, amdgpu_bo_can_reclaim);
/* init reference */
pipe_reference_init(&ws->reference, 1);
@ -480,7 +473,7 @@ amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
ws->base.query_value = amdgpu_query_value;
ws->base.read_registers = amdgpu_read_registers;
amdgpu_bomgr_init_functions(ws);
amdgpu_bo_init_functions(ws);
amdgpu_cs_init_functions(ws);
amdgpu_surface_init_functions(ws);
@ -509,10 +502,7 @@ amdgpu_winsys_create(int fd, radeon_screen_create_t screen_create)
fail:
pipe_mutex_unlock(dev_tab_mutex);
if (ws->cman)
ws->cman->destroy(ws->cman);
if (ws->kman)
ws->kman->destroy(ws->kman);
pb_cache_deinit(&ws->bo_cache);
FREE(ws);
return NULL;
}

5
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.h
View File

@ -32,6 +32,7 @@
#ifndef AMDGPU_WINSYS_H
#define AMDGPU_WINSYS_H
#include "pipebuffer/pb_cache.h"
#include "gallium/drivers/radeon/radeon_winsys.h"
#include "addrlib/addrinterface.h"
#include "os/os_thread.h"
@ -42,6 +43,7 @@ struct amdgpu_cs;
struct amdgpu_winsys {
struct radeon_winsys base;
struct pipe_reference reference;
struct pb_cache bo_cache;
amdgpu_device_handle dev;
@ -57,9 +59,6 @@ struct amdgpu_winsys {
struct radeon_info info;
struct pb_manager *kman;
struct pb_manager *cman;
struct amdgpu_gpu_info amdinfo;
ADDR_HANDLE addrlib;
uint32_t rev_id;