Commit Graph

52785 Commits

Author SHA1 Message Date
Michel Dänzer 30b303743d radeonsi: Handle TGSI_SEMANTIC_FOG.
Fixes exponential fog. The pixel shaders for linear fog seem to get
miscompiled still somehow.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-07 16:12:04 +02:00
Michel Dänzer 3144821ef6 radeon/llvm: Match fexp2 for SI.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-07 12:16:32 +02:00
Brian Paul 043f66204b glapi/glx: rename 'table' variable to 'disp_table'
This fixes an issue where the local 'table' variable was hiding the
function parameter name in glGetColorTable(..., void *table).

This should be OK as long as there's never a GL entrypoint that uses
'disp_table' as a parameter name.

Note: This is a candidate for the 9.0 branch.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2012-09-06 18:58:49 -06:00
Brian Paul 14f55869a4 glx: move 'prime' var into #ifdef'd code block
To silence unused var warning.

Reviewed-by: Jose Fonseca <jfonseca@vmware.com>
2012-09-06 18:58:49 -06:00
Kenneth Graunke 815d9d405c i965: Fix primitive restart on Haswell.
Haswell moved the "Cut Index Enable" bit from the INDEX_BUFFER packet to
a new 3DSTATE_VF packet, so we need to emit that.  Also, it requires us
to specify the cut index rather than assuming it's 0xffffffff.

This adds a new Haswell-specific tracked state atom to gen7_atoms.
Normally, we would create a new generation-specific atom list, but since
there's only one difference over Ivybridge so far, I chose to simply
make it return without doing any work on non-Haswell systems.

Fixes five piglit tests:
- general/primitive-restart-DISABLE_VBO
- general/primitive-restart-VBO_COMBINED_VERTEX_AND_INDEX
- general/primitive-restart-VBO_INDEX_ONLY
- general/primitive-restart-VBO_SEPARATE_VERTEX_AND_INDEX
- general/primitive-restart-VBO_VERTEX_ONLY

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2012-09-06 16:39:48 -07:00
Matt Turner 058fb00716 build: Disable building of d3d1x
It's broken and unmaintained, and I'm tired of seeing bug reports about
it.
2012-09-06 16:20:18 -07:00
Paul Berry 78a34d868d intel: avoid undefined variable warnings in intel_screen.c
Reviewed-by: Matt Turner <mattst88@gmail.com>
2012-09-06 14:49:25 -07:00
Jerome Glisse 5ceb87286f r600g: order atom emission v3
To avoid GPU lockup registers must be emited in a specific order
(no kidding ...). This patch rework atom emission so order in which
atom are emited in respect to each other is always the same. We
don't have any informations on what is the correct order so order
will need to be infered from fglrx command stream.

v2: add comment warning that atom order should not be taken lightly
v3: rebase on top of alphatest atom fix

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-09-06 15:09:17 -04:00
Jerome Glisse 935a729447 r600g: fix num of dwords needed for alphatest_state atom
Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-09-06 15:09:14 -04:00
Chad Versace f29a4b0157 mesa: Don't advertise GLES extensions in GL contexts
glGetStringi(GL_EXTENSIONS) failed to respect the context's API, and so
returned all internally enabled GLES extensions from a GL context.
Likewise, glGetIntegerv(GL_NUM_EXTENSIONS) also failed to repsect the
context's API.

Note: This is a candidate for the 8.0 and 9.0 branches.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Signed-off-by: Chad Versace <chad.versace@linux.intel.com>
2012-09-06 11:46:04 -07:00
José Fonseca edc0a00377 llvmpipe: Make driver name more informative.
Such as

  "llvmpipe (LLVM 3.1, 128 bits)"

or

  "llvmpipe (LLVM 3.1, 256 bits)"

when leveraging AVX 8-wide registers.

Reviewed-by: Brian Paul <brianp@vmware.com>
Reviewed-by: Roland Scheidegger <sroland@vmware.com>
2012-09-06 16:35:25 +01:00
Michel Dänzer 694617a5b4 radeonsi: Handle more L/I/A format cases.
Fixes piglit fbo-generatemipmap-formats.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-06 16:48:16 +02:00
Michel Dänzer cfebaf9dbd radeonsi: Enable whole quad mode for pixel shaders.
Fixes wrong mipmap level being sampled at some triangle edges.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-06 16:46:55 +02:00
Michel Dänzer 5edb80cee0 radeon/llvm: Add intrinsic for enabling whole quad mode in SI pixel shaders.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-06 16:46:42 +02:00
Michel Dänzer e7383b74ef radeon/llvm: SI shader vector instructions implicitly use the EXEC register.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-06 16:46:27 +02:00
Michel Dänzer ab162f80c3 radeon/llvm: Extend SI EXEC register support.
Add 32 bit lo and hi variants, and binary encodings.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-06 16:15:44 +02:00
Tom Stellard 2baaa5c7eb radeon/llvm: Remove R600InstrInfo.td from TD_FILES
Fixes build bug introduced by
cebbdd4ac2
2012-09-06 14:16:59 +00:00
Michel Dänzer d0f51fe567 radeonsi: Enable NPOT textures again.
Should be at least mostly working now (with the corresponding fixes in
libdrm_radeon).

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06 15:39:20 +02:00
Michel Dänzer cf697e875c radeonsi: Mipmaps require memory footprint to be padded to powers of two.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06 15:39:13 +02:00
Michel Dänzer b7d96ca35e radeonsi: Sampler view state simplification.
We can always use the offset and tiling mode from level 0 and restrict the
first and last mipmap level to be used in the sampler resource.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06 15:39:01 +02:00
Michel Dänzer 396af00ffe radeonsi: Untiled textures are linear aligned, not linear general.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-06 15:38:45 +02:00
Tom Stellard cebbdd4ac2 radeon/llvm: Cleanup makefile
Hopefully, this will fix all the parallel make problems people have
been having.
2012-09-06 13:30:42 +00:00
Matt Turner b6109de34f Remove useless checks for NULL before freeing
Same as earlier commit, except for "FREE"

This patch has been generated by the following Coccinelle semantic
patch:

// Remove useless checks for NULL before freeing
//
// free (NULL) is a no-op, so there is no need to avoid it

@@
expression E;
@@
+ FREE (E);
+ E = NULL;
- if (unlikely (E != NULL)) {
-   FREE(E);
(
-   E = NULL;
|
-   E = 0;
)
   ...
- }

@@
expression E;
type T;
@@
+ FREE ((T) E);
+ E = NULL;
- if (unlikely (E != NULL)) {
-   FREE((T) E);
(
-   E = NULL;
|
-   E = 0;
)
   ...
- }

@@
expression E;
@@
+ FREE (E);
- if (unlikely (E != NULL)) {
-   FREE (E);
- }

@@
expression E;
type T;
@@
+ FREE ((T) E);
- if (unlikely (E != NULL)) {
-   FREE ((T) E);
- }

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:28:50 -07:00
Matt Turner da3282b6e2 Replace another malloc/memset-0 combination with calloc
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:28:50 -07:00
Matt Turner 52789496a7 Remove useless memset after calloc
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:28:50 -07:00
Matt Turner 6bda027e01 Use calloc instead of malloc/memset-0
This patch has been generated by the following Coccinelle semantic
patch:

@@
expression E;
identifier I;
@@
- I = malloc(E);
+ I = calloc(1, E);
...
- memset(I, 0, sizeof *I);

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:28:50 -07:00
Matt Turner 5067506ea6 Remove useless checks for NULL before freeing
This patch has been generated by the following Coccinelle semantic
patch:

// Remove useless checks for NULL before freeing
//
// free (NULL) is a no-op, so there is no need to avoid it

@@
expression E;
@@
+ free (E);
+ E = NULL;
- if (unlikely (E != NULL)) {
-   free(E);
(
-   E = NULL;
|
-   E = 0;
)
   ...
- }

@@
expression E;
type T;
@@
+ free ((T) E);
+ E = NULL;
- if (unlikely (E != NULL)) {
-   free((T) E);
(
-   E = NULL;
|
-   E = 0;
)
   ...
- }

@@
expression E;
@@
+ free (E);
- if (unlikely (E != NULL)) {
-   free (E);
- }

@@
expression E;
type T;
@@
+ free ((T) E);
- if (unlikely (E != NULL)) {
-   free ((T) E);
- }

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:28:50 -07:00
Matt Turner a9e8054fff glX_proto_send.py: Don't cast the return value of malloc 2012-09-05 22:28:50 -07:00
Matt Turner 2b7a972e3f Don't cast the return value of malloc/realloc
This patch has been generated by the following Coccinelle semantic
patch:

// Don't cast the return value of malloc/realloc.
//
// Casting the return value of malloc/realloc only stands to hide
// errors.

@@
type T;
expression E1, E2;
@@
- (T)
(
_mesa_align_calloc(E1, E2)
|
_mesa_align_malloc(E1, E2)
|
calloc(E1, E2)
|
malloc(E1)
|
realloc(E1, E2)
)
2012-09-05 22:28:50 -07:00
Matt Turner 812931f602 glX_proto_send.py: Remove deprecated Xmalloc/Xfree calls
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:28:49 -07:00
Matt Turner 7c7b7b068b Remove Xcalloc/Xmalloc/Xfree calls
These calls allowed Xlib to use a custom memory allocator, but Xlib has
used the standard C library functions since at least its initial import
into git in 2003. It seems unlikely that it will grow a custom memory
allocator. The functions now just add extra overhead. Replacing them
will make future Coccinelle patches simpler.

This patch has been generated by the following Coccinelle semantic
patch:

// Remove Xcalloc/Xmalloc/Xfree calls

@@ expression E1, E2; @@
- Xcalloc (E1, E2)
+ calloc (E1, E2)

@@ expression E; @@
- Xmalloc (E)
+ malloc (E)

@@ expression E; @@
- Xfree (E)
+ free (E)

@@ expression E; @@
- XFree (E)
+ free (E)

Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:28:49 -07:00
Vinson Lee 17a574d7cd Use the correct macro _WIN32 for Windows.
The correct predefined macro for Windows is _WIN32, not WIN32 or
__WIN32__.  _WIN32 is defined for 32-bit and 64-bit version of Windows
by both MSVC and MinGW compilers.

http://sourceforge.net/p/predef/wiki/OperatingSystems
http://msdn.microsoft.com/en-us/library/b0084kay.aspx

This patch also fixes a MinGW automake build error.

Signed-off-by: Vinson Lee <vlee@freedesktop.org>
Reviewed-by: Brian Paul <brianp@vmware.com>
2012-09-05 22:14:32 -07:00
Brian Paul df5eb0c9bc mesa: remove #undef CONST in get.c
Reviewed-by: Matt Turner <mattst88@gmail.com>
2012-09-05 21:20:31 -06:00
Brian Paul 97992b05fb mesa: remove now unused CONST macro
Reviewed-by: Matt Turner <mattst88@gmail.com>
2012-09-05 21:20:27 -06:00
Brian Paul 2e23a76eb9 mesa: s/CONST/const/ in a comment
Reviewed-by: Matt Turner <mattst88@gmail.com>
2012-09-05 21:20:21 -06:00
Brian Paul 9f2a7a38e8 mesa: s/CONST/const/ in math/ files
The CONST macro hack will go away soon.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2012-09-05 21:20:03 -06:00
Tom Stellard d220e2de7f radeon/llvm: Fix operand ordering for V_CNDMASK_B32
This fixes several hundred piglit tests.
2012-09-05 13:17:49 -04:00
Tom Stellard 12d3d6f6ab radeon/llvm: Use correct float->int conversion opcode on SI.
V_CVT_I32_F32 converts floats to signed integers, but we were using
V_CVT_F32_I32 which convertes signed integers to float.
2012-09-05 13:17:17 -04:00
Tom Stellard d68e337c60 configure.ac: Don't link gallium drivers with libdricore
Reviewed-by: Matt Turner <mattst88@gmail.com>
2012-09-05 14:01:56 -04:00
Paul Berry e42f16c192 i965/blorp: Fix incorrect indentation. 2012-09-05 10:42:06 -07:00
Paul Berry 772ea84b35 mapi: Add shared-glapi-test to .gitignore 2012-09-05 10:41:42 -07:00
Brian Paul 771e7b6d88 mesa: fix per-level max texture size error checking
This is a long-standing omission in Mesa's texture image size checking.
We need to take the mipmap level into consideration when checking if the
width, height and depth are too large.

Fixes the new piglit max-texture-size-level test.
Thanks to Stéphane Marchesin for finding this problem.

Note: This is a candidate for the stable branches.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-05 08:44:26 -06:00
Kenneth Graunke 456c7355e0 i965: Don't use brw->fragment_program in the old brw_wm_pass2.c.
According to Eric, this shouldn't matter since we don't do precompiles
using the old backend.  In other words, brw->fragment_program (the
currently active program) should equal c->fp (the program currently
being compiled).

However, it's just not a good idea to access brw->fragment_program
directly in compiler code.  It's totally illegal in the new backend, so
let's just not do it here either.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reported-by: Paul Berry <stereotype441@gmail.com>
2012-09-05 06:50:10 -07:00
Tom Stellard 446d19c12a radeon/llvm: Fix lowering of SI_V_CNDLT
SREG_LIT_0 is a scalar register, so it can only be used in the
first argument of vector instructoins.
2012-09-04 14:21:10 -04:00
Tom Stellard f9fede884b radeon/llvm: Fix encoding of V_CNDMASK_B32
The CodeEmitter was not setting the VGPR bit for src0, because the
instruction definition had the VCC register in the src0 slot, instead of
the actual src0 register.  This has been fixed by moving the VCC
register to the end of the operand list.
2012-09-04 14:21:10 -04:00
Brian Paul f73ffacbf0 mesa: fix DIFFERENT_SIGNS() function
Looks like converting this to a macro, returning bool, caused us to
lose the high (31st) bit result.  Fixes piglit fbo-1d test.  Strange
that none of the other tests I ran caught this.

Fixes https://bugs.freedesktop.org/show_bug.cgi?id=54365

Tested-by: Vinson Lee <vlee@freedesktop.org>
2012-09-04 11:36:58 -06:00
Vincent Lejeune 8eaa36317a radeon/llvm: do not convert f32 operand of select_cc node
v2:-use camel coding style

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:54:37 +02:00
Vincent Lejeune a4325b3229 radeon/llvm: custom lowering for FP_TO_UINT when dst is i1 (bool)
v2:-wrap line at 80 characters

Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:54:01 +02:00
Vincent Lejeune d9e135e18c radeon/llvm: support setcc on f32
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:52:53 +02:00
Vincent Lejeune a383142436 radon/llvm: br_cc f32 now lowered without cast
Reviewed-by: Tom Stellard <thomas.stellard@amd.com>
2012-09-04 17:50:44 +02:00