Commit Graph

52785 Commits

Author SHA1 Message Date
Paul Berry 5fd67fac14 i965/blorp: Reduce alignment restrictions for stencil blits.
Previously, we aligned all stencil blit operations to multiples of the
size of a tile, since stencil buffers use W-tiling, and blorp has to
approximate this by configuring the 3D pipeline for Y-tiling and
swizzling coordinates.

However, this was unnecessarily conservative; it turns out that the
differences between W-tiling and Y-tiling are confined to 32-byte
sub-tiles within the 4k tiling pattern; the layout of these 32-byte
sub-tiles within the larger 4k tile is the same (8 sub-tiles across by
16 sub-tiles down, in column-major order).  Therefore we only need to
align stencil blit operations to multiples of the sub-tile size.

Note: although the performance improvement of this change is probably
quite small, the fact that W-tiling and Y-tiling formats only differ
within 32-byte sub-tiles will be essential in a future patch to ensure
that stencil blits work correctly between parts of the miptree other
than level/layer 0.  Making this change provides handy documentation
(and validation) of this fact.

NOTE: This is a candidate for stable release branches.

Acked-by: Eric Anholt <eric@anholt.net>
2012-09-12 14:44:13 -07:00
Paul Berry 1a75063d5f i965/blorp: don't reduce stencil alignment restrictions when multisampling.
When blitting to a stencil buffer, we need to align the rectangle we
send down the rendering pipeline, to account for the fact that the
stencil buffer uses a W-tiled layout, but we are configuring its
surface state as Y-tiled.

Previously, when the stencil buffer was multisampled, we assumed that
we could reduce the amount of alignment that was necessary, since each
pixel occupies a block of 2x2 or 4x2 samples in the stencil buffer.
That would have been correct if the coordinates we were adjusting were
measured in pixels.  However, the conversion from pixel coordinates to
coordinates within the interleaved buffer has already been done;
therefore the full alignment restriction applies.

Note: the reason this mistake wasn't previously uncovered by piglit
tests is because it is being masked by another mistake: the blorp
engine is using overly conservative alignment restrictions when doing
stencil blits.  The overly conservative alignment restrictions will be
removed in the patch that follows.  Doing this fix now will prevent
the subsequent patch from introducing regressions.

NOTE: This is a candidate for stable release branches.

Acked-by: Eric Anholt <eric@anholt.net>
2012-09-12 14:44:13 -07:00
Paul Berry b760c9913d intel: Add map_stencil_as_y_tiled to intel_region_get_aligned_offset.
This patch modifies intel_region_get_aligned_offset() to make the
appropriate calculation when the blorp engine sets up a W-tiled
stencil buffer using a Y-tiled SURFACE_STATE.

NOTE: This is a candidate for stable release branches.

Acked-by: Eric Anholt <eric@anholt.net>
2012-09-12 14:44:13 -07:00
Paul Berry 50dec7fc2d intel: Add map_stencil_as_y_tiled to intel_region_get_tile_masks.
When the blorp engine is performing a blit from one stencil buffer to
another, it sets up the surface state for these buffers as Y-tiled, so
it needs to be able to force intel_region_get_tile_masks() to return
the appropriate masks for a Y-tiled region.

NOTE: This is a candidate for stable release branches.

Acked-by: Eric Anholt <eric@anholt.net>
2012-09-12 14:44:13 -07:00
Paul Berry f04f219906 i965/blorp: Account for offsets when emitting SURFACE_STATE.
Fixes piglit tests "framebuffer-blit-levels {read,draw} depth".

NOTE: This is a candidate for stable release branches.

Reviewed-by: Eric Anholt <eric@anholt.net>
2012-09-12 14:44:12 -07:00
Paul Berry 3123f06215 i965/blorp: Thread level and layer through brw_blorp_blit_miptrees().
Previously, when performing a blit using the blorp engine, we failed
to account for the level and layer of the source and destination.  As
a result, all blits would occur between miplevel 0 and layer 0 of the
corresponding textures, regardless of which level/layer was bound to
the framebuffer.

This patch passes the correct level and layer through
brw_blorp_miptrees() into the brw_blorp_blit_params data structure.

Further patches in the series will adapt
gen{6,7}_blorp_emit_surface_state to make use of these parameters.

NOTE: This is a candidate for stable release branches.

Reviewed-by: Eric Anholt <eric@anholt.net>
2012-09-12 14:44:12 -07:00
Paul Berry bc6cafa045 i965/blorp: Don't create a dummy renderbuffer just to fetch image offsets.
This is unnecessary--the image offsets can be read directly out of the
miptree using intel_miptree_get_image_offset.
2012-09-12 14:44:12 -07:00
Paul Berry c130ce7b2b i965/blorp: store x and y offsets in brw_blorp_mip_info.
Currently, gen{6,7}_blorp_emit_surface_state assumes that the src and
dst surfaces are mapped to miplevel 0 and layer 0 (thus no surface
offset is required).  This is a bug, since the user might try to blit
to and from levels/layers other than 0.

To fix this bug, it will not be sufficient to have
gen6_{6,7}_blorp_emit_surface_state look up the surface offset at the
time they set up the surface state, since these offsets will need to
be tweaked when blitting stencil buffers (due to the fact that stencil
buffer blits have to swizzle between W and Y tiling formats).

So, to pave the way for the bug fix, this patch causes the x and y
offsets to be computed during blit setup and stored in
brw_blorp_mip_info.

As a result of this change, brw_blorp_mip_info doesn't need to store
the level and layer anymore.

For consistency, this patch makes a similar change to the handling of
depth buffers when doing HiZ operations.

NOTE: This is a candidate for stable release branches.

Reviewed-by: Eric Anholt <eric@anholt.net>
2012-09-12 14:44:12 -07:00
Paul Berry 09b0fa8499 i965/blorp: store surface width/height in brw_blorp_mip_info.
Previously, gen{6,7}_blorp_emit_surface_state would look up the width
and height of the surface at the time they set up the surface state,
and then tweak it if necessary (it's necessary when a W-tiled surface
is being mapped as Y-tiled).  With this patch, we look up the width
and height when setting up the blit, and store them in
brw_blorp_mip_info.  This allows us to do the necessary tweak in the
brw_blorp_blit_params constructor (where it makes more sense).  It
also reduces the need to keep track of level and layer in
brw_blorp_mip_info, so that a future patch can eliminate them
entirely.

For consistency, this patch makes a similar change to the handling of
depth buffers when doing HiZ operations.

NOTE: This is a candidate for stable release branches.

Reviewed-by: Eric Anholt <eric@anholt.net>
2012-09-12 14:44:12 -07:00
Paul Berry e14b1288ef i965/blorp: Change gl_renderbuffer* params to intel_renderbuffer*.
This makes it more convenient for blorp functions to get access to
Intel-specific data inside the renderbuffer objects.

NOTE: This is a candidate for stable release branches.

Reviewed-by: Eric Anholt <eric@anholt.net>
2012-09-12 14:44:12 -07:00
Paul Berry 32c7b2769c i965/blorp: Clarify why width/height must be adjusted for Gen6 IMS surfaces.
Also add a clarifying comment for why the width/height doesn't need
adjustment for Gen7.

NOTE: This is a candidate for stable release branches.

Reviewed-by: Eric Anholt <eric@anholt.net>
2012-09-12 14:44:12 -07:00
Paul Berry bde833c9d0 i965/gen6+: Adjust stencil buffer size after computing miptree layout.
Since Gen6+ stencil buffers use W-tiling (a tiling arrangement which
drm and the kernel are not aware of) we need to round up the width and
height of a stencil buffer to multiples of the W-tile size (64x64)
before allocating a stencil buffer.  Previously, we rounded up the
size of the base miplevel, and then computed the miptree layout based
on the rounded up size.  This was incorrect, because it meant that the
total size of the miptree would not be properly W-tile aligned, and
therefore we would not always allocate enough pages.

(Note: even though the GL API doesn't allow creation of mipmapped
stencil textures, it does allow mipmapping of a combined depth/stencil
texture, and on Gen6+, a combined depth/stencil texture is internally
implemented as a pair of separate depth and stencil buffers.)

For example, on Sandy Bridge, when allocating a mipmapped stencil
texture of size 128x128, we would first round up to the nearest
multiple of 64x64 (causing no change to the size), and then compute
the miptree layout (whose size worked out to 128x196).  Then we would
request an allocation of 128*196 bytes (6.125 pages), causing 7 pages
to be allocated to the texture.  However, the texture needs 8 pages,
since each W-tile occupies a page, and it takes 2 W-tiles to cover a
width of 128 and 4 W-tiles to cover a height of 196.

This patch changes the order of operations so that the miptree layout
is computed first and then the total size of the miptree is rounded up
to be W-tile aligned.

NOTE: This is a candidate for stable release branches.

Reviewed-by: Eric Anholt <eric@anholt.net>
2012-09-12 14:44:12 -07:00
Matt Turner af6aeae4e1 build: Don't list glproto and dri2proto in pkg-config file
No files provided by glproto or dri2proto are needed for building
something with Mesa.

Bugzilla: https://bugs.gentoo.org/show_bug.cgi?id=342393
Reviewed-by: Dan Nicholson <dbn.lists@gmail.com>
2012-09-12 11:26:28 -07:00
Michel Dänzer 7443e4e697 radeonsi: Properly handle NULL sampler views.
Fixes piglit shaders/glsl-fs-uniform-sampler-array and many other similar
tests.

In fact, I just completed a piglit quick-driver.tests run without any GPU
lockups or even VM protection faults. Yay!

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-12 15:53:51 +02:00
Michel Dänzer d67d8e2471 radeonsi: Fix calculation of number of records in buffer resource.
The value was too small by 1 in some cases (non-first of several vertex
elements interleaved in a single buffer).

Fixes intermittent incorrect geometry in many apps, e.g. piglit
spec/EXT_texture_snorm/fbo-generatemipmap-formats.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
2012-09-12 13:23:09 +02:00
Imre Deak 9f30cbe9ee mesa: glGet: fix API check for EGL_image_external enums
These enums are valid only in ES1 and ES2. So far they were marked valid
incorrectly, depending on the previous API mask in the enum list.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2012-09-11 17:38:21 -06:00
Imre Deak ae310e37fb mesa: glGet: fix indentation of print_table_stats
No functional change.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2012-09-11 17:38:21 -06:00
Imre Deak 97a693d1fa mesa: glGet: fix indentation of find_value
No functional change.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2012-09-11 17:38:21 -06:00
Imre Deak 746e82fff4 mesa: glGet: fix indentation of _mesa_init_get_hash
No functional change.

Signed-off-by: Imre Deak <imre.deak@intel.com>
Signed-off-by: Brian Paul <brianp@vmware.com>
2012-09-11 17:38:21 -06:00
Brian Paul 35c75f6777 mesa: fix proxy texture error handling in glTexStorage()
This is basically a follow-on to 1f5b1f9846.
Basically, generate GL errors for ordinary invalid parameters for proxy
targets the same as for non-proxy targets.  Only texture size and OOM
errors should be handled specially for proxies.

Note: This is a candidate for the stable branches.
2012-09-11 17:38:21 -06:00
Brian Paul d17440dcaa mesa: make _mesa_get_proxy_target() non-static
Needed for the next patch.

Note: This is a candidate for the stable branches.
2012-09-11 17:38:21 -06:00
Brian Paul 2e4fc54977 mesa: do internal format error checking for glTexStorage()
Turns out we weren't doing any format checking before.  Now check
the internal format and, in particular, make sure that unsized internal
formats aren't accepted.

Note: This is a candidate for the stable branches.
2012-09-11 17:38:21 -06:00
Paul Berry 5d5f0f3491 mesa/msaa: Allow X and Y flips in multisampled blits.
From the GL 4.3 spec, section 18.3.1 "Blitting Pixel Rectangles":

    If SAMPLE_BUFFERS for either the read framebuffer or draw
    framebuffer is greater than zero, no copy is performed and an
    INVALID_OPERATION error is generated if the dimensions of the
    source and destination rectangles provided to BlitFramebuffer are
    not identical, or if the formats of the read and draw framebuffers
    are not identical.

It is not clear from the spec whether "dimensions" should mean both
sign and magnitude, or just magnitude.

Previously, Mesa interpreted "dimensions" as meaning both sign and
magnitude, so any multisampled blit that attempted to flip the image
in the X and/or Y direction would fail.

However, Y flips are likely to be commonplace in OpenGL applications
that have been ported from DirectX applications, as a result of the
fact that DirectX and OpenGL differ in their orientation of the Y
axis.  Furthermore, at least one commercial driver (nVidia) permits Y
filps, and L4D2 relies on them being permitted.  So it seems prudent
for Mesa to permit them.

This patch changes Mesa to allow both X and Y flips, since there is no
language in the spec to indicate that X and Y flips should be treated
differently.

NOTE: This is a candidate for stable release branches.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2012-09-11 15:50:55 -07:00
Tom Stellard 843ac06ad2 radeon/llvm: Fix operand order of V_CNDMASK in custom inserter
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:48 -04:00
Tom Stellard d399ce7615 radeon/llvm: Assert if we try to encode an unknown register
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:48 -04:00
Tom Stellard 0df2753ad2 radeon/llvm: Add register encoding for VCC
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard 056d9c6ef1 radeon/llvm: Ignore special registers when calculating reg count
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard 0fb1e68a0b radeonsi: Handle position input parameter for pixel shaders v2
v2:
  - Don't increment ninterp or set any of the have_* flags for
    TGSI_SEMANTIC_POSITION

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard 0410e9e8c7 radeon/llvm: Coding style fixes
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard d3e58f75d2 radeonsi: Move interpolation mode check into the compiler
The compiler needs to know which interpolation modes are enabled, so
it knows which values will be preloaded into the VGPRs.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard 5fff032dd5 radeonsi: Add missing interpolation mode to check for enabled modes
At least one interpolation mode must be enable, but the code that checks
this was not checking for perspective center.

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard cc571a367e radeonsi: Pass shader type to the compiler
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Tom Stellard dfd3d61abf radeon/llvm: Add SHADER_TYPE instruction
This allows the program to specify the type of shader being compiled
(e.g. PXEL, VERTEX, etc.)

Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-11 14:53:47 -04:00
Jerome Glisse 841c1b5f54 r600g: avoid GPU doing constant preload from random address
Previous command stream might have set any of the constant buffer
and the previous address might no longer be valid thus GPU might
preload constant from random invalid address and possibly triggering
lockup.

Signed-off-by: Jerome Glisse <jglisse@redhat.com>
2012-09-11 12:57:54 -04:00
Michel Dänzer 9ccaa24f84 radeonsi: Texture border colour fixes.
* Handle arbitrary border colours.
* Use correct packing format for detecting special border colours.

Fixes piglit tex-border-1 and probably many other tests using border colours.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-11 11:06:56 +02:00
Michel Dänzer 03dfa30596 radeonsi: Handle NULL sampler states.
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
2012-09-11 11:06:16 +02:00
Kenneth Graunke 23cd6c43da i965: Remove incorrect comment above opt_algebraic.
The comment was cut-and-pasted from propagate_constants(), and had no
relation at all to opt_algebraic().
2012-09-10 22:58:25 -07:00
Kenneth Graunke 354f2cb5c7 glsl: Generate compile errors for explicit blend indices < 0 or > 1.
According to the GLSL 4.30 specification, this is a compile time error.
Earlier specifications don't specify a behavior, but since 0 and 1 are
the only valid indices for dual source blending, it makes sense to
generate the error.

Fixes (the fixed version of) piglit's layout-12.frag.

NOTE: This is a candidate for the 9.0 branch.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Paul Berry <stereotype441@gmail.com>
2012-09-10 20:56:11 -07:00
Marek Olšák 87389d4e5c r600g: remove unused function 2012-09-11 00:02:58 +02:00
Marek Olšák 830b6f3273 r600g: fix printf warning 2012-09-11 00:02:58 +02:00
Andreas Boll e81ee67b51 mesa: bump version to 9.1 (devel)
Now that branch 9.0 is created, bump the minor version in
master.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-09-09 03:00:17 -07:00
Johannes Obermayr 10a96f4a4d Set OSMESA_VERSION=8.
VERSION_NUMBER is not required anymore. So it will be removed.

Reviewed-by: Adam Jackson <ajax@redhat.com>
2012-09-07 14:44:48 -04:00
Christoph Bumiller 3433471e8b nvc0/ir: add initial code to support GK110 ISA encoding 2012-09-07 19:03:40 +02:00
Michel Dänzer 8a497e5955 radeonsi: Float format fixups.
Fixes piglit spec/ARB_texture_float/fbo-generatemipmap-formats.

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-07 18:23:08 +02:00
Michel Dänzer 15c009af28 radeonsi: Handle more SNORM formats.
Fixes piglit spec/EXT_texture_snorm/fbo-generatemipmap-formats (except for
what seems like a random fluke).

Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
2012-09-07 18:23:08 +02:00
Eric Anholt 39aca5076f i965: Fix virtual_grf_interferes() between calculate_live_intervals() and DCE.
This fixes the blue zombies bug in l4d2.

NOTE: This is a candidate for the 9.0 branch.
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-09-07 08:29:49 -07:00
Eric Anholt 7b3fe776e2 i965: Make the param pointer arrays for the VS dynamically sized.
Saves 96MB of wasted memory in the l4d2 demo.

v2: Rebase on compare func change, change brace style.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-09-07 08:29:49 -07:00
Eric Anholt f144b78dfb i965: Make the param pointer arrays for the WM dynamically sized.
Saves 26.5MB of wasted memory allocation in the l4d2 demo.

v2: Rebase on compare func change, fix comments.

Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> (v1)
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-09-07 08:29:48 -07:00
Eric Anholt 99596cba78 i965: Add functions for comparing two brw_wm/vs_prog_data structs.
Currently, this just avoids comparing all unused parts of param[] and
pull_param[], but it's a step toward getting rid of those giant statically
sized arrays.

v2: Actually use the new function instead of just looking at its
    address.  This required changing the args to const pointers.
    (review by Kenneth)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2012-09-07 08:29:48 -07:00
Eric Anholt 5bb94f2bc4 glsl: Count builtin uniforms against uniform component limits.
We don't fully process the builtin uniforms, but at least
num_uniform_components reflects reality now.

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
2012-09-07 08:29:48 -07:00