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radeon/llvm: Fix operand ordering for V_CNDMASK_B32 

This fixes several hundred piglit tests.
This commit is contained in:
Tom Stellard 2012-09-05 11:30:16 -04:00
parent 12d3d6f6ab
commit d220e2de7f
1 changed files with 3 additions and 3 deletions
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6
src/gallium/drivers/radeon/SIInstructions.td
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@ -674,15 +674,15 @@ def S_WAITCNT : SOPP <0x0000000c, (ins i32imm:$simm16), "S_WAITCNT $simm16",
def V_CNDMASK_B32 : VOP2 <0x00000000, (outs VReg_32:$dst),
(ins AllReg_32:$src0, VReg_32:$src1, VCCReg:$vcc), "V_CNDMASK_B32",
[(set (i32 VReg_32:$dst),
(select VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1))] > {
(select VCCReg:$vcc, VReg_32:$src1, AllReg_32:$src0))] > {
let DisableEncoding = "$vcc";
}
//f32 pattern for V_CNDMASK_B32
def : Pat <
(f32 (select VCCReg:$vcc, AllReg_32:$src0, VReg_32:$src1)),
(V_CNDMASK_B32 AllReg_32:$src0, VReg_32:$src1, VCCReg:$vcc)
(f32 (select VCCReg:$vcc, VReg_32:$src0, AllReg_32:$src1)),
(V_CNDMASK_B32 AllReg_32:$src1, VReg_32:$src0, VCCReg:$vcc)
>;
defm V_READLANE_B32 : VOP2_32 <0x00000001, "V_READLANE_B32", []>;