Commit Graph

88040 Commits

Author SHA1 Message Date
Samuel Iglesias Gonsálvez 77077986eb i965: enable ARB_shader_precision to HSW+
v2: update docs (Jordan)

Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-01-12 12:56:57 +01:00
Samuel Iglesias Gonsálvez 1d1ddbaa56 i965: unify the code to enable of ARB_gpu_shader_fp64 and ARB_vertex_attrib_64bit for HSW+
Signed-off-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-01-12 12:56:56 +01:00
Alejandro Piñeiro 485955be9c i965: Enable ARB_vertex_attrib_64bit for Haswell
v2: update docs (Jordan)

Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-01-12 12:56:56 +01:00
Juan A. Suarez Romero 6bb4255f8e i965: check for dual slot attributes on any gen
Those not supporting 64 bit input vertex attributes will have the
dual_slot value as false.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-01-12 12:56:56 +01:00
Juan A. Suarez Romero f51a5b51ab i965/vec4: emit correctly load_inputs for 64bit data
For dvec3 and dvec4 types, a single GRF do not have enough space to
allocate two inputs from two different vertices (SIMD4x2).

So the GRF only contains first two components for the two vertices, and
the next GRF has the remaining components.

We want to put all the components for the same vertex in the same
register. Thus, we do a shuffle to reorder the data.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-01-12 12:56:56 +01:00
Alejandro Piñeiro 58fdb85f0f i965/vec4: take into account doubles when creating attribute mapping
Doubles needs more that one slot per attribute. So when filling the
attribute_map we check if it is a double in order to allocate one
extra register.

Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-01-12 12:56:56 +01:00
Alejandro Piñeiro 57bab6708f i965/vec4/nir: vec4 also needs to remap vs attributes
Doubles need extra space, so we would need to do a remapping for vec4
too in order to take that into account. We reuse the already
existing remap_vs_attrs, but passing is_scalar, so they could
remap accordingly.

v2: code-format remap_vs_attrs_params initialization (Matt)

Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-01-12 12:56:56 +01:00
Alejandro Piñeiro f8310189f4 i965/vec4: use attribute slots for first non payload GRF
As part of the payload setup, setup_attributes is called with the first
GRF that can be used for the attributes (first ones are used for
uniforms for example) and returns the first GRF that is not part of the
payload. Before this patch, it adds directly the number of attributes.
But as with 64-bit attributes can consume more than one slot, that is
not valid anymore. This patch change the addition to use the number of
slots consumed.

gen >= 8 would not be affected, as they use the scalar mode. For that
case, the vs configuration is done at fs_visitor::assign_vs_urb_setup.

v2: add explanation in commit log (Jordan)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-01-12 12:56:35 +01:00
Alejandro Piñeiro 329cbe363d i965: downsize *64*PASSTHRU formats to equivalent *32*FLOAT formats on gen < 8
gen < 8 doesn't support *64*PASSTHRU formats when emitting
vertices. So in order to provide the equivalent functionality, we need
to downsize the format to equivalent *32*FLOAT, and in some cases
(R64G64B64 and R64G64B64A64) submit two 3DSTATE_VERTEX_ELEMENTS for
each vertex element.

Signed-off-by: Alejandro Piñeiro <apinheiro@igalia.com>
Signed-off-by: Juan A. Suarez Romero <jasuarez@igalia.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-01-12 12:56:12 +01:00
Alejandro Piñeiro 717f99b34a i965: return PASSTHRU surface types also on gen7
Although gen7 doesn't include surface types as a valid conversion format,
we return it, as it reflects what we want to achieve, even if we need
to workaround it on gen < 8.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-01-12 12:56:12 +01:00
Alejandro Piñeiro f354cd5c69 main/buffers: take into account FRONT_AND_BACK on ReadBuffer
From OpenGL 3.1 spec, section 4.3.1 "Reading Pixels", page 190 (203 PDF)

  "When READ FRAMEBUFFER BINDING is zero, i.e. the default
   framebuffer, src must be one of the values listed in table 4.4,
   including NONE . FRONT_AND_BACK , FRONT , and LEFT refer to the
   front left buffer."

There is an equivalent text on OpenGL 4.5 spec, section 18.2.1
"Selecting Buffers for Reading", page 502 (524 PDF), so the behaviour
is still the same.

Part of the fix for:
GL45-CTS.direct_state_access.framebuffers_draw_read_buffers_errors

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-01-12 08:21:03 -02:00
Alejandro Piñeiro d54bc7e01f main/buffers: update error handling on DrawBuffers for 4.5
Before 4.5, GL_BACK was not allowed as a value of bufs. Since 4.5 it
is allowed under some circumstances:

From the OpenGL 4.5 specification, Section 17.4.1 "Selecting Buffers
for Writing", page 493 (page 515 of the PDF):
 "An INVALID_ENUM error is generated if any value in bufs is FRONT,
  LEFT, RIGHT, or FRONT_AND_BACK . This restriction applies to both
  the de- fault framebuffer and framebuffer objects, and exists
  because these constants may themselves refer to multiple buffers, as
  shown in table 17.4."

And on page 492 (page 514 of the PDF):
 "If the default framebuffer is affected, then each of the constants
  must be one of the values listed in table 17.6 or the special value
  BACK . When BACK is used, n must be 1 and color values are written
  into the left buffer for single-buffered contexts, or into the back
  left buffer for double-buffered contexts."

This patch keeps the same behaviour if OpenGL version is < 4. We
assume that for 4.x this is the intended behaviour, so a fix, but for
3.x the intended behaviour is the already in place.

Part of the fix for:
GL45-CTS.direct_state_access.framebuffers_draw_read_buffers_errors

v2: remove forgot printf
v3: remove spaces before commas on spec quote, split line too
    long (Anuj)

Reviewed-by: Anuj Phogat <anuj.phogat@gmail.com>
2017-01-12 08:21:03 -02:00
Nicolai Hähnle e33910b0d9 radeonsi: num_records is in units of stride for swizzled buffers even on VI
The old setting didn't hurt, but this is cleaner.

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-01-12 11:02:56 +01:00
Juan A. Suarez Romero 883ca597df docs: document INTEL_PRECISE_TRIG envvar
v2: use more generic description (Jordan)

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2017-01-12 09:58:23 +00:00
Iago Toral Quiroga 5bcafc933c spirv: fix typo in warning message
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2017-01-12 08:18:00 +01:00
Rafael Antognolli ea7e4b1e51 i965: Enable predicate support on gen >= 8.
Predication needs cmd parser only on gen7. For newer platforms, it
should be available without it.

v2 (Ken): rebase on recent changes.

Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com>
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2017-01-11 21:44:59 -08:00
Timothy Arceri 0252ba26c5 util: fix list_is_singular()
Currently its dependant on the user calling and checking the result
of list_empty() before using the result of list_is_singular().

Cc: "13.0" <mesa-stable@lists.freedesktop.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 13:58:32 +11:00
Nanley Chery 5857858aa6 anv/image: Disable HiZ for depth buffer arrays
We currently don't perform clears or resolves on multiple array layers
with HiZ.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-11 17:35:59 -08:00
Nanley Chery 9f1d3a0c97 anv/cmd_buffer: Fix programmed HiZ qpitch
Match the comment above the field by using units of pixels and not HiZ
blocks.

Cc: mesa-stable@lists.freedesktop.org
Suggested-by: Jason Ekstrand <jason@jlekstrand.net>
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-11 17:35:59 -08:00
Nanley Chery 61992e0afe anv/cmd_buffer: Fix arrayed depth/stencil attachments
Enable multiple layers of the depth/stencil buffers to be accessible.

Fixes the crucible test, func.depthstencil.arrayed_clear.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Nanley Chery <nanley.g.chery@intel.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-11 17:35:59 -08:00
Pierre Moreau 4e0d171d7e clover: Check for executables before enqueueing a kernel
Without this check, the kernel::bind() method would fail with a
std::out_of_range exception, letting an exception escape from the
library into the client, rather than returning the corresponding error
code CL_INVALID_PROGRAM_EXECUTABLE.

Signed-off-by: Pierre Moreau <pierre.morrow@free.fr>
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
2017-01-11 16:50:56 -08:00
Kenneth Graunke c17b2f5724 spirv: Shut up unhandled enumeration value warnings.
We don't want to do anything for the other cases.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
2017-01-11 15:16:27 -08:00
Timothy Arceri de8b03f5fb nir: don't turn ieq/ine into inot if used by an if
Otherwise we will end up with an extra instruction to compare the
result of the inot.

On BDW:

total instructions in shared programs: 13060620 -> 13060481 (-0.00%)
instructions in affected programs: 103379 -> 103240 (-0.13%)
helped: 127
HURT: 0

total cycles in shared programs: 256590950 -> 256587408 (-0.00%)
cycles in affected programs: 11324730 -> 11321188 (-0.03%)
helped: 114
HURT: 21

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 09:47:29 +11:00
Timothy Arceri 7acc865226 nir: add late opt to turn inot/b2f combos back to bcsel
We turn these from bcsel into inot/b2f combos in order for other
optimisation passes to get further. Once we have finished turn
the ones that remain and are used in more than a single expression
back into a bcsel.

On BDW:

total instructions in shared programs: 13060965 -> 13060297 (-0.01%)
instructions in affected programs: 835701 -> 835033 (-0.08%)
helped: 670
HURT: 2

total cycles in shared programs: 256599536 -> 256598006 (-0.00%)
cycles in affected programs: 114655488 -> 114653958 (-0.00%)
helped: 419
HURT: 240

LOST:   0
GAINED: 1

The 2 HURT is because inserting bcsel creates the only use of
const 1.0 in two shaders from tri-of-friendship-and-madness.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 09:47:29 +11:00
Timothy Arceri 8f37fc7066 nir: add imprecise flrp optimisation
On BDW:

total instructions in shared programs: 13061890 -> 13061877 (-0.00%)
instructions in affected programs: 2441 -> 2428 (-0.53%)
helped: 13
HURT: 0

total cycles in shared programs: 256612254 -> 256611784 (-0.00%)
cycles in affected programs: 16418 -> 15948 (-2.86%)
helped: 10
HURT: 2

V2: don't use ffma directly

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 09:47:29 +11:00
Kenneth Graunke b4c44ff08c i965: Use the nir_move_comparisons pass.
While the below stats are encouraging this pass will also become
very usefull for avoiding regression once
brw_do_channel_expressions() and brw_do_vector_splitting() are
disabled.

On Broadwell:

total instructions in shared programs: 13078787 -> 13060898 (-0.14%)
instructions in affected programs: 1809827 -> 1791938 (-0.99%)
helped: 4527
HURT: 157

total cycles in shared programs: 256562762 -> 256590424 (0.01%)
cycles in affected programs: 159749392 -> 159777054 (0.02%)
helped: 5583
HURT: 2289

total spills in shared programs: 14929 -> 14923 (-0.04%)
spills in affected programs: 62 -> 56 (-9.68%)
helped: 1
HURT: 0

total fills in shared programs: 20144 -> 20141 (-0.01%)
fills in affected programs: 253 -> 250 (-1.19%)
helped: 1
HURT: 3

LOST:   0
GAINED: 2

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 09:47:29 +11:00
Kenneth Graunke b5e682a1ef i965: Move nir_lower_locals_to_regs a bit later.
I'm going to add a boolean scheduling pass that I want run late, but
after copy propagation and dead code elimination.  Yet, I don't want
to have to think about registers.  So, move the register conversion
a little later.

No impact on shader-db.  Suggested by Jason Ekstrand.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2017-01-12 09:47:29 +11:00
Kenneth Graunke fd957b1751 nir: Introduce a nir_opt_move_comparisons() pass.
This tries to move comparisons (a common source of boolean values)
closer to their first use.  For GPUs which use condition codes,
this can eliminate a lot of temporary booleans and comparisons
which reload the condition code register based on a boolean.

V2: (Timothy Arceri)
 - fix move comparision for phis so we dont end up with:

    vec1 32 ssa_227 = phi block_34: ssa_1, block_38: ssa_240
    vec1 32 ssa_235 = feq ssa_227, ssa_1
    vec1 32 ssa_230 = phi block_34: ssa_221, block_38: ssa_235

 - add nir_op_i2b/nir_op_f2b to the list of comparisons.

V3: (Timothy Arceri)
 - tidy up suggested by Jason.
 - add inot/fnot to move comparison list

V4: (Jason Ekstrand)
 - clean up move_comparison_source
 - get rid of the tuple
 - rework phi handling

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com> [v1]
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 09:47:29 +11:00
Timothy Arceri e8328e55e7 nir/algebraic: add support for conditional helper functions to expressions
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-12 09:47:29 +11:00
Jason Ekstrand a7e399de59 anv/TODO: Check off a bunch of stuff 2017-01-11 10:28:18 -08:00
Jason Ekstrand c472568b4e nir/search: Only allow matching SSA values
This is more correct and should also be a tiny bit faster since we're
just comparing pointers instead of calling nir_src_equal.

Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
Cc: "13.0" <mesa-stable@lists.freedesktop.org>
2017-01-11 10:28:18 -08:00
Derek Foreman 534ea2b5ba egl/dri2: add image_loader_extension back into loader extensions for wayland
before commit f871946594
image_loader_extension was always present in dri2_dpy->extensions,
after that commit it is only present for render nodes.

Its removal broke partial render based on buffer age on (at least)
raspberry pi.

Fixes: f871946594 "egl/dri2: rework dri2_egl_display::extensions storage"
Signed-off-by: Derek Foreman <derekf@osg.samsung.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-11 15:58:14 +00:00
Li Qiang 6205c53303 gallium/tgsi: fix overflow in parse property
In parse_identifier, it doesn't stop copying '*pcur'
untill encounter the NULL. As the 'ret' has a
fixed-size buffer, if the '*pcur' has a long string,
there will be a buffer overflow. This patch avoid this.

Signed-off-by: Li Qiang <liq3ea@gmail.com>
Signed-off-by: Marek Olšák <marek.olsak@amd.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
2017-01-11 12:40:38 +01:00
Mauro Rossi 2c0d849e2d st/dri: remove trailing whitespace
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-11 10:16:19 +02:00
Mauro Rossi eca79e84b9 android: st/mesa: fix building error in libmesa_st_mesa
Fixes building error due to dependency on nir generated headers

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-01-11 10:16:19 +02:00
Dave Airlie e9d3cbca31 radv: fix multi-viewport emission
This set context req seq was in the wrong place.

Signed-off-by: Dave Airlie <airlied@redhat.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-01-11 09:08:51 +01:00
Tapani Pälli f97f938650 nir: change asserts to unreachable in nir_type_conversion_op
this is to avoid following compilation error on Android:

   error: control may reach end of non-void function [-Werror,-Wreturn-type]

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2017-01-11 10:08:13 +02:00
Iago Toral Quiroga a9f497c678 spirv: gl_PrimitiveID in the fragment shader is handled as an input
Geometry and Tessellation stages do handle this as a system value instead.

Fixes:
dEQP-VK.geometry.basic.primitive_id

Reviewed-by: Dave Airlie <ailried@redhat.com>
2017-01-11 08:59:28 +01:00
Rob Clark 99e9dca149 freedreno: add "nogrow" debug param
Sometimes it is useful to disable the "growable" cmdstream buffers for
debugging.  (See 419a154d in libdrm)

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-10 19:40:00 -05:00
Rob Clark a43f3b895c freedreno/a5xx: remove hack for glamor
Now that issues glamor was hitting w/ glsl>=130 (aka missing INSTANCED
bit in vertex attribute state) is fixed, remove hack.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-10 19:40:00 -05:00
Rob Clark 3c71853c9a freedreno/a5xx: fixed instanced
Add missing bit, now that we know where it is.

Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-10 19:40:00 -05:00
Rob Clark b48fde1576 freedreno/a5xx: use the non-_ZERO_BASE for vertexid
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-10 19:40:00 -05:00
Rob Clark 730c3047f0 freedreno/a5xx: add texture MIPLVLS
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-10 19:40:00 -05:00
Rob Clark 1a5d0818df freedreno/a5xx: fix fragcoord related hangs
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-10 19:40:00 -05:00
Rob Clark ff81c3c9fd freedreno: update generated headers
Signed-off-by: Rob Clark <robdclark@gmail.com>
2017-01-10 19:40:00 -05:00
Kenneth Graunke 23a36c2811 anv: Enable tessellation shaders.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-10 13:27:31 -08:00
Kenneth Graunke ebd88b5aa3 anv: Initialize physical device limits for tessellation
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-10 13:27:31 -08:00
Kenneth Graunke dcca706b4e anv: Clamp depth buffer dimensions to be at least 1.
When there are no framebuffer attachments, fb->width and fb->height will
be 0.  Subtracting 1 results in 4294967295 which is too large for the
field, causing genxml assertions when trying to create the packet.

In this case, we can just program it to 1.

Caught by dEQP-VK.tessellation.tesscoord.triangles_equal_spacing.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-10 13:27:31 -08:00
Kenneth Graunke e50d4807a3 anv: Compile TCS/TES shaders.
v2: Merge more TCS/TES info.
v3: Fix caching keys.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-10 13:27:31 -08:00
Kenneth Graunke de05ecba9f anv: Emit 3DSTATE_HS/TE/DS packets.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-01-10 13:27:31 -08:00