KonstantinSeurer
/
mesa
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

i965/vec4: emit correctly load_inputs for 64bit data 

For dvec3 and dvec4 types, a single GRF do not have enough space to
allocate two inputs from two different vertices (SIMD4x2).

So the GRF only contains first two components for the two vertices, and
the next GRF has the remaining components.

We want to put all the components for the same vertex in the same
register. Thus, we do a shuffle to reorder the data.

Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
This commit is contained in:
Juan A. Suarez Romero 2016-07-06 12:40:49 +02:00
parent 58fdb85f0f
commit f51a5b51ab
1 changed files with 16 additions and 7 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

23
src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
View File

@ -417,15 +417,24 @@ vec4_visitor::nir_emit_intrinsic(nir_intrinsic_instr *instr)
/* We set EmitNoIndirectInput for VS */
assert(const_offset);
src = src_reg(ATTR, instr->const_index[0] + const_offset->u32[0],
glsl_type::uvec4_type);
/* Swizzle source based on component layout qualifier */
src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr));
dest = get_nir_dest(instr->dest, src.type);
dest = get_nir_dest(instr->dest);
dest.writemask = brw_writemask_for_size(instr->num_components);
emit(MOV(dest, src));
src = src_reg(ATTR, instr->const_index[0] + const_offset->u32[0],
glsl_type::uvec4_type);
src = retype(src, dest.type);
bool is_64bit = nir_dest_bit_size(instr->dest) == 64;
if (is_64bit) {
dst_reg tmp = dst_reg(this, glsl_type::dvec4_type);
src.swizzle = BRW_SWIZZLE_XYZW;
shuffle_64bit_data(tmp, src, false);
emit(MOV(dest, src_reg(tmp)));
} else {
/* Swizzle source based on component layout qualifier */
src.swizzle = BRW_SWZ_COMP_INPUT(nir_intrinsic_component(instr));
emit(MOV(dest, src));
}
break;
}