Commit Graph

95663 Commits

Author SHA1 Message Date
Tapani Pälli 15b61dec94 anv: fix build errors on android
error: incompatible pointer to integer conversion initializing 'VkFence'
   (aka 'unsigned long long') with an expression of type 'void *' [-Werror,-Wint-conversion]

Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-31 18:05:50 +03:00
Christian König 214b565bc2 winsys/amdgpu: set AMDGPU_GEM_CREATE_VM_ALWAYS_VALID if possible v2
When the kernel supports it set the local flag and
stop adding those BOs to the BO list.

Can probably be optimized much more.

v2: rename new flag to AMDGPU_GEM_CREATE_VM_ALWAYS_VALID

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-31 14:55:38 +02:00
Marek Olšák 8b3a257851 radeonsi: set a per-buffer flag that disables inter-process sharing (v4)
For lower overhead in the CS ioctl.
Winsys allocators are not used with interprocess-sharable resources.

v2: It shouldn't crash anymore, but the kernel will reject the new flag.
v3 (christian): Rename the flag, avoid sending those buffers in the BO list.
v4 (christian): Remove setting the kernel flag for now

Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-31 14:55:21 +02:00
Kenneth Graunke 5ae2de81c8 i965: Use BLORP for buffer object stall avoidance blits instead of BLT.
Improves performance of GFXBench4 tests at 1024x768 on a Kabylake GT2:
- Manhattan 3.1 by 1.32134% +/- 0.322734% (n=8).
- Car Chase by 1.25607% +/- 0.291262% (n=5).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-30 16:59:24 -07:00
Kenneth Graunke 3efedf98e8 i965: Always flush caches after blitting to a GL buffer object.
When we blit data into a buffer object, we may need to invalidate any
caches that might contain stale data, so the new data becomes visible.

For example, if the buffer object is bound as a vertex buffer, we need
to invalidate the vertex fetch cache.

While this flushing was missing, it usually happened implicitly for
non-obvious reasons: we're usually on the render ring, and calling
intel_emit_linear_blit() would require switching to the BLT ring,
causing an implicit flush.  This likely provoked the kernel to do
PIPE_CONTROLs on our behalf.  Although, Gen4-5 wouldn't have this
behavior.  At any rate, we should do it ourselves.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-30 16:59:23 -07:00
Kenneth Graunke df8f4bfc02 i965: Add PIPE_CONTRTOL_DATA_CACHE flush to brw_emit_mi_flush().
Although we're phasing out brw_emit_mi_flush(), we still use it in some
places in order to "flush everything".  In a number of those places, we
write data to a buffer that we may then bind as an image surface, SSBO,
or atomic buffer.  Those usages require us to flush the data cache.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-30 16:59:22 -07:00
Kenneth Graunke 225425111f i965: Add a brw_blorp_copy_buffers() command.
This exposes the new blorp_copy_buffer() functionality to i965.
It should be a drop-in replacement for intel_emit_linear_blit()
(other than the arguments being backwards, for consistency with BLORP).

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-30 16:59:21 -07:00
Kenneth Graunke fc20df830c blorp: Make blorp_buffer_copy work on Gen4-6.
Gen4-6 can only handle surfaces up to 8192.  Only Gen7+ can do 16384.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-30 16:59:19 -07:00
Kenneth Graunke 81d5b61a19 blorp: Turn anv_CmdCopyBuffer into a blorp_buffer_copy() helper.
I want to be able to copy between buffer objects using BLORP in the i965
driver.  Anvil already had code to do this, in a reasonably efficient
manner - first using large bpp copies, then smaller bpp copies.

This patch moves that logic into BLORP as blorp_buffer_copy(), so we
can use it in both drivers.

Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-08-30 16:59:07 -07:00
Grazvydas Ignotas b8dd69e1b4 radv: don't assert on empty hash table
Currently if table_size is 0, it's falling through to:

unreachable("hash table should never be full");

But table_size can be 0 when RADV_DEBUG=nocache is set, or when the
table allocation fails (which is not considered an error).

Fixes: f4e499ec79 "radv: add initial non-conformant radv vulkan driver"
Signed-off-by: Grazvydas Ignotas <notasas@gmail.com>
Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl>
2017-08-31 02:47:26 +03:00
Brian Paul 5610911fed svga: include sample count in surface_size() computation
Use MAX2() because sampleCount will be zero for non-MSAA surfaces.
No Piglit regressions.

Reviewed-by: Charmaine Lee <charmainel@vmware.com>
2017-08-30 13:59:14 -06:00
Lionel Landwerlin 350ead0f26 i965: drop unused brw->needs_unlit_centroid_workaround
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:18 +01:00
Lionel Landwerlin b1c9ed25a5 i965: drop brw->has_surface_tile_offset in favor of devinfo's
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:18 +01:00
Lionel Landwerlin aff1ad0798 i965: drop unused brw->no_simd8
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:18 +01:00
Lionel Landwerlin 6da7a00a84 i965: drop unused brw->has_pln
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:18 +01:00
Lionel Landwerlin cbee3b03c9 i965: drop brw->must_use_separate_stencil in favor of devinfo's
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:18 +01:00
Lionel Landwerlin 40d20699b7 i965: drop unused brw->has_negative_rhw_bug
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:18 +01:00
Lionel Landwerlin 71493b320d i965: drop unused brw->has_compr4
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:18 +01:00
Lionel Landwerlin a5f0821485 i965: drop brw->has_llc in favor of devinfo->has_llc
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:18 +01:00
Lionel Landwerlin 27e273578f i965: drop brw->is_broxton
We need to take some take here as brw->is_broxton has been used to
check whether the device is a low power gen9 (aka Atom gen9 platform).

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:18 +01:00
Lionel Landwerlin b6e783300c i965: drop brw->is_cherryview in favor of devinfo->is_cherryview
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:17 +01:00
Lionel Landwerlin 97e90113c6 i965: drop brw->is_haswell in favor of devinfo->is_haswell
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:17 +01:00
Lionel Landwerlin d324197de9 i965: drop brw->is_baytrail in favor of devinfo->is_baytrail
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:17 +01:00
Lionel Landwerlin 990c24ad85 i965: drop brw->is_g4x in favor of devinfo->is_g4x
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:17 +01:00
Lionel Landwerlin 46213f676e i965: drop brw->gt in favor of devinfo->gt
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:17 +01:00
Lionel Landwerlin b83a97a65d i965: drop brw->gen in favor of devinfo->gen
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:17 +01:00
Lionel Landwerlin de9649071a anv: use device->info instead of brw->is_*
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 17:59:17 +01:00
Mark Janes 8c9df0daf2 Revert "egl: Allow creation of per surface out fence"
This reverts commit 13c23b19d0.

Mesa CI was brought down by this commit, with:

mesa/drivers/dri/i965/brw_sync.c:491: brw_dri_create_fence_fd:
Assertion `brw->screen->has_exec_fence' failed.
2017-08-30 08:45:36 -07:00
Kevin Rogovin 783f2b70c0 i965: add 2xMSAA 16xMSAA modes to DRI configs.
For Gen8, add 2xMSAA. For Gen9, add 2xMSAA and 16xMSAA.
Special thanks to Eero Tamminen for reporting rasterizer
numbers being twice what it should be for 2xMSAA under
a benchmark.

V2: Make pointer name less ugly + add 2xMSAA for Gen8

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-08-30 08:21:38 -07:00
Kenneth Graunke d808f44ae5 Revert "i965: add 2xMSAA and 16xMSAA to DRI configs for Gen9."
This reverts commit f6d38785e8.

Kevin's original patch accidentally didn't add 2x for Gen8; he sent
a v2 with a bunch of style fixes shortly after I pushed the original
patch, not knowing it was coming.  Let's just revert this one, apply
v2, and move on.
2017-08-30 08:21:38 -07:00
Eric Engestrom ac0d8dc3fa mesa/st: remove unwanted backup file
Fixes: 0ac78dc925 "util: move string_to_uint_map to glsl"
Cc: Emil Velikov <emil.velikov@collabora.com>
Signed-off-by: Eric Engestrom <eric@engestrom.ch>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 14:52:16 +01:00
Michael Olbrich 81d5c31631 egl/dri2: only destroy created objects
dri2_display_destroy may be called by dri2_initialize_wayland_drm() if
initialization fails. In this case, these objects may not be initialized.

Cc: mesa-stable@lists.freedesktop.org
Signed-off-by: Michael Olbrich <m.olbrich@pengutronix.de>
Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
2017-08-30 14:06:49 +01:00
Zhongmin Wu 13c23b19d0 egl: Allow creation of per surface out fence
Add plumbing to allow creation of per display surface out fence.

Currently enabled only on android, since the system expects a valid
fd in ANativeWindow::{queue,cancel}Buffer. We pass a fd of -1 with
which native applications such as flatland fail. The patch enables
explicit sync on android and fixes one of the functional issue for
apps or buffer consumers which depend upon fence and its timestamp.

v2: a) Also implement the fence in cancelBuffer.
    b) The last sync fence is stored in drawable object
       rather than brw context.
    c) format clear.

v3: a) Save the last fence fd in DRI Context object.
    b) Return the last fence if the batch buffer is empty and
       nothing to be flushed when _intel_batchbuffer_flush_fence
    c) Add the new interface in vbtl to set the retrieve fence

v3.1 a) close fd in the new vbtl interface on none Android platform

v4: a) The last fence is saved in brw context.
    b) The retrieve fd is for all the platform but not just Android
    c) Add a uniform dri2 interface to initialize the surface.

v4.1: a) make some changes of variable name.
      b) the patch is broken into two patches.

v4.2: a) Add a deinit interface for surface to clear the out fence

v5: a) Add enable_out_fence to init, platform sets it true or
       false
    b) Change get fd to update fd and check for fence
    c) Commit description updated

v6: a) Heading and commit description updated
    b) enable_out_fence is set only if fence is supported
    c) Review comments on function names
    d) Test with standalone patch, resolves the bug

v6.1: Check for old display fence reverted

v6.2: enable_out_fence initialized to false by default,
      dri2_surf_update_fence_fd updated, deinit changed to fini

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101655

Signed-off-by: Zhongmin Wu <zhongmin.wu@intel.com>
Signed-off-by: Yogesh Marathe <yogesh.marathe@intel.com>
Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Tomasz Figa <tfiga@chromium.org>
2017-08-30 11:55:39 +01:00
Samuel Pitoiset 0d9117b7bd winsys/amdgpu: add BO to the global list only when RADEON_ALL_BOS is set
Only useful when that debug option is enabled.

Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-30 09:33:59 +02:00
Samuel Pitoiset 59101e771d radeonsi: update dirty_level_mask before dispatching
This fixes a rendering issue with Hitman when bindless textures
are enabled.

Fixes: 2263610827 ("radeonsi: flush DB caches only when transitioning from DB to texturing")
Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Reviewed-by: Marek Olšák <marek.olsak@amd.com>
2017-08-30 09:33:55 +02:00
Juan A. Suarez Romero a2234614b6 anv: set right datatypes in anv_pipeline_binding
This structure contains two fields, binding and index, that store the
binding in the descriptor set and the index inside the binding.

These structures are defined as uint8_t, but the types in Vulkan
specification are uint32_t, so big values are clamp.

This fixes dEQP-VK.binding_model.shader_access.*.multiple_arbitrary_descriptors.*

v2: use UINT32_MAX for index when having no render targets (Tapani)

Reviewed-by: Tapani Pälli <tapani.palli@intel.com>
2017-08-30 08:01:53 +02:00
Brian Paul 88cdf16871 llvmpipe: initialize llvmpipe->dirty with LP_NEW_SCISSOR
If llvmpipe_set_scissor_states() is never called, we still need to be sure
that derived scissor/clip state is updated.  As of commit 743ad599a9
that function might not be called.

Fixes regressed Piglit gl-1.0-scissor-offscreen -fbo -auto test.

Reviewed-by: Roland Scheidegger <sroland@vmware.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101709
Fixes: 743ad599a9 ("st/mesa: don't set 16 scissors and 16 viewports
if they're unused")
Cc: "17.2" <mesa-stable@lists.freedesktop.org>
2017-08-29 20:49:36 -06:00
Kenneth Graunke df85a0f54e i965: Bump the initial program cache size from 4kB to 16kB.
Our initial size of 4kB is way too small to do anything useful, so we
end up growing it at least a few times.  We may as well start it larger.

Some data points:

- Dinoshade (from Mesa Demos): hit 8kB.
- Chromium 60: hit 16kB after browsing a few things in Google Docs.
- GFXBench4 TRex/Manhattan 3.1: hit 128kB
- Unigine Valley 1.0: hit 512kB

It might make sense to start it even larger.

Acked-by: Matt Turner <mattst88@gmail.com>
2017-08-29 16:45:16 -07:00
Kenneth Graunke 9a09e4684d i965: Issue performance warnings when growing the program cache
This involves a bunch of unnecessary copying, a batch flush, and
state re-emission.

Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-08-29 16:45:07 -07:00
Kevin Rogovin f6d38785e8 i965: add 2xMSAA and 16xMSAA to DRI configs for Gen9.
Special thanks to Eero Tamminen for reporting rasterizer
numbers being twice what it should be for 2xMSAA under
a benchmark.

Signed-off-by: Kevin Rogovin <kevin.rogovin@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-08-29 16:35:15 -07:00
Matt Turner 8b5b6a8abf glsl: define YY_NO_INPUT to prevent unused symbol warnings
Otherwise clang warns:

glsl/glsl_lexer.cpp:3507:16: warning: function 'yyinput' is not needed
and will not be emitted [-Wunneeded-internal-declaration]
    static int yyinput (yyscan_t yyscanner)
               ^

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-08-29 15:20:57 -07:00
Matt Turner 37f664a066 blorp: Explicitly cast between different enums
Fixes warnings like

warning: implicit conversion from enumeration type 'enum isl_format' to
different enumeration type 'enum GEN10_SURFACE_FORMAT'
[-Wenum-conversion]
         .SourceElementFormat = ISL_FORMAT_R32_UINT,
                                ^~~~~~~~~~~~~~~~~~~

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-08-29 15:20:57 -07:00
Matt Turner b962922fb7 intel/isl: Mark functions used conditionally as UNUSED
The functions we're marking as UNUSED in isl_surface_state.c are used
only when compiling for particular generations.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-08-29 15:20:57 -07:00
Matt Turner c4ce12728e intel/isl: Explicitly cast between different enums
Fixes warnings like

warning: implicit conversion from enumeration type 'enum isl_format' to
different enumeration type 'enum GEN10_SURFACE_FORMAT'
[-Wenum-conversion]
         .SourceElementFormat = ISL_FORMAT_R32_UINT,
                                ^~~~~~~~~~~~~~~~~~~

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-08-29 15:20:57 -07:00
Matt Turner 9fdbc273ef intel/isl: Remove 'inline' keywords
Unless you have data, the compiler knows better than you whether a
function should be inlined.

Unlike all other cases in this series, the removal of the inline keyword
from isl_format_has_channel_type actually changes the resulting binary
with gcc-6.3.0:

   text	   data	    bss	    dec	    hex	filename
7831116	 346384	 420648	8598148	 833284	i965_dri.so before
7830716	 346384	 420648	8597748	 8330f4	i965_dri.so after

I think this is likely an improvement. No difference in the resulting
binary with clang-4.0.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-08-29 15:20:57 -07:00
Matt Turner cdbaa8a12f anv: Mark functions used conditionally as UNUSED
The functions we're marking as UNUSED in genX_pipeline.c are used only
when compiling for particular generations.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-08-29 15:20:57 -07:00
Matt Turner 5d4afef459 anv: Explicitly cast between different enums
Fixes warnings like

warning: implicit conversion from enumeration type 'enum isl_format' to
different enumeration type 'enum GEN10_SURFACE_FORMAT'
[-Wenum-conversion]
         .SourceElementFormat = ISL_FORMAT_R32_UINT,
                                ^~~~~~~~~~~~~~~~~~~

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-08-29 15:20:57 -07:00
Matt Turner 6cfc49287d anv: Remove 'inline' keywords
Unless you have data, the compiler knows better than you whether a
function should be inlined.

No difference in the resulting binary with gcc-6.3.0 or clang-4.0.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-08-29 15:20:57 -07:00
Matt Turner 012887ef48 anv: Use GNU C empty brace initializer
Avoids Clang's warning about the current code:

   warning: suggest braces around initialization of subobject

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-08-29 15:20:57 -07:00
Matt Turner e99dcfd803 i965: Add $(WNO_OVERRIDE_INIT) to AM_CFLAGS
brw_surface_formats.c and genX_blorp_exec.c do this a lot, causing lots
of warnings from clang.

Reviewed-by: Emil Velikov <emil.velikov@collabora.com>
Reviewed-by: Eric Engestrom <eric.engestrom@imgtec.com>
2017-08-29 15:20:57 -07:00