i965: Add PIPE_CONTRTOL_DATA_CACHE flush to brw_emit_mi_flush().
Although we're phasing out brw_emit_mi_flush(), we still use it in some places in order to "flush everything". In a number of those places, we write data to a buffer that we may then bind as an image surface, SSBO, or atomic buffer. Those usages require us to flush the data cache. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
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@ -449,6 +449,7 @@ brw_emit_mi_flush(struct brw_context *brw)
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if (devinfo->gen >= 6) {
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flags |= PIPE_CONTROL_INSTRUCTION_INVALIDATE |
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PIPE_CONTROL_CONST_CACHE_INVALIDATE |
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PIPE_CONTROL_DATA_CACHE_FLUSH |
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PIPE_CONTROL_DEPTH_CACHE_FLUSH |
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PIPE_CONTROL_VF_CACHE_INVALIDATE |
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PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
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